From bf046ba09c9f694517a73af28133917e76d4924a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 18:34:32 -0700
Subject: Add ice40_opt test

---
 tests/ice40/ice40_opt.ys | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 tests/ice40/ice40_opt.ys

(limited to 'tests')

diff --git a/tests/ice40/ice40_opt.ys b/tests/ice40/ice40_opt.ys
new file mode 100644
index 000000000..18e0d2b8a
--- /dev/null
+++ b/tests/ice40/ice40_opt.ys
@@ -0,0 +1,24 @@
+read_verilog -icells -formal <<EOT
+module top(input CI, I0, output CO, O);
+    wire A = 1'b0, B = 1'b0;
+	\$__ICE40_CARRY_WRAPPER #(
+		//    A[0]: 1010 1010 1010 1010
+		//    A[1]: 1100 1100 1100 1100
+		//    A[2]: 1111 0000 1111 0000
+		//    A[3]: 1111 1111 0000 0000
+		.LUT(~16'b 0110_1001_1001_0110)
+	) fadd (
+		.A(A),
+		.B(B),
+		.CI(CI),
+		.I0(I0),
+		.I3(CI),
+		.CO(CO),
+		.O(O)
+	);
+endmodule
+EOT
+
+equiv_opt -assert -map +/ice40/cells_map.v -map +/ice40/cells_sim.v ice40_opt
+design -load postopt
+select -assert-count 1 t:$lut
-- 
cgit v1.2.3


From cd5d6940e1c108b26ef4990accfb49fe7d8534c4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 18:44:57 -0700
Subject: Add SB_CARRY to ice40_opt test

---
 tests/ice40/ice40_opt.ys | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

(limited to 'tests')

diff --git a/tests/ice40/ice40_opt.ys b/tests/ice40/ice40_opt.ys
index 18e0d2b8a..b17c69c91 100644
--- a/tests/ice40/ice40_opt.ys
+++ b/tests/ice40/ice40_opt.ys
@@ -1,5 +1,5 @@
 read_verilog -icells -formal <<EOT
-module top(input CI, I0, output CO, O);
+module top(input CI, I0, output [1:0] CO, output O);
     wire A = 1'b0, B = 1'b0;
 	\$__ICE40_CARRY_WRAPPER #(
 		//    A[0]: 1010 1010 1010 1010
@@ -7,18 +7,20 @@ module top(input CI, I0, output CO, O);
 		//    A[2]: 1111 0000 1111 0000
 		//    A[3]: 1111 1111 0000 0000
 		.LUT(~16'b 0110_1001_1001_0110)
-	) fadd (
+	) u0 (
 		.A(A),
 		.B(B),
 		.CI(CI),
 		.I0(I0),
 		.I3(CI),
-		.CO(CO),
+		.CO(CO[0]),
 		.O(O)
 	);
+    SB_CARRY u1 (.I0(~A), .I1(~B), .CI(CI), .CO(CO[1]));
 endmodule
 EOT
 
 equiv_opt -assert -map +/ice40/cells_map.v -map +/ice40/cells_sim.v ice40_opt
 design -load postopt
+select -assert-count 1 t:*
 select -assert-count 1 t:$lut
-- 
cgit v1.2.3


From 1fdb3fc98cdbd7126f07778397e3c334f45945df Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 19:58:58 -0700
Subject: Add failing test

---
 tests/various/hierarchy_defer.ys | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
 create mode 100644 tests/various/hierarchy_defer.ys

(limited to 'tests')

diff --git a/tests/various/hierarchy_defer.ys b/tests/various/hierarchy_defer.ys
new file mode 100644
index 000000000..170bb8c5f
--- /dev/null
+++ b/tests/various/hierarchy_defer.ys
@@ -0,0 +1,18 @@
+read -vlog2k <<EOT
+module first;
+endmodule
+
+(* top *)
+module top(input i, output o);
+sub s0(i, o);
+endmodule
+
+module sub(input i, output o);
+assign o = ~i;
+endmodule
+EOT
+
+hierarchy -auto-top
+select -assert-any top
+select -assert-any sub
+select -assert-none foo
-- 
cgit v1.2.3


From 67587bad7fb1adf14ca9598bb1a01d0ffda6a018 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 29 Aug 2019 09:10:20 -0700
Subject: Add constant expression attribute to test

---
 tests/various/hierarchy_defer.ys | 1 +
 1 file changed, 1 insertion(+)

(limited to 'tests')

diff --git a/tests/various/hierarchy_defer.ys b/tests/various/hierarchy_defer.ys
index 170bb8c5f..0bf4de44e 100644
--- a/tests/various/hierarchy_defer.ys
+++ b/tests/various/hierarchy_defer.ys
@@ -7,6 +7,7 @@ module top(input i, output o);
 sub s0(i, o);
 endmodule
 
+(* constant_expression=1+1?2*2:3/3 *)
 module sub(input i, output o);
 assign o = ~i;
 endmodule
-- 
cgit v1.2.3


From 7df0e77565ea9dc46d0eeca536d1be47851326e5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 30 Aug 2019 14:35:05 -0700
Subject: Add mul_unsigned test

---
 tests/xilinx/mul_unsigned.v  | 30 ++++++++++++++++++++++++++++++
 tests/xilinx/mul_unsigned.ys | 11 +++++++++++
 2 files changed, 41 insertions(+)
 create mode 100644 tests/xilinx/mul_unsigned.v
 create mode 100644 tests/xilinx/mul_unsigned.ys

(limited to 'tests')

diff --git a/tests/xilinx/mul_unsigned.v b/tests/xilinx/mul_unsigned.v
new file mode 100644
index 000000000..e3713a642
--- /dev/null
+++ b/tests/xilinx/mul_unsigned.v
@@ -0,0 +1,30 @@
+/*
+Example from: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug901-vivado-synthesis.pdf [p. 89].
+*/
+
+// Unsigned 16x24-bit Multiplier
+// 1 latency stage on operands
+// 3 latency stage after the multiplication
+// File: multipliers2.v
+//
+module mul_unsigned (clk, A, B, RES);
+parameter WIDTHA = /*16*/ 6;
+parameter WIDTHB = /*24*/ 9;
+input clk;
+input [WIDTHA-1:0] A;
+input [WIDTHB-1:0] B;
+output [WIDTHA+WIDTHB-1:0] RES;
+reg [WIDTHA-1:0] rA;
+reg [WIDTHB-1:0] rB;
+reg [WIDTHA+WIDTHB-1:0] M [3:0];
+integer i;
+always @(posedge clk)
+ begin
+ rA <= A;
+ rB <= B;
+ M[0] <= rA * rB;
+ for (i = 0; i < 3; i = i+1)
+ M[i+1] <= M[i];
+ end
+assign RES = M[3];
+endmodule
diff --git a/tests/xilinx/mul_unsigned.ys b/tests/xilinx/mul_unsigned.ys
new file mode 100644
index 000000000..72d1f37d7
--- /dev/null
+++ b/tests/xilinx/mul_unsigned.ys
@@ -0,0 +1,11 @@
+read_verilog mul_unsigned.v
+proc
+hierarchy -top mul_unsigned
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mul_unsigned # Constrain all select calls below inside the top module
+stat
+select -assert-count 1 t:BUFG
+select -assert-count 1 t:DSP48E1
+select -assert-count 15 t:SRL16E
+select -assert-none t:DSP48E1 t:SRL16E t:BUFG %% t:* %D
-- 
cgit v1.2.3


From d508dc2906f27b088e9c1c40e7cf2f475e80c15b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 30 Aug 2019 15:01:08 -0700
Subject: Update test for ffM

---
 tests/xilinx/mul_unsigned.ys | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/xilinx/mul_unsigned.ys b/tests/xilinx/mul_unsigned.ys
index 72d1f37d7..30c034afe 100644
--- a/tests/xilinx/mul_unsigned.ys
+++ b/tests/xilinx/mul_unsigned.ys
@@ -7,5 +7,5 @@ cd mul_unsigned # Constrain all select calls below inside the top module
 stat
 select -assert-count 1 t:BUFG
 select -assert-count 1 t:DSP48E1
-select -assert-count 15 t:SRL16E
-select -assert-none t:DSP48E1 t:SRL16E t:BUFG %% t:* %D
+select -assert-count 30 t:FDRE
+select -assert-none t:DSP48E1 t:FDRE t:BUFG %% t:* %D
-- 
cgit v1.2.3


From 9be9631e5acaa570804e1772caae55f5cfc7a918 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 30 Aug 2019 16:18:14 -0700
Subject: Add macc test, with equiv_opt not currently passing

---
 tests/xilinx/macc.v  | 37 +++++++++++++++++++++++++++++++++++++
 tests/xilinx/macc.ys | 17 +++++++++++++++++
 2 files changed, 54 insertions(+)
 create mode 100644 tests/xilinx/macc.v
 create mode 100644 tests/xilinx/macc.ys

(limited to 'tests')

diff --git a/tests/xilinx/macc.v b/tests/xilinx/macc.v
new file mode 100644
index 000000000..bae63b5a4
--- /dev/null
+++ b/tests/xilinx/macc.v
@@ -0,0 +1,37 @@
+// Signed 40-bit streaming accumulator with 16-bit inputs
+// File: HDL_Coding_Techniques/multipliers/multipliers4.v
+//
+module macc # (parameter SIZEIN = /*16*/7, SIZEOUT = 40)
+ (input clk, ce, sload,
+ input signed [SIZEIN-1:0] a, b,
+ output signed [SIZEOUT-1:0] accum_out);
+ // Declare registers for intermediate values
+ reg signed [SIZEIN-1:0] a_reg, b_reg;
+ reg sload_reg;
+ reg signed [2*SIZEIN:0] mult_reg;
+ reg signed [SIZEOUT-1:0] adder_out, old_result;
+ always @(adder_out or sload_reg) begin
+ //if (sload_reg)
+ //old_result <= 0;
+ //else
+ // 'sload' is now active (=low) and opens the accumulation loop.
+ // The accumulator takes the next multiplier output in
+ // the same cycle.
+ old_result <= adder_out;
+ a_reg <= a;
+ b_reg <= b;
+ end
+
+ always @(posedge clk)
+ //if (ce)
+ begin
+ mult_reg <= a_reg * b_reg;
+ sload_reg <= sload;
+ // Store accumulation result into a register
+ adder_out <= old_result + mult_reg;
+ end
+
+ // Output accumulation result
+ assign accum_out = adder_out;
+
+endmodule // macc
diff --git a/tests/xilinx/macc.ys b/tests/xilinx/macc.ys
new file mode 100644
index 000000000..62b69f4d2
--- /dev/null
+++ b/tests/xilinx/macc.ys
@@ -0,0 +1,17 @@
+read_verilog macc.v
+proc
+hierarchy -top macc
+equiv_opt -run :restore -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+
+#equiv_miter -trigger miter equiv
+#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+
+#equiv_opt -assert -run :prove -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+#miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -set-init-zero -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter
+
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd macc # Constrain all select calls below inside the top module
+select -assert-count 1 t:BUFG
+select -assert-count 1 t:DSP48E1
+select -assert-none t:BUFG t:DSP48E1 %% t:* %D
-- 
cgit v1.2.3


From 4290548de35beba766bd7e0684e19de83a0cb2fa Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 30 Aug 2019 20:31:53 -0700
Subject: Make abc9 test a bit more interesting

---
 tests/various/abc9.v | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/various/abc9.v b/tests/various/abc9.v
index a08b613a8..30ebd4e26 100644
--- a/tests/various/abc9.v
+++ b/tests/various/abc9.v
@@ -5,5 +5,7 @@ always @*
 endmodule
 
 module abc9_test028(input i, output o);
-unknown u(~i, o);
+wire w;
+unknown u(~i, w);
+unknown2 u2(w, o);
 endmodule
-- 
cgit v1.2.3


From 69a5dea89ef8cbf8bcc1b761518738623e028e38 Mon Sep 17 00:00:00 2001
From: Emily <vcs@emily.moe>
Date: Tue, 3 Sep 2019 00:57:32 +0100
Subject: Use `command -v` rather than `which`

---
 tests/simple/run-test.sh      | 2 +-
 tests/simple_abc9/run-test.sh | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/simple/run-test.sh b/tests/simple/run-test.sh
index 967ac49f2..f20fd0d30 100755
--- a/tests/simple/run-test.sh
+++ b/tests/simple/run-test.sh
@@ -12,7 +12,7 @@ done
 shift "$((OPTIND-1))"
 
 # check for Icarus Verilog
-if ! which iverilog > /dev/null ; then
+if ! command -v iverilog > /dev/null ; then
   echo "$0: Error: Icarus Verilog 'iverilog' not found."
   exit 1
 fi
diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh
index 8df6994e3..0d4262005 100755
--- a/tests/simple_abc9/run-test.sh
+++ b/tests/simple_abc9/run-test.sh
@@ -12,7 +12,7 @@ done
 shift "$((OPTIND-1))"
 
 # check for Icarus Verilog
-if ! which iverilog > /dev/null ; then
+if ! command -v iverilog > /dev/null ; then
   echo "$0: Error: Icarus Verilog 'iverilog' not found."
   exit 1
 fi
-- 
cgit v1.2.3


From 81247168302a578add43e3e856eb74868dc5a1ba Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 3 Sep 2019 10:52:34 -0700
Subject: Add `read -noverific` before read

---
 tests/various/hierarchy_defer.ys | 1 +
 1 file changed, 1 insertion(+)

(limited to 'tests')

diff --git a/tests/various/hierarchy_defer.ys b/tests/various/hierarchy_defer.ys
index 0bf4de44e..baec52c9d 100644
--- a/tests/various/hierarchy_defer.ys
+++ b/tests/various/hierarchy_defer.ys
@@ -1,3 +1,4 @@
+read -noverific
 read -vlog2k <<EOT
 module first;
 endmodule
-- 
cgit v1.2.3


From 0ca070663091ec0eecd089801f37339feb7813c8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 3 Sep 2019 12:17:26 -0700
Subject: Expand test with `hierarchy' without -auto-top

---
 tests/various/hierarchy_defer.ys | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'tests')

diff --git a/tests/various/hierarchy_defer.ys b/tests/various/hierarchy_defer.ys
index baec52c9d..70f5b70a3 100644
--- a/tests/various/hierarchy_defer.ys
+++ b/tests/various/hierarchy_defer.ys
@@ -13,8 +13,15 @@ module sub(input i, output o);
 assign o = ~i;
 endmodule
 EOT
+design -save read
 
 hierarchy -auto-top
 select -assert-any top
 select -assert-any sub
 select -assert-none foo
+
+design -load read
+hierarchy
+select -assert-any top
+select -assert-any sub
+select -assert-none foo
-- 
cgit v1.2.3


From 0cee66e7591b6315f9e7dce91b789c1f6b53138f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 4 Sep 2019 12:34:44 -0700
Subject: Add peepopt_dffmuxext tests

---
 tests/simple/peepopt.v | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'tests')

diff --git a/tests/simple/peepopt.v b/tests/simple/peepopt.v
index 1bf427897..b4d113dba 100644
--- a/tests/simple/peepopt.v
+++ b/tests/simple/peepopt.v
@@ -11,3 +11,11 @@ wire [3:0] t;
 assign t = i * 3;
 assign o = t / 3;
 endmodule
+
+module peepopt_dffmuxext_signed(input clk, ce, input signed [1:0] i, output reg signed [3:0] o);
+    always @(posedge clk) if (ce) o <= i;
+endmodule
+
+module peepopt_dffmuxext_unsigned(input clk, ce, input [1:0] i, output reg [3:0] o);
+    always @(posedge clk) if (ce) o <= i;
+endmodule
-- 
cgit v1.2.3


From 6fe1ca633d90fb238d2671dba3d7f772c263a497 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 4 Sep 2019 15:20:04 -0700
Subject: abc9 followed by clean otherwise netlist could be invalid for sim

---
 tests/simple_abc9/run-test.sh | 1 +
 1 file changed, 1 insertion(+)

(limited to 'tests')

diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh
index 0d4262005..4d15a3253 100755
--- a/tests/simple_abc9/run-test.sh
+++ b/tests/simple_abc9/run-test.sh
@@ -25,5 +25,6 @@ exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-n 300 -p '\
     synth -run coarse; \
     opt -full; \
     techmap; abc9 -lut 4 -box ../abc.box; \
+    clean; \
     check -assert; \
     select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'"
-- 
cgit v1.2.3


From 11f623cbe0057ee752f2545eb7100966afb08676 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 5 Sep 2019 08:25:09 -0700
Subject: Revert "abc9 followed by clean otherwise netlist could be invalid for
 sim"

This reverts commit 6fe1ca633d90fb238d2671dba3d7f772c263a497.
---
 tests/simple_abc9/run-test.sh | 1 -
 1 file changed, 1 deletion(-)

(limited to 'tests')

diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh
index 4d15a3253..0d4262005 100755
--- a/tests/simple_abc9/run-test.sh
+++ b/tests/simple_abc9/run-test.sh
@@ -25,6 +25,5 @@ exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-n 300 -p '\
     synth -run coarse; \
     opt -full; \
     techmap; abc9 -lut 4 -box ../abc.box; \
-    clean; \
     check -assert; \
     select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'"
-- 
cgit v1.2.3


From ef0681ea4ca0b34689cbf14d5a4478e2785600d9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 5 Sep 2019 08:43:22 -0700
Subject: simple/peepopt.v tests to various/peepopt.ys with equiv_opt & select

---
 tests/simple/peepopt.v   | 21 ----------------
 tests/various/peepopt.ys | 63 ++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 63 insertions(+), 21 deletions(-)
 delete mode 100644 tests/simple/peepopt.v
 create mode 100644 tests/various/peepopt.ys

(limited to 'tests')

diff --git a/tests/simple/peepopt.v b/tests/simple/peepopt.v
deleted file mode 100644
index b4d113dba..000000000
--- a/tests/simple/peepopt.v
+++ /dev/null
@@ -1,21 +0,0 @@
-module peepopt_shiftmul_0 #(parameter N=3, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output [W-1:0] o);
-assign o = i[s*W+:W];
-endmodule
-
-module peepopt_shiftmul_1 (output y, input [2:0] w);
-assign y = 1'b1 >> (w * (3'b110));
-endmodule
-
-module peepopt_muldiv_0(input [1:0] i, output [1:0] o);
-wire [3:0] t;
-assign t = i * 3;
-assign o = t / 3;
-endmodule
-
-module peepopt_dffmuxext_signed(input clk, ce, input signed [1:0] i, output reg signed [3:0] o);
-    always @(posedge clk) if (ce) o <= i;
-endmodule
-
-module peepopt_dffmuxext_unsigned(input clk, ce, input [1:0] i, output reg [3:0] o);
-    always @(posedge clk) if (ce) o <= i;
-endmodule
diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys
new file mode 100644
index 000000000..91db22423
--- /dev/null
+++ b/tests/various/peepopt.ys
@@ -0,0 +1,63 @@
+read_verilog <<EOT
+module peepopt_shiftmul_0 #(parameter N=3, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output [W-1:0] o);
+assign o = i[s*W+:W];
+endmodule
+EOT
+
+prep -nokeepdc
+equiv_opt peepopt
+design -load postopt
+clean
+select -assert-count 1 t:$shiftx
+select -assert-count 0 t:$shiftx t:* %D
+
+####################
+
+design -reset
+read_verilog <<EOT
+module peepopt_shiftmul_1 (output [7:0] y, input [2:0] w);
+assign y = 1'b1 >> (w * (3'b110));
+endmodule
+EOT
+
+prep -nokeepdc
+equiv_opt peepopt
+design -load postopt
+clean
+select -assert-count 1 t:$shr
+select -assert-count 1 t:$mul
+select -assert-count 0 t:$shr t:$mul %% t:* %D
+
+####################
+
+design -reset
+read_verilog <<EOT
+module peepopt_muldiv_0(input [1:0] i, output [1:0] o);
+wire [3:0] t;
+assign t = i * 3;
+assign o = t / 3;
+endmodule
+EOT
+
+prep -nokeepdc
+equiv_opt peepopt
+design -load postopt
+clean
+select -assert-count 0 t:*
+
+####################
+
+design -reset
+read_verilog <<EOT
+module peepopt_dffmuxext_signed(input clk, ce, input signed [1:0] i, output reg signed [3:0] o);
+    always @(posedge clk) if (ce) o <= i;
+endmodule
+EOT
+
+prep -nokeepdc
+equiv_opt peepopt
+design -load postopt
+clean
+select -assert-count 1 t:$dff r:WIDTH=2 %i
+select -assert-count 1 t:$mux r:WIDTH=2 %i
+select -assert-count 0 t:$dff t:$mux %% t:* %D
-- 
cgit v1.2.3


From 51b559af2cc60226d85880efc3705f0860ffaed6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 6 Sep 2019 22:48:04 -0700
Subject: Usee equiv_opt -assert

---
 tests/various/peepopt.ys | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'tests')

diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys
index 91db22423..a476133a2 100644
--- a/tests/various/peepopt.ys
+++ b/tests/various/peepopt.ys
@@ -5,7 +5,7 @@ endmodule
 EOT
 
 prep -nokeepdc
-equiv_opt peepopt
+equiv_opt -assert peepopt
 design -load postopt
 clean
 select -assert-count 1 t:$shiftx
@@ -21,7 +21,7 @@ endmodule
 EOT
 
 prep -nokeepdc
-equiv_opt peepopt
+equiv_opt -assert peepopt
 design -load postopt
 clean
 select -assert-count 1 t:$shr
@@ -40,7 +40,7 @@ endmodule
 EOT
 
 prep -nokeepdc
-equiv_opt peepopt
+equiv_opt -assert peepopt
 design -load postopt
 clean
 select -assert-count 0 t:*
-- 
cgit v1.2.3


From e2c2d784c8217e4bcf29fb6b156b6a8285036b80 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 6 Sep 2019 22:48:23 -0700
Subject: Make one check $shift(x)? only; change testcase to be 8b

---
 tests/various/peepopt.ys | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys
index a476133a2..dcf3cacbd 100644
--- a/tests/various/peepopt.ys
+++ b/tests/various/peepopt.ys
@@ -16,7 +16,7 @@ select -assert-count 0 t:$shiftx t:* %D
 design -reset
 read_verilog <<EOT
 module peepopt_shiftmul_1 (output [7:0] y, input [2:0] w);
-assign y = 1'b1 >> (w * (3'b110));
+assign y = 1'b1 >> (w * (8'b110));
 endmodule
 EOT
 
@@ -25,7 +25,7 @@ equiv_opt -assert peepopt
 design -load postopt
 clean
 select -assert-count 1 t:$shr
-select -assert-count 1 t:$mul
+select -assert-count 0 t:$mul
 select -assert-count 0 t:$shr t:$mul %% t:* %D
 
 ####################
-- 
cgit v1.2.3


From 97e1520b13231c8170cec73774eee7a22c5dc065 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 6 Sep 2019 22:50:03 -0700
Subject: Missing equiv_opt -assert

---
 tests/various/peepopt.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys
index dcf3cacbd..33555264d 100644
--- a/tests/various/peepopt.ys
+++ b/tests/various/peepopt.ys
@@ -55,7 +55,7 @@ endmodule
 EOT
 
 prep -nokeepdc
-equiv_opt peepopt
+equiv_opt -assert peepopt
 design -load postopt
 clean
 select -assert-count 1 t:$dff r:WIDTH=2 %i
-- 
cgit v1.2.3


From 173c7936c3c329917ca8eb929163a03aab51811e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 6 Sep 2019 22:51:44 -0700
Subject: Add missing -assert to equiv_opt

---
 tests/opt/opt_expr.ys | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

(limited to 'tests')

diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys
index ecc2c8da8..e0acead82 100644
--- a/tests/opt/opt_expr.ys
+++ b/tests/opt/opt_expr.ys
@@ -204,7 +204,7 @@ endmodule
 EOT
 check
 
-equiv_opt opt_expr -fine
+equiv_opt -assert opt_expr -fine
 design -load postopt
 select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
 
@@ -218,7 +218,7 @@ endmodule
 EOT
 check
 
-equiv_opt opt_expr -fine
+equiv_opt -assert opt_expr -fine
 design -load postopt
 select -assert-count 1 t:$alu r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
 
@@ -232,7 +232,7 @@ endmodule
 EOT
 check
 
-equiv_opt opt_expr
+equiv_opt -assert opt_expr
 design -load postopt
 select -assert-count 1 t:$shiftx r:A_WIDTH=3 %i
 
@@ -246,7 +246,7 @@ endmodule
 EOT
 check
 
-equiv_opt opt_expr
+equiv_opt -assert opt_expr
 design -load postopt
 select -assert-count 1 t:$shiftx r:A_WIDTH=12 %i
 
@@ -260,7 +260,7 @@ endmodule
 EOT
 check
 
-equiv_opt opt_expr
+equiv_opt -assert opt_expr
 design -load postopt
 select -assert-count 1 t:$shift r:A_WIDTH=3 %i
 
@@ -274,7 +274,7 @@ endmodule
 EOT
 check
 
-equiv_opt opt_expr
+equiv_opt -assert opt_expr
 design -load postopt
 select -assert-count 1 t:$shift r:A_WIDTH=10 %i
 
@@ -288,6 +288,6 @@ endmodule
 EOT
 check
 
-equiv_opt opt_expr -keepdc
+equiv_opt -assert opt_expr -keepdc
 design -load postopt
 select -assert-count 1 t:$shift r:A_WIDTH=13 %i
-- 
cgit v1.2.3


From e68507a71603553426a338bcffb0eccb1653436f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 6 Sep 2019 23:19:03 -0700
Subject: Update macc test

---
 tests/xilinx/macc.v  | 66 ++++++++++++++++++++++++++++------------------------
 tests/xilinx/macc.ys | 18 ++++++--------
 2 files changed, 42 insertions(+), 42 deletions(-)

(limited to 'tests')

diff --git a/tests/xilinx/macc.v b/tests/xilinx/macc.v
index bae63b5a4..0bb673316 100644
--- a/tests/xilinx/macc.v
+++ b/tests/xilinx/macc.v
@@ -1,37 +1,41 @@
 // Signed 40-bit streaming accumulator with 16-bit inputs
 // File: HDL_Coding_Techniques/multipliers/multipliers4.v
 //
-module macc # (parameter SIZEIN = /*16*/7, SIZEOUT = 40)
- (input clk, ce, sload,
- input signed [SIZEIN-1:0] a, b,
- output signed [SIZEOUT-1:0] accum_out);
- // Declare registers for intermediate values
- reg signed [SIZEIN-1:0] a_reg, b_reg;
- reg sload_reg;
- reg signed [2*SIZEIN:0] mult_reg;
- reg signed [SIZEOUT-1:0] adder_out, old_result;
- always @(adder_out or sload_reg) begin
- //if (sload_reg)
- //old_result <= 0;
- //else
- // 'sload' is now active (=low) and opens the accumulation loop.
- // The accumulator takes the next multiplier output in
- // the same cycle.
- old_result <= adder_out;
- a_reg <= a;
- b_reg <= b;
- end
+// Source:
+// https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug901-vivado-synthesis.pdf p.90
+//
+module macc # (parameter SIZEIN = 16, SIZEOUT = 40) (
+	input clk, ce, sload,
+	input signed [SIZEIN-1:0] a, b,
+	output signed [SIZEOUT-1:0] accum_out
+);
+// Declare registers for intermediate values
+reg signed [SIZEIN-1:0] a_reg, b_reg;
+reg sload_reg;
+reg signed [2*SIZEIN-1:0] mult_reg;
+reg signed [SIZEOUT-1:0] adder_out, old_result;
+always @* /*(adder_out or sload_reg)*/ begin // Modification necessary to fix sim/synth mismatch
+	if (sload_reg)
+		old_result <= 0;
+	else
+		// 'sload' is now active (=low) and opens the accumulation loop.
+		// The accumulator takes the next multiplier output in
+		// the same cycle.
+		old_result <= adder_out;
+end
 
- always @(posedge clk)
- //if (ce)
- begin
- mult_reg <= a_reg * b_reg;
- sload_reg <= sload;
- // Store accumulation result into a register
- adder_out <= old_result + mult_reg;
- end
+always @(posedge clk)
+	if (ce)
+	begin
+		a_reg <= a;
+		b_reg <= b;
+		mult_reg <= a_reg * b_reg;
+		sload_reg <= sload;
+		// Store accumulation result into a register
+		adder_out <= old_result + mult_reg;
+	end
 
- // Output accumulation result
- assign accum_out = adder_out;
+	// Output accumulation result
+	assign accum_out = adder_out;
 
-endmodule // macc
+endmodule
diff --git a/tests/xilinx/macc.ys b/tests/xilinx/macc.ys
index 62b69f4d2..de408162c 100644
--- a/tests/xilinx/macc.ys
+++ b/tests/xilinx/macc.ys
@@ -1,17 +1,13 @@
 read_verilog macc.v
 proc
-hierarchy -top macc
-equiv_opt -run :restore -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-
-#equiv_miter -trigger miter equiv
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
-
-#equiv_opt -assert -run :prove -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-#miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -set-init-zero -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter
-
+hierarchy -auto-top
+#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd macc # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
+select -assert-count 1 t:FDRE
 select -assert-count 1 t:DSP48E1
-select -assert-none t:BUFG t:DSP48E1 %% t:* %D
+select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D
-- 
cgit v1.2.3


From a82e8df7d37c02258d36223bb16833331dc8808e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= <koriakin@0x04.net>
Date: Fri, 16 Aug 2019 03:14:03 +0000
Subject: techmap: Add support for extracting init values of ports

---
 tests/techmap/wireinit.ys | 98 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 98 insertions(+)
 create mode 100644 tests/techmap/wireinit.ys

(limited to 'tests')

diff --git a/tests/techmap/wireinit.ys b/tests/techmap/wireinit.ys
new file mode 100644
index 000000000..1396839fe
--- /dev/null
+++ b/tests/techmap/wireinit.ys
@@ -0,0 +1,98 @@
+read_verilog <<EOT
+(* techmap_celltype = "$_DFF_P_" *)
+module ffmap(...);
+input D;
+input C;
+output Q;
+parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+
+ffbb #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_(.D(D), .Q(Q), .C(C));
+
+wire _TECHMAP_FAIL_ = _TECHMAP_WIREINIT_Q_ === 1'b1;
+
+wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
+
+endmodule
+EOT
+design -stash map
+
+read_verilog <<EOT
+(* techmap_celltype = "$_DFF_P_" *)
+module ffmap(...);
+input D;
+input C;
+output Q;
+parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
+
+ffbb #(.INIT(_TECHMAP_WIREINIT_Q_)) _TECHMAP_REPLACE_(.D(D), .Q(Q), .C(C));
+
+wire _TECHMAP_FAIL_ = _TECHMAP_WIREINIT_Q_ === 1'b1;
+
+wire _TECHMAP_REMOVEINIT_Q_ = 1'b0;
+
+endmodule
+EOT
+design -stash map_noremove
+
+read_verilog <<EOT
+module ffbb (...);
+parameter [0:0] INIT = 1'bx;
+input D, C;
+output Q;
+endmodule
+
+module top(...);
+input clk;
+input d;
+output reg q0 = 0;
+output reg q1 = 1;
+output reg qx;
+
+always @(posedge clk) begin
+	q0 <= d;
+	q1 <= d;
+	qx <= d;
+end
+endmodule
+EOT
+
+design -save ref
+
+hierarchy -auto-top
+proc
+simplemap
+techmap -map %map
+clean
+# Make sure the parameter was used properly.
+select -assert-count 2 top/t:ffbb
+select -set ff0 top/w:q0 %ci t:ffbb %i
+select -set ffx top/w:qx %ci t:ffbb %i
+select -assert-count 1 @ff0
+select -assert-count 1 @ffx
+select -assert-count 1 @ff0 r:INIT=1'b0 %i
+select -assert-count 1 @ffx r:INIT=1'bx %i
+select -assert-count 0 top/w:q1 %ci t:ffbb %i
+# Make sure the init values are dropped from the wires iff mapping was performed.
+select -assert-count 0 top/w:q0 a:init %i
+select -assert-count 1 top/w:q1 a:init=1'b1 %i
+select -assert-count 0 top/w:qx a:init %i
+
+design -load ref
+hierarchy -auto-top
+proc
+simplemap
+techmap -map %map_noremove
+clean
+# Make sure the parameter was used properly.
+select -assert-count 2 top/t:ffbb
+select -set ff0 top/w:q0 %ci t:ffbb %i
+select -set ffx top/w:qx %ci t:ffbb %i
+select -assert-count 1 @ff0
+select -assert-count 1 @ffx
+select -assert-count 1 @ff0 r:INIT=1'b0 %i
+select -assert-count 1 @ffx r:INIT=1'bx %i
+select -assert-count 0 top/w:q1 %ci t:ffbb %i
+# Make sure the init values are not dropped from the wires.
+select -assert-count 1 top/w:q0 a:init=1'b0 %i
+select -assert-count 1 top/w:q1 a:init=1'b1 %i
+select -assert-count 0 top/w:qx a:init %i
-- 
cgit v1.2.3


From 702ce405c18c2c28e7f5d354451141d8f16a4085 Mon Sep 17 00:00:00 2001
From: Sean Cross <sean@xobs.io>
Date: Tue, 10 Sep 2019 08:47:16 +0800
Subject: tests: ice40: fix div_mod SB_LUT4 count

This test is failing due to one of the changes present in this patchset.
Adjust the test to match the newly-observed values.

https://github.com/xobs/yosys/compare/smtbmc-msvc2-build-fixes...YosysHQ:xobs/pr1362

Signed-off-by: Sean Cross <sean@xobs.io>
---
 tests/ice40/div_mod.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys
index 21cac7144..821d6c301 100644
--- a/tests/ice40/div_mod.ys
+++ b/tests/ice40/div_mod.ys
@@ -4,6 +4,6 @@ flatten
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
-select -assert-count 62 t:SB_LUT4
+select -assert-count 59 t:SB_LUT4
 select -assert-count 41 t:SB_CARRY
 select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D
-- 
cgit v1.2.3


From 1fc50a03fcaeebc0d1b12f397c2d31bcd27df715 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 9 Sep 2019 21:40:06 -0700
Subject: Add SIMD test

---
 tests/xilinx/dsp_simd.ys | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)
 create mode 100644 tests/xilinx/dsp_simd.ys

(limited to 'tests')

diff --git a/tests/xilinx/dsp_simd.ys b/tests/xilinx/dsp_simd.ys
new file mode 100644
index 000000000..956952327
--- /dev/null
+++ b/tests/xilinx/dsp_simd.ys
@@ -0,0 +1,25 @@
+read_verilog <<EOT
+module simd(input [12*4-1:0] a, input [12*4-1:0] b, (* use_dsp="simd" *) output [7*12-1:0] o12, (* use_dsp="simd" *) output [2*24-1:0] o24);
+generate
+    genvar i;
+    // 4 x 12-bit adder
+    for (i = 0; i < 4; i++)
+        assign o12[i*12+:12] = a[i*12+:12] + b[i*12+:12];
+    // 2 x 24-bit subtract
+    for (i = 0; i < 2; i++)
+        assign o24[i*24+:24] = a[i*24+:24] - b[i*24+:24];
+endgenerate
+reg [3*12-1:0] ro;
+always @* begin
+    ro[0*12+:12] = a[0*10+:10] + b[0*10+:10];
+    ro[1*12+:12] = a[1*10+:10] + b[1*10+:10];
+    ro[2*12+:12] = a[2*8+:8] + b[2*8+:8];
+end
+assign o12[4*12+:3*12] = ro;
+endmodule
+EOT
+
+proc
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx
+design -load postopt
+select -assert-count 3 t:DSP48E1
-- 
cgit v1.2.3


From 580faae8ad608981ef6ef6a99ca6b771dc0368ae Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 11 Sep 2019 00:07:17 -0700
Subject: Add unsigned case

---
 tests/various/peepopt.ys | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

(limited to 'tests')

diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys
index 33555264d..e930015a4 100644
--- a/tests/various/peepopt.ys
+++ b/tests/various/peepopt.ys
@@ -47,6 +47,23 @@ select -assert-count 0 t:*
 
 ####################
 
+design -reset
+read_verilog <<EOT
+module peepopt_dffmuxext_unsigned(input clk, ce, input [1:0] i, output reg [3:0] o);
+    always @(posedge clk) if (ce) o <= i;
+endmodule
+EOT
+
+prep -nokeepdc
+equiv_opt -assert peepopt
+design -load postopt
+clean
+select -assert-count 1 t:$dff r:WIDTH=2 %i
+select -assert-count 1 t:$mux r:WIDTH=2 %i
+select -assert-count 0 t:$dff t:$mux %% t:* %D
+
+####################
+
 design -reset
 read_verilog <<EOT
 module peepopt_dffmuxext_signed(input clk, ce, input signed [1:0] i, output reg signed [3:0] o);
-- 
cgit v1.2.3


From 3a8582081e1eda7e4a41ec1ec7292e7d247559da Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 11 Sep 2019 00:14:06 -0700
Subject: proc instead of prep

---
 tests/various/peepopt.ys | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys
index e930015a4..2a660d5c9 100644
--- a/tests/various/peepopt.ys
+++ b/tests/various/peepopt.ys
@@ -54,7 +54,7 @@ module peepopt_dffmuxext_unsigned(input clk, ce, input [1:0] i, output reg [3:0]
 endmodule
 EOT
 
-prep -nokeepdc
+proc
 equiv_opt -assert peepopt
 design -load postopt
 clean
@@ -71,7 +71,7 @@ module peepopt_dffmuxext_signed(input clk, ce, input signed [1:0] i, output reg
 endmodule
 EOT
 
-prep -nokeepdc
+proc
 equiv_opt -assert peepopt
 design -load postopt
 clean
-- 
cgit v1.2.3


From c43e52d2d7d16c26b1a4a9c20fad83c9f4577910 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Wed, 11 Sep 2019 13:55:16 +0100
Subject: Add equiv_opt -multiclock

Signed-off-by: David Shah <dave@ds0.me>
---
 tests/various/equiv_opt_multiclock.ys | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 tests/various/equiv_opt_multiclock.ys

(limited to 'tests')

diff --git a/tests/various/equiv_opt_multiclock.ys b/tests/various/equiv_opt_multiclock.ys
new file mode 100644
index 000000000..81e36d018
--- /dev/null
+++ b/tests/various/equiv_opt_multiclock.ys
@@ -0,0 +1,12 @@
+read_verilog <<EOT
+module top(input clk, pre, d, output reg q);
+	always @(posedge clk, posedge pre)
+		if (pre)
+			q <= 1'b1;
+		else
+			q <= d;
+endmodule
+EOT
+
+prep
+equiv_opt -assert -multiclock -map +/simcells.v synth
-- 
cgit v1.2.3


From 36d6db7f8aac6568acc2fb2d4ea5a5427d00d667 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 11 Sep 2019 09:09:08 -0700
Subject: Extend test for RSTP and RSTM

---
 tests/xilinx/macc.v  | 36 ++++++++++++++++++++++++++++++++++--
 tests/xilinx/macc.ys | 17 ++++++++++++++++-
 2 files changed, 50 insertions(+), 3 deletions(-)

(limited to 'tests')

diff --git a/tests/xilinx/macc.v b/tests/xilinx/macc.v
index 0bb673316..c6ad2a578 100644
--- a/tests/xilinx/macc.v
+++ b/tests/xilinx/macc.v
@@ -35,7 +35,39 @@ always @(posedge clk)
 		adder_out <= old_result + mult_reg;
 	end
 
-	// Output accumulation result
-	assign accum_out = adder_out;
+// Output accumulation result
+assign accum_out = adder_out;
+
+endmodule
+
+// Adapted variant of above
+module macc2 # (parameter SIZEIN = 16, SIZEOUT = 40) (
+	input clk, ce, rst,
+	input signed [SIZEIN-1:0] a, b,
+	output signed [SIZEOUT-1:0] accum_out
+);
+// Declare registers for intermediate values
+reg signed [SIZEIN-1:0] a_reg, b_reg;
+reg rst_reg;
+reg signed [2*SIZEIN-1:0] mult_reg;
+reg signed [SIZEOUT-1:0] adder_out, old_result;
+always @(posedge clk) begin
+	if (ce)
+	begin
+		a_reg <= a;
+		b_reg <= b;
+		mult_reg <= a_reg * b_reg;
+		rst_reg <= rst;
+		// Store accumulation result into a register
+		adder_out <= adder_out + mult_reg;
+	end
+    if (rst) begin
+		mult_reg <= 0;
+		adder_out <= 0;
+    end
+end
+
+// Output accumulation result
+assign accum_out = adder_out;
 
 endmodule
diff --git a/tests/xilinx/macc.ys b/tests/xilinx/macc.ys
index de408162c..294b83c69 100644
--- a/tests/xilinx/macc.ys
+++ b/tests/xilinx/macc.ys
@@ -1,6 +1,8 @@
 read_verilog macc.v
+design -save read
+
 proc
-hierarchy -auto-top
+hierarchy -top macc
 #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO
 equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
@@ -11,3 +13,16 @@ select -assert-count 1 t:BUFG
 select -assert-count 1 t:FDRE
 select -assert-count 1 t:DSP48E1
 select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D
+
+design -load read
+proc
+hierarchy -top macc2
+#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd macc2 # Constrain all select calls below inside the top module
+select -assert-count 1 t:BUFG
+select -assert-count 1 t:DSP48E1
+select -assert-none t:BUFG t:DSP48E1 %% t:* %D
-- 
cgit v1.2.3


From 6a95ecd41d31a841537357a1ffaabf4ea5c7ed93 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 11 Sep 2019 10:13:13 -0700
Subject: Update test with a/b reset

---
 tests/xilinx/macc.v | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/xilinx/macc.v b/tests/xilinx/macc.v
index c6ad2a578..5dc99ab8e 100644
--- a/tests/xilinx/macc.v
+++ b/tests/xilinx/macc.v
@@ -61,10 +61,12 @@ always @(posedge clk) begin
 		// Store accumulation result into a register
 		adder_out <= adder_out + mult_reg;
 	end
-    if (rst) begin
+	if (rst) begin
+		a_reg <= 0;
+		b_reg <= 0;
 		mult_reg <= 0;
 		adder_out <= 0;
-    end
+	end
 end
 
 // Output accumulation result
-- 
cgit v1.2.3


From f72765090cd001ff4dc54d5a9c01a2d4b3339865 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= <koriakin@0x04.net>
Date: Tue, 10 Sep 2019 16:31:50 +0000
Subject: Add -match-init option to dff2dffs.

---
 tests/techmap/dff2dffs.ys | 50 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)
 create mode 100644 tests/techmap/dff2dffs.ys

(limited to 'tests')

diff --git a/tests/techmap/dff2dffs.ys b/tests/techmap/dff2dffs.ys
new file mode 100644
index 000000000..13f1a3cf3
--- /dev/null
+++ b/tests/techmap/dff2dffs.ys
@@ -0,0 +1,50 @@
+read_verilog << EOT
+module top(...);
+input clk;
+input d;
+input sr;
+output reg q0, q1, q2, q3, q4, q5;
+
+initial q0 = 1'b0;
+initial q1 = 1'b0;
+initial q2 = 1'b1;
+initial q3 = 1'b1;
+initial q4 = 1'bx;
+initial q5 = 1'bx;
+
+always @(posedge clk) begin
+	q0 <= sr ? 1'b0 : d;
+	q1 <= sr ? 1'b1 : d;
+	q2 <= sr ? 1'b0 : d;
+	q3 <= sr ? 1'b1 : d;
+	q4 <= sr ? 1'b0 : d;
+	q5 <= sr ? 1'b1 : d;
+end
+
+endmodule
+EOT
+
+proc
+simplemap
+design -save ref
+
+dff2dffs
+clean
+
+select -assert-count 1 w:q0 %x t:$__DFFS_PP0_ %i
+select -assert-count 1 w:q1 %x t:$__DFFS_PP1_ %i
+select -assert-count 1 w:q2 %x t:$__DFFS_PP0_ %i
+select -assert-count 1 w:q3 %x t:$__DFFS_PP1_ %i
+select -assert-count 1 w:q4 %x t:$__DFFS_PP0_ %i
+select -assert-count 1 w:q5 %x t:$__DFFS_PP1_ %i
+
+design -load ref
+dff2dffs -match-init
+clean
+
+select -assert-count 1 w:q0 %x t:$__DFFS_PP0_ %i
+select -assert-count 0 w:q1 %x t:$__DFFS_PP1_ %i
+select -assert-count 0 w:q2 %x t:$__DFFS_PP0_ %i
+select -assert-count 1 w:q3 %x t:$__DFFS_PP1_ %i
+select -assert-count 1 w:q4 %x t:$__DFFS_PP0_ %i
+select -assert-count 1 w:q5 %x t:$__DFFS_PP1_ %i
-- 
cgit v1.2.3


From f46ef47893b4d2cb01fc5914fe0ee89d206f686f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 11 Sep 2019 13:22:41 -0700
Subject: Add more tests

---
 tests/various/peepopt.ys | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

(limited to 'tests')

diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys
index 2a660d5c9..8dce679ff 100644
--- a/tests/various/peepopt.ys
+++ b/tests/various/peepopt.ys
@@ -78,3 +78,35 @@ clean
 select -assert-count 1 t:$dff r:WIDTH=2 %i
 select -assert-count 1 t:$mux r:WIDTH=2 %i
 select -assert-count 0 t:$dff t:$mux %% t:* %D
+
+###################
+
+design -reset
+read_verilog <<EOT
+module peepopt_dffmuxext_const(input clk, ce, input [1:0] i, output reg [5:0] o);
+    always @(posedge clk) if (ce) o <= {1'b0, i[1], 2'b1x, i[0], 1'bz};
+endmodule
+EOT
+
+proc
+equiv_opt -assert peepopt
+design -load postopt
+select -assert-count 1 t:$dff r:WIDTH=2 %i
+select -assert-count 1 t:$mux r:WIDTH=2 %i
+select -assert-count 0 t:$dff t:$mux %% t:* %D
+
+###################
+
+design -reset
+read_verilog <<EOT
+module peepopt_dffmuxext_const_init(input clk, ce, input [1:0] i, (* init=6'b0x00x1 *) output reg [5:0] o);
+    always @(posedge clk) if (ce) o <= {1'b0, i[1], 2'b1x, i[0], 1'bz};
+endmodule
+EOT
+
+proc
+equiv_opt -assert peepopt
+design -load postopt
+select -assert-count 1 t:$dff r:WIDTH=5 %i
+select -assert-count 1 t:$mux r:WIDTH=5 %i
+select -assert-count 0 t:$dff t:$mux %% t:* %D
-- 
cgit v1.2.3


From bdb5e0f29c3e913fb4e701317105363064b9a7d3 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 11 Sep 2019 13:36:37 -0700
Subject: Cope with presence of reset muxes too

---
 tests/various/peepopt.ys | 39 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

(limited to 'tests')

diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys
index 8dce679ff..886c8cd9d 100644
--- a/tests/various/peepopt.ys
+++ b/tests/various/peepopt.ys
@@ -110,3 +110,42 @@ design -load postopt
 select -assert-count 1 t:$dff r:WIDTH=5 %i
 select -assert-count 1 t:$mux r:WIDTH=5 %i
 select -assert-count 0 t:$dff t:$mux %% t:* %D
+
+####################
+
+design -reset
+read_verilog <<EOT
+module peepopt_dffmuxext_unsigned_rst(input clk, ce, rst, input [1:0] i, output reg [3:0] o);
+    always @(posedge clk) if (rst) o <= 0; else if (ce) o <= i;
+endmodule
+EOT
+
+proc
+equiv_opt -assert peepopt
+design -load postopt
+wreduce
+select -assert-count 1 t:$dff r:WIDTH=2 %i
+select -assert-count 2 t:$mux
+select -assert-count 2 t:$mux r:WIDTH=2 %i
+select -assert-count 0 t:$dff t:$mux %% t:* %D
+
+####################
+
+design -reset
+read_verilog <<EOT
+module peepopt_dffmuxext_signed_rst(input clk, ce, rstn, input signed [1:0] i, output reg signed [3:0] o);
+    always @(posedge clk) begin
+        if (ce) o <= i;
+        if (!rstn) o <= 4'b1111;
+    end
+endmodule
+EOT
+
+proc
+equiv_opt -assert peepopt
+design -load postopt
+wreduce
+select -assert-count 1 t:$dff r:WIDTH=2 %i
+select -assert-count 2 t:$mux
+select -assert-count 2 t:$mux r:WIDTH=2 %i
+select -assert-count 0 t:$logic_not t:$dff t:$mux %% t:* %D
-- 
cgit v1.2.3


From 7d644f40ed42f3f0c5e5218c5f0274a7bcdfca85 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 11 Sep 2019 17:05:47 -0700
Subject: Add AREG=2 BREG=2 test

---
 tests/xilinx/macc.v | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/xilinx/macc.v b/tests/xilinx/macc.v
index 5dc99ab8e..9d684477f 100644
--- a/tests/xilinx/macc.v
+++ b/tests/xilinx/macc.v
@@ -47,7 +47,7 @@ module macc2 # (parameter SIZEIN = 16, SIZEOUT = 40) (
 	output signed [SIZEOUT-1:0] accum_out
 );
 // Declare registers for intermediate values
-reg signed [SIZEIN-1:0] a_reg, b_reg;
+reg signed [SIZEIN-1:0] a_reg, b_reg, a_reg2, b_reg2;
 reg rst_reg;
 reg signed [2*SIZEIN-1:0] mult_reg;
 reg signed [SIZEOUT-1:0] adder_out, old_result;
@@ -56,14 +56,18 @@ always @(posedge clk) begin
 	begin
 		a_reg <= a;
 		b_reg <= b;
-		mult_reg <= a_reg * b_reg;
+		a_reg2 <= a_reg;
+		b_reg2 <= b_reg;
+		mult_reg <= a_reg2 * b_reg2;
 		rst_reg <= rst;
 		// Store accumulation result into a register
 		adder_out <= adder_out + mult_reg;
 	end
 	if (rst) begin
 		a_reg <= 0;
+		a_reg2 <= 0;
 		b_reg <= 0;
+		b_reg2 <= 0;
 		mult_reg <= 0;
 		adder_out <= 0;
 	end
-- 
cgit v1.2.3


From 14d72c39c385bba3005085815a0d66989a437eff Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 13 Sep 2019 16:33:18 -0700
Subject: Revert "Make one check $shift(x)? only; change testcase to be 8b"

This reverts commit e2c2d784c8217e4bcf29fb6b156b6a8285036b80.
---
 tests/various/peepopt.ys | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys
index 886c8cd9d..abee9cc0a 100644
--- a/tests/various/peepopt.ys
+++ b/tests/various/peepopt.ys
@@ -16,7 +16,7 @@ select -assert-count 0 t:$shiftx t:* %D
 design -reset
 read_verilog <<EOT
 module peepopt_shiftmul_1 (output [7:0] y, input [2:0] w);
-assign y = 1'b1 >> (w * (8'b110));
+assign y = 1'b1 >> (w * (3'b110));
 endmodule
 EOT
 
@@ -25,7 +25,7 @@ equiv_opt -assert peepopt
 design -load postopt
 clean
 select -assert-count 1 t:$shr
-select -assert-count 0 t:$mul
+select -assert-count 1 t:$mul
 select -assert-count 0 t:$shr t:$mul %% t:* %D
 
 ####################
-- 
cgit v1.2.3


From a2eee9ebefc6e8089c815b4355bc64d1ac3396b5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 13 Sep 2019 16:41:10 -0700
Subject: Add counter-example from @cliffordwolf

---
 tests/various/peepopt.ys | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

(limited to 'tests')

diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys
index abee9cc0a..7c1c3b5bc 100644
--- a/tests/various/peepopt.ys
+++ b/tests/various/peepopt.ys
@@ -30,6 +30,30 @@ select -assert-count 0 t:$shr t:$mul %% t:* %D
 
 ####################
 
+design -reset
+read_verilog <<EOT
+module peepopt_shiftmul_2 (input [11:0] D, input [1:0] S, output [11:0] Y);
+	assign Y = D >> (S*3);
+endmodule
+EOT
+
+prep
+design -save gold
+peepopt
+design -stash gate
+
+design -import gold -as gold peepopt_shiftmul_2
+design -import gate -as gate peepopt_shiftmul_2
+
+miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter
+sat -show-public -enable_undef -prove-asserts miter
+select -assert-count 1 t:$shr
+select -assert-count 1 t:$mul
+select -assert-count 0 t:$shr t:$mul %% t:* %D
+exit
+
+####################
+
 design -reset
 read_verilog <<EOT
 module peepopt_muldiv_0(input [1:0] i, output [1:0] o);
-- 
cgit v1.2.3


From f492567c872c1f6bc864fe0a3d86021558f8101e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 13 Sep 2019 18:19:07 -0700
Subject: Oops

---
 tests/various/peepopt.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys
index 7c1c3b5bc..6bca62e2b 100644
--- a/tests/various/peepopt.ys
+++ b/tests/various/peepopt.ys
@@ -47,10 +47,10 @@ design -import gate -as gate peepopt_shiftmul_2
 
 miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter
 sat -show-public -enable_undef -prove-asserts miter
+cd gate
 select -assert-count 1 t:$shr
 select -assert-count 1 t:$mul
 select -assert-count 0 t:$shr t:$mul %% t:* %D
-exit
 
 ####################
 
-- 
cgit v1.2.3


From c3cba7ab93bb21f5fa713fd037c77b890544a95c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 18 Sep 2019 12:07:25 -0700
Subject: Refine macc testcase

---
 tests/xilinx/macc.v  | 21 +++++++++++++--------
 tests/xilinx/macc.ys |  5 ++++-
 2 files changed, 17 insertions(+), 9 deletions(-)

(limited to 'tests')

diff --git a/tests/xilinx/macc.v b/tests/xilinx/macc.v
index 9d684477f..e36b2bab1 100644
--- a/tests/xilinx/macc.v
+++ b/tests/xilinx/macc.v
@@ -42,26 +42,29 @@ endmodule
 
 // Adapted variant of above
 module macc2 # (parameter SIZEIN = 16, SIZEOUT = 40) (
-	input clk, ce, rst,
+	input clk,
+	input ce,
+	input rst,
 	input signed [SIZEIN-1:0] a, b,
-	output signed [SIZEOUT-1:0] accum_out
+	output signed [SIZEOUT-1:0] accum_out,
+	output overflow
 );
 // Declare registers for intermediate values
 reg signed [SIZEIN-1:0] a_reg, b_reg, a_reg2, b_reg2;
-reg rst_reg;
-reg signed [2*SIZEIN-1:0] mult_reg;
-reg signed [SIZEOUT-1:0] adder_out, old_result;
+reg signed [2*SIZEIN-1:0] mult_reg = 0;
+reg signed [SIZEOUT:0] adder_out = 0;
+reg overflow_reg;
 always @(posedge clk) begin
-	if (ce)
+	//if (ce)
 	begin
 		a_reg <= a;
 		b_reg <= b;
 		a_reg2 <= a_reg;
 		b_reg2 <= b_reg;
 		mult_reg <= a_reg2 * b_reg2;
-		rst_reg <= rst;
 		// Store accumulation result into a register
 		adder_out <= adder_out + mult_reg;
+		overflow_reg <= overflow;
 	end
 	if (rst) begin
 		a_reg <= 0;
@@ -70,10 +73,12 @@ always @(posedge clk) begin
 		b_reg2 <= 0;
 		mult_reg <= 0;
 		adder_out <= 0;
+		overflow_reg <= 1'b0;
 	end
 end
+assign overflow = (adder_out >= 2**(SIZEOUT-1)) | overflow_reg;
 
 // Output accumulation result
-assign accum_out = adder_out;
+assign accum_out = overflow ? 2**(SIZEOUT-1)-1 : adder_out;
 
 endmodule
diff --git a/tests/xilinx/macc.ys b/tests/xilinx/macc.ys
index 294b83c69..417a3b21b 100644
--- a/tests/xilinx/macc.ys
+++ b/tests/xilinx/macc.ys
@@ -25,4 +25,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd macc2 # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
 select -assert-count 1 t:DSP48E1
-select -assert-none t:BUFG t:DSP48E1 %% t:* %D
+select -assert-count 1 t:FDRE
+select -assert-count 1 t:LUT2
+select -assert-count 41 t:LUT3
+select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:LUT3 %% t:* %D
-- 
cgit v1.2.3


From c9fe4d7992078ca0dec2cb7bcc6c58813e73189d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 18 Sep 2019 12:11:33 -0700
Subject: Add .gitignore

---
 tests/xilinx/.gitignore | 1 +
 1 file changed, 1 insertion(+)

(limited to 'tests')

diff --git a/tests/xilinx/.gitignore b/tests/xilinx/.gitignore
index b48f808a1..54733fb71 100644
--- a/tests/xilinx/.gitignore
+++ b/tests/xilinx/.gitignore
@@ -1,3 +1,4 @@
 /*.log
 /*.out
 /run-test.mk
+/*_uut.v
-- 
cgit v1.2.3


From c663a3680b13422c568e3dc438e7b971b81a71c3 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 18 Sep 2019 12:44:34 -0700
Subject: Remove stat

---
 tests/xilinx/mul_unsigned.ys | 1 -
 1 file changed, 1 deletion(-)

(limited to 'tests')

diff --git a/tests/xilinx/mul_unsigned.ys b/tests/xilinx/mul_unsigned.ys
index 30c034afe..77990bd68 100644
--- a/tests/xilinx/mul_unsigned.ys
+++ b/tests/xilinx/mul_unsigned.ys
@@ -4,7 +4,6 @@ hierarchy -top mul_unsigned
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mul_unsigned # Constrain all select calls below inside the top module
-stat
 select -assert-count 1 t:BUFG
 select -assert-count 1 t:DSP48E1
 select -assert-count 30 t:FDRE
-- 
cgit v1.2.3


From c9f9518de4af34b2539d230c0894b04d174b755d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= <koriakin@0x04.net>
Date: Wed, 28 Aug 2019 14:58:14 +0000
Subject: Added extractinv pass

---
 tests/techmap/extractinv.ys | 41 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)
 create mode 100644 tests/techmap/extractinv.ys

(limited to 'tests')

diff --git a/tests/techmap/extractinv.ys b/tests/techmap/extractinv.ys
new file mode 100644
index 000000000..6146f829a
--- /dev/null
+++ b/tests/techmap/extractinv.ys
@@ -0,0 +1,41 @@
+read_verilog << EOT
+
+module ff4(...);
+parameter [0:0] CLK_INV = 1'b0;
+parameter [3:0] DATA_INV = 4'b0000;
+(* invertible_pin = "CLK_INV" *)
+input clk;
+(* invertible_pin = "DATA_INV" *)
+input [3:0] d;
+output [3:0] q;
+endmodule
+
+module inv(...);
+output o;
+input i;
+endmodule
+
+module top(...);
+input d0, d1, d2, d3;
+input clk;
+output q;
+ff4 #(.DATA_INV(4'h5)) ff_inst (.clk(clk), .d({d3, d2, d1, d0}), .q(q));
+endmodule
+
+EOT
+
+extractinv -inv inv o:i
+clean
+
+select -assert-count 2 top/t:inv
+select -assert-count 2 top/t:inv top/t:ff4 %ci:+[d] %ci:+[o] %i
+
+select -assert-count 1 top/t:inv top/w:d0 %co:+[i] %i
+select -assert-count 0 top/t:inv top/w:d1 %co:+[i] %i
+select -assert-count 1 top/t:inv top/w:d2 %co:+[i] %i
+select -assert-count 0 top/t:inv top/w:d3 %co:+[i] %i
+
+select -assert-count 0 top/t:ff4 top/w:d0 %co:+[d] %i
+select -assert-count 1 top/t:ff4 top/w:d1 %co:+[d] %i
+select -assert-count 0 top/t:ff4 top/w:d2 %co:+[d] %i
+select -assert-count 1 top/t:ff4 top/w:d3 %co:+[d] %i
-- 
cgit v1.2.3


From 65fa8adf6c834cc3c73300a19d4fe96c31b8d361 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Sep 2019 11:02:14 -0700
Subject: Format macc.v

---
 tests/ice40/macc.v | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

(limited to 'tests')

diff --git a/tests/ice40/macc.v b/tests/ice40/macc.v
index 6c3676c83..757c36a66 100644
--- a/tests/ice40/macc.v
+++ b/tests/ice40/macc.v
@@ -13,13 +13,13 @@ reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c;
 assign c = reg_tmp_c;
 always @(posedge clk)
 begin
-if(set)
-begin
-reg_tmp_c <= 0;
-end
-else
-begin
-reg_tmp_c <= a * b + c;
-end
+    if(set)
+    begin
+        reg_tmp_c <= 0;
+    end
+    else
+    begin
+        reg_tmp_c <= a * b + c;
+    end
 end
 endmodule
-- 
cgit v1.2.3


From 2f98f9deee063de1e6a57437f1fe885d42916e19 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Sep 2019 18:08:16 -0700
Subject: Add mac.sh and macc_tb.v for testing

---
 tests/xilinx/macc.sh   |  3 ++
 tests/xilinx/macc_tb.v | 96 ++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 99 insertions(+)
 create mode 100644 tests/xilinx/macc.sh
 create mode 100644 tests/xilinx/macc_tb.v

(limited to 'tests')

diff --git a/tests/xilinx/macc.sh b/tests/xilinx/macc.sh
new file mode 100644
index 000000000..86e4c2bb6
--- /dev/null
+++ b/tests/xilinx/macc.sh
@@ -0,0 +1,3 @@
+../../yosys -qp "synth_xilinx -top macc2; rename -top macc2_uut" macc.v -o macc_uut.v
+iverilog -o test_macc macc_tb.v macc_uut.v macc.v ../../techlibs/xilinx/cells_sim.v
+vvp -N ./test_macc
diff --git a/tests/xilinx/macc_tb.v b/tests/xilinx/macc_tb.v
new file mode 100644
index 000000000..64aed05c4
--- /dev/null
+++ b/tests/xilinx/macc_tb.v
@@ -0,0 +1,96 @@
+`timescale 1ns / 1ps
+
+module testbench;
+
+    parameter SIZEIN = 16, SIZEOUT = 40;
+	reg clk, ce, rst;
+   	reg signed [SIZEIN-1:0] a, b;
+	output signed [SIZEOUT-1:0] REF_accum_out, accum_out;
+	output REF_overflow, overflow;
+
+	integer errcount = 0;
+
+	reg ERROR_FLAG = 0;
+
+	task clkcycle;
+		begin
+			#5;
+			clk = ~clk;
+			#10;
+			clk = ~clk;
+			#2;
+			ERROR_FLAG = 0;
+			if (REF_accum_out !== accum_out) begin
+				$display("ERROR at %1t: REF_accum_out=%b UUT_accum_out=%b DIFF=%b", $time, REF_accum_out, accum_out, REF_accum_out ^ accum_out);
+				errcount = errcount + 1;
+				ERROR_FLAG = 1;
+			end
+			if (REF_overflow !== overflow) begin
+				$display("ERROR at %1t: REF_overflow=%b UUT_overflow=%b DIFF=%b", $time, REF_overflow, overflow, REF_overflow ^ overflow);
+				errcount = errcount + 1;
+				ERROR_FLAG = 1;
+			end
+			#3;
+		end
+	endtask
+
+	initial begin
+		//$dumpfile("test_macc.vcd");
+		//$dumpvars(0, testbench);
+
+		#2;
+		clk = 1'b0;
+        ce = 1'b0;
+        a = 0;
+        b = 0;
+
+        rst = 1'b1;
+		repeat (10) begin
+			#10;
+			clk = 1'b1;
+			#10;
+			clk = 1'b0;
+			#10;
+			clk = 1'b1;
+			#10;
+			clk = 1'b0;
+		end
+		rst = 1'b0;
+
+		repeat (10000) begin
+			clkcycle;
+            ce = 1; //$urandom & $urandom;
+			//rst = $urandom & $urandom & $urandom & $urandom & $urandom & $urandom;
+			a = $urandom & ~(1 << (SIZEIN-1));
+			b = $urandom & ~(1 << (SIZEIN-1));
+		end
+
+		if (errcount == 0) begin
+			$display("All tests passed.");
+			$finish;
+		end else begin
+			$display("Caught %1d errors.", errcount);
+			$stop;
+		end
+	end
+
+	macc2 ref (
+        .clk(clk),
+        .ce(ce),
+        .rst(rst),
+        .a(a),
+        .b(b),
+        .accum_out(REF_accum_out),
+        .overflow(REF_overflow)
+	);
+
+	macc2_uut uut (
+        .clk(clk),
+        .ce(ce),
+        .rst(rst),
+        .a(a),
+        .b(b),
+        .accum_out(accum_out),
+        .overflow(overflow)
+	);
+endmodule
-- 
cgit v1.2.3


From 4100825b810408e25b1773cb1e57d25821f164b5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Sep 2019 22:39:15 -0700
Subject: Add more complicated macc testcase

---
 tests/ice40/macc.v  | 22 ++++++++++++++++++++++
 tests/ice40/macc.ys | 22 +++++++++++++++++-----
 2 files changed, 39 insertions(+), 5 deletions(-)

(limited to 'tests')

diff --git a/tests/ice40/macc.v b/tests/ice40/macc.v
index 757c36a66..6f68e7500 100644
--- a/tests/ice40/macc.v
+++ b/tests/ice40/macc.v
@@ -23,3 +23,25 @@ begin
     end
 end
 endmodule
+
+module top2(clk,a,b,c,hold);
+parameter A_WIDTH = 6 /*4*/;
+parameter B_WIDTH = 6 /*3*/;
+input hold;
+input clk;
+input signed [(A_WIDTH - 1):0] a;
+input signed [(B_WIDTH - 1):0] b;
+output signed [(A_WIDTH + B_WIDTH - 1):0] c;
+reg signed [A_WIDTH-1:0] reg_a;
+reg signed [B_WIDTH-1:0] reg_b;
+reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c;
+assign c = reg_tmp_c;
+always @(posedge clk)
+begin
+    if (!hold) begin
+        reg_a <= a;
+        reg_b <= b;
+        reg_tmp_c <= reg_a * reg_b + c;
+    end
+end
+endmodule
diff --git a/tests/ice40/macc.ys b/tests/ice40/macc.ys
index 0f4c19be5..fd30e79c5 100644
--- a/tests/ice40/macc.ys
+++ b/tests/ice40/macc.ys
@@ -1,13 +1,25 @@
 read_verilog macc.v
 proc
+design -save read
+
 hierarchy -top top
-#equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
+equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_MAC16
+select -assert-none t:SB_MAC16 %% t:* %D
+
+design -load read
+hierarchy -top top2
 
-equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 -dsp
-async2sync
-equiv_opt -run prove: -assert null
+#equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
+
+equiv_opt -run :prove -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
+clk2fflogic
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -set-init-zero -seq 4 -verify -prove-asserts -show-ports miter
 
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd top2 # Constrain all select calls below inside the top module
 select -assert-count 1 t:SB_MAC16
 select -assert-none t:SB_MAC16 %% t:* %D
-- 
cgit v1.2.3


From 6258e6a7e28ade2bdc7b6809675461326c873a45 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 20 Sep 2019 17:49:26 -0700
Subject: Add testcase

---
 tests/techmap/autopurge.ys | 43 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)
 create mode 100644 tests/techmap/autopurge.ys

(limited to 'tests')

diff --git a/tests/techmap/autopurge.ys b/tests/techmap/autopurge.ys
new file mode 100644
index 000000000..4773d5ce3
--- /dev/null
+++ b/tests/techmap/autopurge.ys
@@ -0,0 +1,43 @@
+# https://github.com/YosysHQ/yosys/issues/1391
+read_verilog <<EOT
+module sub(input i, output o, (* techmap_autopurge *) input [1:0] j);
+foobar f(i, o, j);
+endmodule
+EOT
+design -stash techmap
+
+read_verilog <<EOT
+(* blackbox *)
+module sub(input i, output o, input j);
+endmodule
+
+(* blackbox *)
+module foobar(input i, output o, input j);
+endmodule
+
+module top(input i, output o);
+sub s0(i, o);
+endmodule
+EOT
+
+techmap -map %techmap
+hierarchy
+check -assert
+
+read_verilog -overwrite <<EOT
+(* blackbox *)
+module sub(input i, output o, input j);
+endmodule
+
+(* blackbox *)
+module foobar(input i, output o, input j);
+endmodule
+
+module top(input i, output o);
+wire j;
+sub s0(i, o, j);
+endmodule
+EOT
+
+techmap -map %techmap
+hierarchy
-- 
cgit v1.2.3


From 7c8de1dd180e4d6cf708700d73f29f3b581722ce Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 20 Sep 2019 17:58:51 -0700
Subject: Hell let's add the original #1381 testcase too

---
 tests/techmap/autopurge.ys | 25 ++++++++++++++++++++++---
 1 file changed, 22 insertions(+), 3 deletions(-)

(limited to 'tests')

diff --git a/tests/techmap/autopurge.ys b/tests/techmap/autopurge.ys
index 4773d5ce3..1eb99ec37 100644
--- a/tests/techmap/autopurge.ys
+++ b/tests/techmap/autopurge.ys
@@ -1,6 +1,6 @@
-# https://github.com/YosysHQ/yosys/issues/1391
+# https://github.com/YosysHQ/yosys/issues/1381
 read_verilog <<EOT
-module sub(input i, output o, (* techmap_autopurge *) input [1:0] j);
+module sub(input i, output o, (* techmap_autopurge *) input j);
 foobar f(i, o, j);
 endmodule
 EOT
@@ -24,7 +24,16 @@ techmap -map %techmap
 hierarchy
 check -assert
 
-read_verilog -overwrite <<EOT
+# https://github.com/YosysHQ/yosys/issues/1391
+design -reset
+read_verilog <<EOT
+module sub(input i, output o, (* techmap_autopurge *) input [1:0] j);
+foobar f(i, o, j);
+endmodule
+EOT
+design -stash techmap
+
+read_verilog <<EOT
 (* blackbox *)
 module sub(input i, output o, input j);
 endmodule
@@ -33,6 +42,16 @@ endmodule
 module foobar(input i, output o, input j);
 endmodule
 
+module top(input i, output o);
+sub s0(i, o);
+endmodule
+EOT
+
+techmap -map %techmap
+hierarchy
+check -assert
+
+read_verilog -overwrite <<EOT
 module top(input i, output o);
 wire j;
 sub s0(i, o, j);
-- 
cgit v1.2.3


From fc6ebf8268780c47b503e68be4b2ec368388e2c5 Mon Sep 17 00:00:00 2001
From: SergeyDegtyar <sndegtyar@gmail.com>
Date: Tue, 24 Sep 2019 14:55:32 +0300
Subject: adffs test update (equiv_opt -multiclock).

---
 tests/ice40/adffs.v  | 18 +++++++-----------
 tests/ice40/adffs.ys | 13 ++++++-------
 2 files changed, 13 insertions(+), 18 deletions(-)

(limited to 'tests')

diff --git a/tests/ice40/adffs.v b/tests/ice40/adffs.v
index 93c8bf52c..05e68caf7 100644
--- a/tests/ice40/adffs.v
+++ b/tests/ice40/adffs.v
@@ -22,30 +22,26 @@ module adffn
             q <= d;
 endmodule
 
-module dffsr
+module dffs
     ( input d, clk, pre, clr, output reg q );
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge pre, posedge clr )
-		if ( clr )
-			q <= 1'b0;
-		else if ( pre )
+	always @( posedge clk )
+		if ( pre )
 			q <= 1'b1;
 		else
             q <= d;
 endmodule
 
-module ndffnsnr
+module ndffnr
     ( input d, clk, pre, clr, output reg q );
     initial begin
       q = 0;
     end
-	always @( negedge clk, negedge pre, negedge clr )
+	always @( negedge clk )
 		if ( !clr )
 			q <= 1'b0;
-		else if ( !pre )
-			q <= 1'b1;
 		else
             q <= d;
 endmodule
@@ -58,7 +54,7 @@ input a,
 output b,b1,b2,b3
 );
 
-dffsr u_dffsr (
+dffs u_dffs (
         .clk (clk ),
         .clr (clr),
         .pre (pre),
@@ -66,7 +62,7 @@ dffsr u_dffsr (
         .q (b )
     );
 
-ndffnsnr u_ndffnsnr (
+ndffnr u_ndffnr (
         .clk (clk ),
         .clr (clr),
         .pre (pre),
diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys
index 14b251c5c..f82da6b14 100644
--- a/tests/ice40/adffs.ys
+++ b/tests/ice40/adffs.ys
@@ -1,12 +1,11 @@
 read_verilog adffs.v
 proc
-async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock
 flatten
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
+equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
-select -assert-count 1 t:SB_DFF
-select -assert-count 1 t:SB_DFFN
-select -assert-count 2 t:SB_DFFSR
-select -assert-count 7 t:SB_LUT4
-select -assert-none t:SB_DFF t:SB_DFFN t:SB_DFFSR t:SB_LUT4 %% t:* %D
+select -assert-count 1 t:SB_DFFNSR
+select -assert-count 2 t:SB_DFFR
+select -assert-count 1 t:SB_DFFSS
+select -assert-count 1 t:SB_LUT4
+select -assert-none t:SB_DFFNSR t:SB_DFFR t:SB_DFFSS t:SB_LUT4 %% t:* %D
-- 
cgit v1.2.3


From b66364ada279c1fb81583003001b332dd4521f93 Mon Sep 17 00:00:00 2001
From: SergeyDegtyar <sndegtyar@gmail.com>
Date: Wed, 25 Sep 2019 14:43:26 +0300
Subject: Change sync controls to async.

---
 tests/ice40/adffs.v  | 8 ++++----
 tests/ice40/adffs.ys | 8 ++++----
 2 files changed, 8 insertions(+), 8 deletions(-)

(limited to 'tests')

diff --git a/tests/ice40/adffs.v b/tests/ice40/adffs.v
index 05e68caf7..09dc36001 100644
--- a/tests/ice40/adffs.v
+++ b/tests/ice40/adffs.v
@@ -27,7 +27,7 @@ module dffs
     initial begin
       q = 0;
     end
-	always @( posedge clk )
+	always @( posedge clk, posedge pre )
 		if ( pre )
 			q <= 1'b1;
 		else
@@ -39,9 +39,9 @@ module ndffnr
     initial begin
       q = 0;
     end
-	always @( negedge clk )
-		if ( !clr )
-			q <= 1'b0;
+	always @( negedge clk, negedge pre )
+		if ( !pre )
+			q <= 1'b1;
 		else
             q <= d;
 endmodule
diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys
index f82da6b14..548060b66 100644
--- a/tests/ice40/adffs.ys
+++ b/tests/ice40/adffs.ys
@@ -4,8 +4,8 @@ flatten
 equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
-select -assert-count 1 t:SB_DFFNSR
+select -assert-count 1 t:SB_DFFNS
 select -assert-count 2 t:SB_DFFR
-select -assert-count 1 t:SB_DFFSS
-select -assert-count 1 t:SB_LUT4
-select -assert-none t:SB_DFFNSR t:SB_DFFR t:SB_DFFSS t:SB_LUT4 %% t:* %D
+select -assert-count 1 t:SB_DFFS
+select -assert-count 2 t:SB_LUT4
+select -assert-none t:SB_DFFNS t:SB_DFFR t:SB_DFFS t:SB_LUT4 %% t:* %D
-- 
cgit v1.2.3


From 7f0eec8270dbef06e3e6970af20dae2d6f89f6b9 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 27 Sep 2019 11:31:55 +0200
Subject: Change order of parameters, to work on other os

---
 tests/ice40/run-test.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/ice40/run-test.sh b/tests/ice40/run-test.sh
index 2c72ca3a9..46716f9a0 100755
--- a/tests/ice40/run-test.sh
+++ b/tests/ice40/run-test.sh
@@ -6,7 +6,7 @@ for x in *.ys; do
 	echo "all:: run-$x"
 	echo "run-$x:"
 	echo "	@echo 'Running $x..'"
-	echo "	@../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'"
+	echo "	@../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
 done
 for s in *.sh; do
 	if [ "$s" != "run-test.sh" ]; then
-- 
cgit v1.2.3


From fd0e3a2c43d96ba31beede9865d5000230029994 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= <marcin@symbioticeda.com>
Date: Fri, 27 Sep 2019 11:03:04 +0200
Subject: Fix _TECHMAP_REMOVEINIT_ handling.

Previously, this wire was handled in the code that populated the "do or
do not" techmap cache, resulting in init value removal being performed
only for the first use of a given template.

Fixes the problem identified in #1396.
---
 tests/techmap/wireinit.ys | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/techmap/wireinit.ys b/tests/techmap/wireinit.ys
index 1396839fe..89afaafb5 100644
--- a/tests/techmap/wireinit.ys
+++ b/tests/techmap/wireinit.ys
@@ -46,11 +46,13 @@ input clk;
 input d;
 output reg q0 = 0;
 output reg q1 = 1;
+output reg qq0 = 0;
 output reg qx;
 
 always @(posedge clk) begin
 	q0 <= d;
 	q1 <= d;
+	qq0 <= q0;
 	qx <= d;
 end
 endmodule
@@ -64,16 +66,20 @@ simplemap
 techmap -map %map
 clean
 # Make sure the parameter was used properly.
-select -assert-count 2 top/t:ffbb
+select -assert-count 3 top/t:ffbb
 select -set ff0 top/w:q0 %ci t:ffbb %i
+select -set ffq0 top/w:qq0 %ci t:ffbb %i
 select -set ffx top/w:qx %ci t:ffbb %i
 select -assert-count 1 @ff0
+select -assert-count 1 @ffq0
 select -assert-count 1 @ffx
 select -assert-count 1 @ff0 r:INIT=1'b0 %i
+select -assert-count 1 @ffq0 r:INIT=1'b0 %i
 select -assert-count 1 @ffx r:INIT=1'bx %i
 select -assert-count 0 top/w:q1 %ci t:ffbb %i
 # Make sure the init values are dropped from the wires iff mapping was performed.
 select -assert-count 0 top/w:q0 a:init %i
+select -assert-count 0 top/w:qq0 a:init %i
 select -assert-count 1 top/w:q1 a:init=1'b1 %i
 select -assert-count 0 top/w:qx a:init %i
 
@@ -84,15 +90,19 @@ simplemap
 techmap -map %map_noremove
 clean
 # Make sure the parameter was used properly.
-select -assert-count 2 top/t:ffbb
+select -assert-count 3 top/t:ffbb
 select -set ff0 top/w:q0 %ci t:ffbb %i
+select -set ffq0 top/w:qq0 %ci t:ffbb %i
 select -set ffx top/w:qx %ci t:ffbb %i
 select -assert-count 1 @ff0
+select -assert-count 1 @ffq0
 select -assert-count 1 @ffx
 select -assert-count 1 @ff0 r:INIT=1'b0 %i
+select -assert-count 1 @ffq0 r:INIT=1'b0 %i
 select -assert-count 1 @ffx r:INIT=1'bx %i
 select -assert-count 0 top/w:q1 %ci t:ffbb %i
 # Make sure the init values are not dropped from the wires.
 select -assert-count 1 top/w:q0 a:init=1'b0 %i
+select -assert-count 1 top/w:qq0 a:init=1'b0 %i
 select -assert-count 1 top/w:q1 a:init=1'b1 %i
 select -assert-count 0 top/w:qx a:init %i
-- 
cgit v1.2.3


From 6216e45edae11fa3cc6e45a65762e5c215af0904 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 27 Sep 2019 12:50:20 -0700
Subject: Add latch test modified from #1363

---
 tests/xilinx/latches.v  | 58 +++++++++++++++++++++++++++++++++++++++++++++++++
 tests/xilinx/latches.ys | 15 +++++++++++++
 2 files changed, 73 insertions(+)
 create mode 100644 tests/xilinx/latches.v
 create mode 100644 tests/xilinx/latches.ys

(limited to 'tests')

diff --git a/tests/xilinx/latches.v b/tests/xilinx/latches.v
new file mode 100644
index 000000000..83bad7f35
--- /dev/null
+++ b/tests/xilinx/latches.v
@@ -0,0 +1,58 @@
+module latchp
+    ( input d, en, output reg q );
+	always @*
+		if ( en )
+			q <= d;
+endmodule
+
+module latchn
+    ( input d, en, output reg q );
+	always @*
+		if ( !en )
+			q <= d;
+endmodule
+
+module latchsr
+    ( input d, en, clr, pre, output reg q );
+	always @*
+		if ( clr )
+			q <= 1'b0;
+		else if ( pre )
+			q <= 1'b1;
+		else if ( en )
+			q <= d;
+endmodule
+
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2
+);
+
+
+latchp u_latchp (
+        .en (clk ),
+        .d (a ),
+        .q (b )
+    );
+
+
+latchn u_latchn (
+        .en (clk ),
+        .d (a ),
+        .q (b1 )
+    );
+
+
+latchsr u_latchsr (
+        .en (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b2 )
+    );
+
+endmodule
diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys
new file mode 100644
index 000000000..ac1102896
--- /dev/null
+++ b/tests/xilinx/latches.ys
@@ -0,0 +1,15 @@
+read_verilog latches.v
+
+proc
+flatten
+equiv_opt -assert -run :prove -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+async2sync
+equiv_opt -assert -run prove: -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+
+design -load preopt
+synth_xilinx
+cd top
+select -assert-count 1 t:LUT1
+select -assert-count 2 t:LUT3
+select -assert-count 3 t:LDCE
+select -assert-none t:LUT1 t:LUT3 t:LDCE %% t:* %D
-- 
cgit v1.2.3


From 99a7f39084cf4b9cd21e2a1e4f4a842993dfd147 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Thu, 26 Sep 2019 03:57:16 +0000
Subject: rpc: new frontend.

A new pass, connect_rpc, allows any HDL frontend that can read/write
JSON from/to stdin/stdout or an unix socket or a named pipe to
participate in elaboration as a first class citizen, such that any
other HDL supported by Yosys directly or indirectly can transparently
instantiate modules handled by this frontend.

Recognizing that many HDL frontends emit Verilog, it allows the RPC
frontend to direct Yosys to process the result of instantiation via
any built-in Yosys frontend. The resulting RTLIL is then hygienically
integrated into the overall design.
---
 tests/rpc/.gitignore  |   1 +
 tests/rpc/design.v    |   8 ++++
 tests/rpc/exec.ys     |   5 ++
 tests/rpc/frontend.py | 126 ++++++++++++++++++++++++++++++++++++++++++++++++++
 tests/rpc/run-test.sh |   6 +++
 tests/rpc/unix.ys     |   6 +++
 6 files changed, 152 insertions(+)
 create mode 100644 tests/rpc/.gitignore
 create mode 100644 tests/rpc/design.v
 create mode 100644 tests/rpc/exec.ys
 create mode 100644 tests/rpc/frontend.py
 create mode 100755 tests/rpc/run-test.sh
 create mode 100644 tests/rpc/unix.ys

(limited to 'tests')

diff --git a/tests/rpc/.gitignore b/tests/rpc/.gitignore
new file mode 100644
index 000000000..397b4a762
--- /dev/null
+++ b/tests/rpc/.gitignore
@@ -0,0 +1 @@
+*.log
diff --git a/tests/rpc/design.v b/tests/rpc/design.v
new file mode 100644
index 000000000..80f1dac1a
--- /dev/null
+++ b/tests/rpc/design.v
@@ -0,0 +1,8 @@
+module top(input [3:0] i, output [3:0] o);
+	python_inv #(
+	  .width(4)
+	) inv (
+		.i(i),
+		.o(o),
+	);
+endmodule
diff --git a/tests/rpc/exec.ys b/tests/rpc/exec.ys
new file mode 100644
index 000000000..b46009fb9
--- /dev/null
+++ b/tests/rpc/exec.ys
@@ -0,0 +1,5 @@
+connect_rpc -exec python3 frontend.py stdio
+read_verilog design.v
+hierarchy -top top
+flatten
+select -assert-count 1 t:$neg
diff --git a/tests/rpc/frontend.py b/tests/rpc/frontend.py
new file mode 100644
index 000000000..eff41738a
--- /dev/null
+++ b/tests/rpc/frontend.py
@@ -0,0 +1,126 @@
+def modules():
+	return ["python_inv"]
+
+def derive(module, parameters):
+	assert module == r"python_inv"
+	if parameters.keys() != {r"\width"}:
+		raise ValueError("Invalid parameters")
+	return "ilang", r"""
+module \impl
+	wire width {width:d} input 1 \i
+	wire width {width:d} output 2 \o
+	cell $neg $0
+		parameter \A_SIGNED 1'0
+		parameter \A_WIDTH 32'{width:b}
+		parameter \Y_WIDTH 32'{width:b}
+		connect \A \i
+		connect \Y \o
+	end
+end
+module \python_inv
+	wire width {width:d} input 1 \i
+	wire width {width:d} output 2 \o
+	cell \impl $0
+		connect \i \i
+		connect \o \o
+	end
+end
+""".format(width=parameters[r"\width"])
+
+# ----------------------------------------------------------------------------
+
+import json
+import argparse
+import sys, socket, os
+try:
+	import msvcrt, win32pipe, win32file
+except ImportError:
+	msvcrt = win32pipe = win32file = None
+
+def map_parameter(parameter):
+	if parameter["type"] == "unsigned":
+		return int(parameter["value"], 2)
+	if parameter["type"] == "signed":
+		width = len(parameter["value"])
+		value = int(parameter["value"], 2)
+		if value & (1 << (width - 1)):
+			value = -((1 << width) - value)
+		return value
+	if parameter["type"] == "string":
+		return parameter["value"]
+	if parameter["type"] == "real":
+		return float(parameter["value"])
+
+def call(input_json):
+	input = json.loads(input_json)
+	if input["method"] == "modules":
+		return json.dumps({"modules": modules()})
+	if input["method"] == "derive":
+		try:
+			frontend, source = derive(input["module"],
+				{name: map_parameter(value) for name, value in input["parameters"].items()})
+			return json.dumps({"frontend": frontend, "source": source})
+		except ValueError as e:
+			return json.dumps({"error": str(e)})
+
+def main():
+	parser = argparse.ArgumentParser()
+	modes = parser.add_subparsers(dest="mode")
+	mode_stdio = modes.add_parser("stdio")
+	if os.name == "posix":
+		mode_path = modes.add_parser("unix-socket")
+	if os.name == "nt":
+		mode_path = modes.add_parser("named-pipe")
+	mode_path.add_argument("path")
+	args = parser.parse_args()
+
+	if args.mode == "stdio":
+		while True:
+			input = sys.stdin.readline()
+			if not input: break
+			sys.stdout.write(call(input) + "\n")
+			sys.stdout.flush()
+
+	if args.mode == "unix-socket":
+		sock = socket.socket(socket.AF_UNIX, socket.SOCK_STREAM)
+		sock.bind(args.path)
+		try:
+			sock.listen(1)
+			conn, addr = sock.accept()
+			file = conn.makefile("rw")
+			while True:
+				input = file.readline()
+				if not input: break
+				file.write(call(input) + "\n")
+				file.flush()
+		finally:
+			sock.close()
+			os.unlink(args.path)
+
+	if args.mode == "named-pipe":
+		pipe = win32pipe.CreateNamedPipe(args.path, win32pipe.PIPE_ACCESS_DUPLEX,
+		    win32pipe.PIPE_TYPE_BYTE|win32pipe.PIPE_READMODE_BYTE|win32pipe.PIPE_WAIT,
+		    1, 4096, 4096, 0, None)
+		win32pipe.ConnectNamedPipe(pipe, None)
+		try:
+			while True:
+				input = b""
+				while not input.endswith(b"\n"):
+					result, data = win32file.ReadFile(pipe, 4096)
+					assert result == 0
+					input += data
+					assert not b"\n" in input or input.endswith(b"\n")
+				output = (call(input.decode("utf-8")) + "\n").encode("utf-8")
+				length = len(output)
+				while length > 0:
+					result, done = win32file.WriteFile(pipe, output)
+					assert result == 0
+					length -= done
+		except win32file.error as e:
+			if e.args[0] == 109: # ERROR_BROKEN_PIPE
+				pass
+			else:
+				raise
+
+if __name__ == "__main__":
+	main()
diff --git a/tests/rpc/run-test.sh b/tests/rpc/run-test.sh
new file mode 100755
index 000000000..44ce7e674
--- /dev/null
+++ b/tests/rpc/run-test.sh
@@ -0,0 +1,6 @@
+#!/bin/bash
+set -e
+for x in *.ys; do
+  echo "Running $x.."
+  ../../yosys -ql ${x%.ys}.log $x
+done
diff --git a/tests/rpc/unix.ys b/tests/rpc/unix.ys
new file mode 100644
index 000000000..cc7ec14ab
--- /dev/null
+++ b/tests/rpc/unix.ys
@@ -0,0 +1,6 @@
+!python3 frontend.py unix-socket frontend.sock & sleep 0.1
+connect_rpc -path frontend.sock
+read_verilog design.v
+hierarchy -top top
+flatten
+select -assert-count 1 t:$neg
-- 
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