From 21699e5840b71433eb242d9c60f1635908717f5e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 19 Aug 2019 13:04:57 +0200 Subject: Add *.sv to tests/simple_abc9/.gitignore Signed-off-by: Clifford Wolf --- tests/simple_abc9/.gitignore | 1 + 1 file changed, 1 insertion(+) (limited to 'tests') diff --git a/tests/simple_abc9/.gitignore b/tests/simple_abc9/.gitignore index 598951333..2355aea29 100644 --- a/tests/simple_abc9/.gitignore +++ b/tests/simple_abc9/.gitignore @@ -1,3 +1,4 @@ *.v +*.sv *.log *.out -- cgit v1.2.3 From 4a942ba7b9bb76f207adf23369f46d31f7607b75 Mon Sep 17 00:00:00 2001 From: whitequark Date: Mon, 19 Aug 2019 16:44:23 +0000 Subject: proc_clean: fix order of switch insertion. Fixes #1268. --- tests/proc/.gitignore | 1 + tests/proc/bug_1268.v | 23 +++++++++++++++++++++++ tests/proc/bug_1268.ys | 5 +++++ tests/proc/run-test.sh | 6 ++++++ 4 files changed, 35 insertions(+) create mode 100644 tests/proc/.gitignore create mode 100644 tests/proc/bug_1268.v create mode 100644 tests/proc/bug_1268.ys create mode 100755 tests/proc/run-test.sh (limited to 'tests') diff --git a/tests/proc/.gitignore b/tests/proc/.gitignore new file mode 100644 index 000000000..397b4a762 --- /dev/null +++ b/tests/proc/.gitignore @@ -0,0 +1 @@ +*.log diff --git a/tests/proc/bug_1268.v b/tests/proc/bug_1268.v new file mode 100644 index 000000000..698ac937a --- /dev/null +++ b/tests/proc/bug_1268.v @@ -0,0 +1,23 @@ +module gold (input clock, ctrl, din, output reg dout); + always @(posedge clock) begin + if (1'b1) begin + if (1'b0) begin end else begin + dout <= 0; + end + if (ctrl) + dout <= din; + end + end +endmodule + +module gate (input clock, ctrl, din, output reg dout); + always @(posedge clock) begin + if (1'b1) begin + if (1'b0) begin end else begin + dout <= 0; + end + end + if (ctrl) + dout <= din; + end +endmodule diff --git a/tests/proc/bug_1268.ys b/tests/proc/bug_1268.ys new file mode 100644 index 000000000..b73e94449 --- /dev/null +++ b/tests/proc/bug_1268.ys @@ -0,0 +1,5 @@ +read_verilog bug_1268.v +proc +equiv_make gold gate equiv +equiv_induct +equiv_status -assert diff --git a/tests/proc/run-test.sh b/tests/proc/run-test.sh new file mode 100755 index 000000000..44ce7e674 --- /dev/null +++ b/tests/proc/run-test.sh @@ -0,0 +1,6 @@ +#!/bin/bash +set -e +for x in *.ys; do + echo "Running $x.." + ../../yosys -ql ${x%.ys}.log $x +done -- cgit v1.2.3 From 6ffb910d12a93e64182b52a58e69386851f2d595 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 20 Aug 2019 11:38:21 +0200 Subject: Add test case for real parameters Signed-off-by: Clifford Wolf --- tests/simple/realexpr.v | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/simple/realexpr.v b/tests/simple/realexpr.v index 5b756e6be..74ed8faa5 100644 --- a/tests/simple/realexpr.v +++ b/tests/simple/realexpr.v @@ -1,4 +1,3 @@ - module demo_001(y1, y2, y3, y4); output [7:0] y1, y2, y3, y4; @@ -22,3 +21,13 @@ module demo_002(y0, y1, y2, y3); assign y3 = 1 ? -1 : 'd0; endmodule +module demo_003(output A, B); + parameter real p = 0; + assign A = (p==1.0); + assign B = (p!="1.000000"); +endmodule + +module demo_004(output A, B, C, D); + demo_003 #(1.0) demo_real (A, B); + demo_003 #(1) demo_int (C, D); +endmodule -- cgit v1.2.3