From ef1a1402bcecd5cf3edc41b9842ab5500e52a95e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 19 Feb 2019 15:25:03 -0800 Subject: Add a quick abc9 test --- tests/techmap/abc9/abc9.v | 6 ++++++ tests/techmap/abc9/abc9_runtest.sh | 5 +++++ tests/techmap/abc9/run-test.sh | 10 ++++++++++ tests/techmap/run-test.sh | 8 ++++++++ 4 files changed, 29 insertions(+) create mode 100644 tests/techmap/abc9/abc9.v create mode 100644 tests/techmap/abc9/abc9_runtest.sh create mode 100755 tests/techmap/abc9/run-test.sh (limited to 'tests') diff --git a/tests/techmap/abc9/abc9.v b/tests/techmap/abc9/abc9.v new file mode 100644 index 000000000..2d9aea366 --- /dev/null +++ b/tests/techmap/abc9/abc9.v @@ -0,0 +1,6 @@ +module top(input [1:0] a, output [1:0] b, output c, output d, output e); +assign b = a; +assign c = ^a; +assign d = ~c; +assign e = d; +endmodule diff --git a/tests/techmap/abc9/abc9_runtest.sh b/tests/techmap/abc9/abc9_runtest.sh new file mode 100644 index 000000000..2deaad719 --- /dev/null +++ b/tests/techmap/abc9/abc9_runtest.sh @@ -0,0 +1,5 @@ +#!/bin/bash + +set -ev + +../../../yosys -p 'abc9 -lut 4; check; select -assert-count 2 t:$lut; select -assert-none c:* t:$lut %n %i' abc9.v diff --git a/tests/techmap/abc9/run-test.sh b/tests/techmap/abc9/run-test.sh new file mode 100755 index 000000000..e2fc11e52 --- /dev/null +++ b/tests/techmap/abc9/run-test.sh @@ -0,0 +1,10 @@ +#!/bin/bash +set -e +for x in *_runtest.sh; do + echo "Running $x.." + if ! bash $x &> ${x%.sh}.log; then + tail ${x%.sh}.log + echo ERROR + exit 1 + fi +done diff --git a/tests/techmap/run-test.sh b/tests/techmap/run-test.sh index e2fc11e52..129451e08 100755 --- a/tests/techmap/run-test.sh +++ b/tests/techmap/run-test.sh @@ -8,3 +8,11 @@ for x in *_runtest.sh; do exit 1 fi done + +for d in */; do + if [ -x $d/run-test.sh ]; then + cd $d + bash run-test.sh + cd .. + fi +done -- cgit v1.2.3 From 945bbcc2989c6b6cad2ef3b9aae253f23d6a2697 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 20 Feb 2019 15:31:35 -0800 Subject: Add tests/simple_abc9 --- tests/simple_abc9/run-test.sh | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100755 tests/simple_abc9/run-test.sh (limited to 'tests') diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh new file mode 100755 index 000000000..5c51e44f9 --- /dev/null +++ b/tests/simple_abc9/run-test.sh @@ -0,0 +1,23 @@ +#!/bin/bash + +OPTIND=1 +seed="" # default to no seed specified +while getopts "S:" opt +do + case "$opt" in + S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space + seed="SEED=$arg" ;; + esac +done +shift "$((OPTIND-1))" + +# check for Icarus Verilog +if ! which iverilog > /dev/null ; then + echo "$0: Error: Icarus Verilog 'iverilog' not found." + exit 1 +fi + +cp ../simple/*.v . +rm dff_different_styles.v # FIXME: dffsr1 fails because opt_rmdff does something fishy (#816) +rm partsel.v # FIXME: Contains 1'hx, thus write_xaiger fails +exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p \"synth -abc9 -lut 4\"" -- cgit v1.2.3 From 43d5471570bd208ec87e2994f53a835c1e8ef3b9 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 20 Feb 2019 15:34:59 -0800 Subject: Move tests/techmap/abc9 to simple_abc9 --- tests/simple_abc9/abc9.v | 6 ++++++ tests/techmap/abc9/abc9.v | 6 ------ tests/techmap/abc9/abc9_runtest.sh | 5 ----- tests/techmap/abc9/run-test.sh | 10 ---------- tests/techmap/run-test.sh | 8 -------- 5 files changed, 6 insertions(+), 29 deletions(-) create mode 100644 tests/simple_abc9/abc9.v delete mode 100644 tests/techmap/abc9/abc9.v delete mode 100644 tests/techmap/abc9/abc9_runtest.sh delete mode 100755 tests/techmap/abc9/run-test.sh (limited to 'tests') diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v new file mode 100644 index 000000000..2d9aea366 --- /dev/null +++ b/tests/simple_abc9/abc9.v @@ -0,0 +1,6 @@ +module top(input [1:0] a, output [1:0] b, output c, output d, output e); +assign b = a; +assign c = ^a; +assign d = ~c; +assign e = d; +endmodule diff --git a/tests/techmap/abc9/abc9.v b/tests/techmap/abc9/abc9.v deleted file mode 100644 index 2d9aea366..000000000 --- a/tests/techmap/abc9/abc9.v +++ /dev/null @@ -1,6 +0,0 @@ -module top(input [1:0] a, output [1:0] b, output c, output d, output e); -assign b = a; -assign c = ^a; -assign d = ~c; -assign e = d; -endmodule diff --git a/tests/techmap/abc9/abc9_runtest.sh b/tests/techmap/abc9/abc9_runtest.sh deleted file mode 100644 index 2deaad719..000000000 --- a/tests/techmap/abc9/abc9_runtest.sh +++ /dev/null @@ -1,5 +0,0 @@ -#!/bin/bash - -set -ev - -../../../yosys -p 'abc9 -lut 4; check; select -assert-count 2 t:$lut; select -assert-none c:* t:$lut %n %i' abc9.v diff --git a/tests/techmap/abc9/run-test.sh b/tests/techmap/abc9/run-test.sh deleted file mode 100755 index e2fc11e52..000000000 --- a/tests/techmap/abc9/run-test.sh +++ /dev/null @@ -1,10 +0,0 @@ -#!/bin/bash -set -e -for x in *_runtest.sh; do - echo "Running $x.." - if ! bash $x &> ${x%.sh}.log; then - tail ${x%.sh}.log - echo ERROR - exit 1 - fi -done diff --git a/tests/techmap/run-test.sh b/tests/techmap/run-test.sh index 129451e08..e2fc11e52 100755 --- a/tests/techmap/run-test.sh +++ b/tests/techmap/run-test.sh @@ -8,11 +8,3 @@ for x in *_runtest.sh; do exit 1 fi done - -for d in */; do - if [ -x $d/run-test.sh ]; then - cd $d - bash run-test.sh - cd .. - fi -done -- cgit v1.2.3 From 869343b040d60ffa9bfdda81660c2ecd88848e79 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 20 Feb 2019 16:19:01 -0800 Subject: simple_abc9 tests to now preserve memories --- tests/simple_abc9/run-test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh index 5c51e44f9..1baf31244 100755 --- a/tests/simple_abc9/run-test.sh +++ b/tests/simple_abc9/run-test.sh @@ -20,4 +20,4 @@ fi cp ../simple/*.v . rm dff_different_styles.v # FIXME: dffsr1 fails because opt_rmdff does something fishy (#816) rm partsel.v # FIXME: Contains 1'hx, thus write_xaiger fails -exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p \"synth -abc9 -lut 4\"" +exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p \"hierarchy; synth -run coarse; techmap; opt -full; abc9 -lut 4\"" -- cgit v1.2.3 From c6fd057eda5dba371ff9c1142019b801bee81111 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 21 Feb 2019 10:37:45 -0800 Subject: Add abc9.v testcase to simple_abc9 --- tests/simple_abc9/abc9.v | 50 ++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 46 insertions(+), 4 deletions(-) (limited to 'tests') diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 2d9aea366..d387b99eb 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -1,6 +1,48 @@ -module top(input [1:0] a, output [1:0] b, output c, output d, output e); +module abc9_test001(input a, output o); +assign o = a; +endmodule + +module abc9_test002(input [1:0] a, output o); +assign o = a[1]; +endmodule + +module abc9_test003(input [1:0] a, output [1:0] o); +assign o = a; +endmodule + +module abc9_test004(input [1:0] a, output o); +assign o = ^a; +endmodule + +module abc9_test005(input [1:0] a, output o, output p); +assign o = ^a; +assign p = ~o; +endmodule + +module abc9_test006(input [1:0] a, output [2:0] o); +assign o[0] = ^a; +assign o[1] = ~o[0]; +assign o[2] = o[1]; +endmodule + +module abc9_test007(input a, output o); +wire b, c; +assign c = ~a; +assign b = c; +abc9_test007_sub s(b, o); +endmodule + +module abc9_test007_sub(input a, output b); assign b = a; -assign c = ^a; -assign d = ~c; -assign e = d; +endmodule + +module abc9_test008(input a, output o); +wire b, c; +assign b = ~a; +assign c = b; +abc9_test008_sub s(b, o); +endmodule + +module abc9_test008_sub(input a, output b); +assign b = ~a; endmodule -- cgit v1.2.3 From 107da3becff01cdedf6572ece3af9a74463a3e93 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 21 Feb 2019 11:16:25 -0800 Subject: Working simple_abc9 tests --- tests/simple_abc9/run-test.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh index 1baf31244..bf48d007d 100755 --- a/tests/simple_abc9/run-test.sh +++ b/tests/simple_abc9/run-test.sh @@ -18,6 +18,6 @@ if ! which iverilog > /dev/null ; then fi cp ../simple/*.v . -rm dff_different_styles.v # FIXME: dffsr1 fails because opt_rmdff does something fishy (#816) rm partsel.v # FIXME: Contains 1'hx, thus write_xaiger fails -exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p \"hierarchy; synth -run coarse; techmap; opt -full; abc9 -lut 4\"" +DOLLAR='?' +exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'hierarchy; synth -run coarse; techmap; opt -full; abc9 -lut 4; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_'" -- cgit v1.2.3 From 5994382a20a0b7e890d22d032eecb39b61e0b3ce Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 21 Feb 2019 11:16:57 -0800 Subject: tests/simple to also do LUT synth --- tests/tools/autotest.sh | 1 + 1 file changed, 1 insertion(+) (limited to 'tests') diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index 65fd4cb1f..34007b689 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -180,6 +180,7 @@ do else test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.v test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.v + test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -lut 4" ${bn}_ref.v if [ -n "$firrtl2verilog" ]; then if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then "$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt; memory; opt; fsm; opt -full -fine; pmuxtree" ${bn}_ref.v -- cgit v1.2.3 From ca870688c33f7a71eea78709d85a069957966ba6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 21 Feb 2019 13:15:45 -0800 Subject: Revert "tests/simple to also do LUT synth" This reverts commit 5994382a20a0b7e890d22d032eecb39b61e0b3ce. --- tests/tools/autotest.sh | 1 - 1 file changed, 1 deletion(-) (limited to 'tests') diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index 2b8e60200..13c25432f 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -178,7 +178,6 @@ do else test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.v test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.v - test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -lut 4" ${bn}_ref.v if [ -n "$firrtl2verilog" ]; then if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then "$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt; memory; opt; fsm; opt -full -fine; pmuxtree" ${bn}_ref.v -- cgit v1.2.3 From 65c8ccf7b57a69f1e1629a3b3df7505073b0474c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 25 Feb 2019 15:06:23 -0800 Subject: Add broken testcases --- tests/simple_abc9/abc9.v | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'tests') diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index d387b99eb..ad0e86d24 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -46,3 +46,49 @@ endmodule module abc9_test008_sub(input a, output b); assign b = ~a; endmodule + +// TODO +//module abc9_test009(inout io, input oe); +//reg latch; +//always @(io or oe) +// if (!oe) +// latch <= io; +//assign io = oe ? ~latch : 1'bz; +//endmodule + +// TODO +//module abc9_test010(inout [7:0] io, input oe); +//reg [7:0] latch; +//always @(io or oe) +// if (!oe) +// latch <= io; +//assign io = oe ? ~latch : 1'bz; +//endmodule + +// TODO +//module abc9_test011(inout [7:0] io, input oe); +//reg [7:0] latch; +//always @(io or oe) +// if (!oe) +// latch[3:0] <= io; +// else +// latch[7:4] <= io; +//assign io[3:0] = oe ? ~latch[3:0] : 4'bz; +//assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz; +//endmodule + +// TODO +//module abc9_test012(inout [7:0] io, input oe); +//abc9_test012_sub sub(io, oe); +//endmodule +// +//module abc9_test012_sub(inout [7:0] io, input oe); +//reg [7:0] latch; +//always @(io or oe) +// if (!oe) +// latch[3:0] <= io; +// else +// latch[7:4] <= io; +//assign io[3:0] = oe ? ~latch[3:0] : 4'bz; +//assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz; +//endmodule -- cgit v1.2.3 From 66b5f5166b358ae7efebd278ad32cd05f3eb72be Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 26 Feb 2019 11:39:17 -0800 Subject: Enable two inout tests --- tests/simple_abc9/abc9.v | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) (limited to 'tests') diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index ad0e86d24..8a809e480 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -47,23 +47,21 @@ module abc9_test008_sub(input a, output b); assign b = ~a; endmodule -// TODO -//module abc9_test009(inout io, input oe); -//reg latch; -//always @(io or oe) -// if (!oe) -// latch <= io; -//assign io = oe ? ~latch : 1'bz; -//endmodule +module abc9_test009(inout io, input oe); +reg latch; +always @(io or oe) + if (!oe) + latch <= io; +assign io = oe ? ~latch : 1'bz; +endmodule -// TODO -//module abc9_test010(inout [7:0] io, input oe); -//reg [7:0] latch; -//always @(io or oe) -// if (!oe) -// latch <= io; -//assign io = oe ? ~latch : 1'bz; -//endmodule +module abc9_test010(inout [7:0] io, input oe); +reg [7:0] latch; +always @(io or oe) + if (!oe) + latch <= io; +assign io = oe ? ~latch : 8'bz; +endmodule // TODO //module abc9_test011(inout [7:0] io, input oe); -- cgit v1.2.3 From dfb23a79dd0e2ffbe4f058eadb552d8194540eef Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 26 Feb 2019 12:18:48 -0800 Subject: Uncomment out more tests --- tests/simple_abc9/abc9.v | 64 +++++++++++++++++++++++++++++------------------- 1 file changed, 39 insertions(+), 25 deletions(-) (limited to 'tests') diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 8a809e480..eca340693 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -63,30 +63,44 @@ always @(io or oe) assign io = oe ? ~latch : 8'bz; endmodule -// TODO -//module abc9_test011(inout [7:0] io, input oe); -//reg [7:0] latch; -//always @(io or oe) -// if (!oe) -// latch[3:0] <= io; -// else -// latch[7:4] <= io; -//assign io[3:0] = oe ? ~latch[3:0] : 4'bz; -//assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz; -//endmodule - -// TODO -//module abc9_test012(inout [7:0] io, input oe); -//abc9_test012_sub sub(io, oe); -//endmodule -// -//module abc9_test012_sub(inout [7:0] io, input oe); -//reg [7:0] latch; +module abc9_test011(inout io, input oe); +reg latch; +always @(io or oe) + if (!oe) + latch <= io; +//assign io = oe ? ~latch : 8'bz; +endmodule + +module abc9_test012(inout io, input oe); +reg latch; //always @(io or oe) // if (!oe) -// latch[3:0] <= io; -// else -// latch[7:4] <= io; -//assign io[3:0] = oe ? ~latch[3:0] : 4'bz; -//assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz; -//endmodule +// latch <= io; +assign io = oe ? ~latch : 8'bz; +endmodule + +module abc9_test013(inout [3:0] io, input oe); +reg [3:0] latch; +always @(io or oe) + if (!oe) + latch[3:0] <= io[3:0]; + else + latch[7:4] <= io; +assign io[3:0] = oe ? ~latch[3:0] : 4'bz; +assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz; +endmodule + +module abc9_test014(inout [7:0] io, input oe); +abc9_test012_sub sub(io, oe); +endmodule + +module abc9_test012_sub(inout [7:0] io, input oe); +reg [7:0] latch; +always @(io or oe) + if (!oe) + latch[3:0] <= io; + else + latch[7:4] <= io; +assign io[3:0] = oe ? ~latch[3:0] : 4'bz; +assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz; +endmodule -- cgit v1.2.3 From 0c8a839f13bf7bc8368625ab55960dd3f219b0d8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 16 Apr 2019 13:10:35 -0700 Subject: Re-enable partsel.v test --- tests/simple_abc9/run-test.sh | 1 - 1 file changed, 1 deletion(-) (limited to 'tests') diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh index bf48d007d..af003d52e 100755 --- a/tests/simple_abc9/run-test.sh +++ b/tests/simple_abc9/run-test.sh @@ -18,6 +18,5 @@ if ! which iverilog > /dev/null ; then fi cp ../simple/*.v . -rm partsel.v # FIXME: Contains 1'hx, thus write_xaiger fails DOLLAR='?' exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'hierarchy; synth -run coarse; techmap; opt -full; abc9 -lut 4; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_'" -- cgit v1.2.3 From 59c993e4372df1624b538bd12aee96381c874f6f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 19 Apr 2019 15:47:53 -0700 Subject: Select to find union of both sets on stack --- tests/simple_abc9/run-test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh index af003d52e..97f284378 100755 --- a/tests/simple_abc9/run-test.sh +++ b/tests/simple_abc9/run-test.sh @@ -19,4 +19,4 @@ fi cp ../simple/*.v . DOLLAR='?' -exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'hierarchy; synth -run coarse; techmap; opt -full; abc9 -lut 4; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_'" +exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'hierarchy; synth -run coarse; techmap; opt -full; abc9 -lut 4; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'" -- cgit v1.2.3 From bfd71e09906096c72039beebb1b3b6a79dd6b36c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 23 Apr 2019 16:11:14 -0700 Subject: Fix abc9 with (* keep *) wires --- tests/simple_abc9/abc9.v | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'tests') diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index eca340693..f37d975ff 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -104,3 +104,41 @@ always @(io or oe) assign io[3:0] = oe ? ~latch[3:0] : 4'bz; assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz; endmodule + +module abc9_test015(input a, output b, input c); +assign b = ~a; +(* keep *) wire d; +assign d = ~c; +endmodule + +module abc9_test016(input a, output b); +assign b = ~a; +(* keep *) reg c; +always @* c <= ~a; +endmodule + +module abc9_test017(input a, output b); +assign b = ~a; +(* keep *) reg c; +always @* c = b; +endmodule + +module abc9_test018(input a, output b, output c); +assign b = ~a; +(* keep *) wire [1:0] d; +assign c = &d; +endmodule + +module abc9_test019(input a, output b); +assign b = ~a; +(* keep *) reg [1:0] c; +reg d; +always @* d <= &c; +endmodule + +module abc9_test020(input a, output b); +assign b = ~a; +(* keep *) reg [1:0] c; +(* keep *) reg d; +always @* d <= &c; +endmodule -- cgit v1.2.3 From eec314e2621d3d055d7810f4b7e573a99e0239b2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 24 Apr 2019 21:06:53 -0700 Subject: Remove topo sort no-loop assertion, with test --- tests/simple_abc9/abc.box | 2 ++ tests/simple_abc9/abc9.v | 73 +++++++++++++++++++++++++++++++++++++++++++ tests/simple_abc9/run-test.sh | 2 +- 3 files changed, 76 insertions(+), 1 deletion(-) create mode 100644 tests/simple_abc9/abc.box (limited to 'tests') diff --git a/tests/simple_abc9/abc.box b/tests/simple_abc9/abc.box new file mode 100644 index 000000000..a8801d807 --- /dev/null +++ b/tests/simple_abc9/abc.box @@ -0,0 +1,2 @@ +MUXF8 1 0 3 1 +1 1 1 diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index f37d975ff..fb5b759fb 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -142,3 +142,76 @@ assign b = ~a; (* keep *) reg d; always @* d <= &c; endmodule + +module abc9_test021(clk, rst, s_eth_hdr_valid, s_eth_hdr_ready, s_eth_dest_mac, s_eth_src_mac, s_eth_type, s_eth_payload_axis_tdata, s_eth_payload_axis_tkeep, s_eth_payload_axis_tvalid, s_eth_payload_axis_tready, s_eth_payload_axis_tlast, s_eth_payload_axis_tid, s_eth_payload_axis_tdest, s_eth_payload_axis_tuser, m_eth_hdr_valid, m_eth_hdr_ready, m_eth_dest_mac, m_eth_src_mac, m_eth_type, m_eth_payload_axis_tdata, m_eth_payload_axis_tkeep, m_eth_payload_axis_tvalid, m_eth_payload_axis_tready, m_eth_payload_axis_tlast, m_eth_payload_axis_tid, m_eth_payload_axis_tdest, m_eth_payload_axis_tuser); + input clk; + output [47:0] m_eth_dest_mac; + input m_eth_hdr_ready; + output m_eth_hdr_valid; + output [7:0] m_eth_payload_axis_tdata; + output [7:0] m_eth_payload_axis_tdest; + output [7:0] m_eth_payload_axis_tid; + output m_eth_payload_axis_tkeep; + output m_eth_payload_axis_tlast; + input m_eth_payload_axis_tready; + output m_eth_payload_axis_tuser; + output m_eth_payload_axis_tvalid; + output [47:0] m_eth_src_mac; + output [15:0] m_eth_type; + input rst; + input [191:0] s_eth_dest_mac; + output [3:0] s_eth_hdr_ready; + input [3:0] s_eth_hdr_valid; + input [31:0] s_eth_payload_axis_tdata; + input [31:0] s_eth_payload_axis_tdest; + input [31:0] s_eth_payload_axis_tid; + input [3:0] s_eth_payload_axis_tkeep; + input [3:0] s_eth_payload_axis_tlast; + output [3:0] s_eth_payload_axis_tready; + input [3:0] s_eth_payload_axis_tuser; + input [3:0] s_eth_payload_axis_tvalid; + input [191:0] s_eth_src_mac; + input [63:0] s_eth_type; + (* keep *) + wire [0:0] grant, request; + wire a; + not u0 ( + a, + grant[0] + ); + and u1 ( + request[0], + s_eth_hdr_valid[0], + a + ); + (* keep *) + MUXF8 u2 ( + .I0(1'bx), + .I1(1'bx), + .O(o), + .S(1'bx) + ); + arbiter arb_inst ( + .acknowledge(acknowledge), + .clk(clk), + .grant(grant), + .grant_encoded(grant_encoded), + .grant_valid(grant_valid), + .request(request), + .rst(rst) + ); +endmodule + +module arbiter (clk, rst, request, acknowledge, grant, grant_valid, grant_encoded); + input [3:0] acknowledge; + input clk; + output [3:0] grant; + output [1:0] grant_encoded; + output grant_valid; + input [3:0] request; + input rst; +endmodule + +(* abc_box_id=1 *) +module MUXF8(input I0, I1, S, output O); +endmodule diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh index 97f284378..4935d41ad 100755 --- a/tests/simple_abc9/run-test.sh +++ b/tests/simple_abc9/run-test.sh @@ -19,4 +19,4 @@ fi cp ../simple/*.v . DOLLAR='?' -exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'hierarchy; synth -run coarse; techmap; opt -full; abc9 -lut 4; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'" +exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4 -box ../abc.box; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'" -- cgit v1.2.3 From 0eb7150a5706e81ff36a6a57d8c0c6a2fda05e07 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 25 Apr 2019 18:08:05 -0700 Subject: Add test --- tests/various/split_shiftx.v | 118 ++++++++++++++++++++++++++++++++++++++++++ tests/various/split_shiftx.ys | 21 ++++++++ 2 files changed, 139 insertions(+) create mode 100644 tests/various/split_shiftx.v create mode 100644 tests/various/split_shiftx.ys (limited to 'tests') diff --git a/tests/various/split_shiftx.v b/tests/various/split_shiftx.v new file mode 100644 index 000000000..dfcea3880 --- /dev/null +++ b/tests/various/split_shiftx.v @@ -0,0 +1,118 @@ +module split_shiftx_test01(i, s, o); + wire [3:0] _0_; + input [8:0] i; + output [2:0] o; + input [1:0] s; + \$macc #( + .A_WIDTH(32'd4), + .B_WIDTH(32'd0), + .CONFIG(10'h282), + .CONFIG_WIDTH(32'd10), + .Y_WIDTH(32'd4) + ) _1_ ( + .A({ 2'h3, s }), + .B(), + .Y(_0_) + ); + \$shiftx #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd9), + .B_SIGNED(32'd1), + .B_WIDTH(32'd5), + .Y_WIDTH(32'd3) + ) _2_ ( + .A(i), + .B({ 1'h0, _0_ }), + .Y(o) + ); +endmodule + +// Sign bit is 1 +module split_shiftx_test02(i, s, o); + wire [3:0] _0_; + input [8:0] i; + output [2:0] o; + input [1:0] s; + \$macc #( + .A_WIDTH(32'd4), + .B_WIDTH(32'd0), + .CONFIG(10'h282), + .CONFIG_WIDTH(32'd10), + .Y_WIDTH(32'd4) + ) _1_ ( + .A({ 2'h3, s }), + .B(), + .Y(_0_) + ); + \$shiftx #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd9), + .B_SIGNED(32'd1), + .B_WIDTH(32'd5), + .Y_WIDTH(32'd3) + ) _2_ ( + .A(i), + .B({ 1'h1, _0_ }), + .Y(o) + ); +endmodule + +// Non constant $macc +module split_shiftx_test03(i, s, o); + wire [3:0] _0_; + input [8:0] i; + output [2:0] o; + input [1:0] s; + \$macc #( + .A_WIDTH(32'd4), + .B_WIDTH(32'd0), + .CONFIG(10'h282), + .CONFIG_WIDTH(32'd10), + .Y_WIDTH(32'd4) + ) _1_ ( + .A({ s, s }), + .B(), + .Y(_0_) + ); + \$shiftx #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd9), + .B_SIGNED(32'd1), + .B_WIDTH(32'd5), + .Y_WIDTH(32'd3) + ) _2_ ( + .A(i), + .B({ 1'h0, _0_ }), + .Y(o) + ); +endmodule + +// Wrong constant $macc +module split_shiftx_test04(i, s, o); + wire [3:0] _0_; + input [8:0] i; + output [2:0] o; + input [1:0] s; + \$macc #( + .A_WIDTH(32'd4), + .B_WIDTH(32'd0), + .CONFIG(10'h282), + .CONFIG_WIDTH(32'd10), + .Y_WIDTH(32'd4) + ) _1_ ( + .A({ 2'h2, s }), + .B(), + .Y(_0_) + ); + \$shiftx #( + .A_SIGNED(32'd0), + .A_WIDTH(32'd9), + .B_SIGNED(32'd1), + .B_WIDTH(32'd5), + .Y_WIDTH(32'd3) + ) _2_ ( + .A(i), + .B({ 1'h0, _0_ }), + .Y(o) + ); +endmodule diff --git a/tests/various/split_shiftx.ys b/tests/various/split_shiftx.ys new file mode 100644 index 000000000..810348aa3 --- /dev/null +++ b/tests/various/split_shiftx.ys @@ -0,0 +1,21 @@ +read_verilog -icells split_shiftx.v +split_shiftx + +cd split_shiftx_test01 +select -assert-count 3 t:$shiftx +select -assert-count 0 t: t:$shiftx %n %i + +cd split_shiftx_test02 +select -assert-count 1 t:$shiftx +select -assert-count 1 t:$macc +select -assert-count 0 t: t:$shiftx t:$macc %u %n %i + +cd split_shiftx_test03 +select -assert-count 1 t:$shiftx +select -assert-count 1 t:$macc +select -assert-count 0 t: t:$shiftx t:$macc %u %n %i + +cd split_shiftx_test04 +select -assert-count 1 t:$shiftx +select -assert-count 1 t:$macc +select -assert-count 0 t: t:$shiftx t:$macc %u %n %i -- cgit v1.2.3 From 0f1ba949243aa7ccc7c6b42738a60a09be7a209e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 26 Apr 2019 19:45:47 -0700 Subject: Remove split_shiftx tests --- tests/various/split_shiftx.v | 118 ------------------------------------------ tests/various/split_shiftx.ys | 21 -------- 2 files changed, 139 deletions(-) delete mode 100644 tests/various/split_shiftx.v delete mode 100644 tests/various/split_shiftx.ys (limited to 'tests') diff --git a/tests/various/split_shiftx.v b/tests/various/split_shiftx.v deleted file mode 100644 index dfcea3880..000000000 --- a/tests/various/split_shiftx.v +++ /dev/null @@ -1,118 +0,0 @@ -module split_shiftx_test01(i, s, o); - wire [3:0] _0_; - input [8:0] i; - output [2:0] o; - input [1:0] s; - \$macc #( - .A_WIDTH(32'd4), - .B_WIDTH(32'd0), - .CONFIG(10'h282), - .CONFIG_WIDTH(32'd10), - .Y_WIDTH(32'd4) - ) _1_ ( - .A({ 2'h3, s }), - .B(), - .Y(_0_) - ); - \$shiftx #( - .A_SIGNED(32'd0), - .A_WIDTH(32'd9), - .B_SIGNED(32'd1), - .B_WIDTH(32'd5), - .Y_WIDTH(32'd3) - ) _2_ ( - .A(i), - .B({ 1'h0, _0_ }), - .Y(o) - ); -endmodule - -// Sign bit is 1 -module split_shiftx_test02(i, s, o); - wire [3:0] _0_; - input [8:0] i; - output [2:0] o; - input [1:0] s; - \$macc #( - .A_WIDTH(32'd4), - .B_WIDTH(32'd0), - .CONFIG(10'h282), - .CONFIG_WIDTH(32'd10), - .Y_WIDTH(32'd4) - ) _1_ ( - .A({ 2'h3, s }), - .B(), - .Y(_0_) - ); - \$shiftx #( - .A_SIGNED(32'd0), - .A_WIDTH(32'd9), - .B_SIGNED(32'd1), - .B_WIDTH(32'd5), - .Y_WIDTH(32'd3) - ) _2_ ( - .A(i), - .B({ 1'h1, _0_ }), - .Y(o) - ); -endmodule - -// Non constant $macc -module split_shiftx_test03(i, s, o); - wire [3:0] _0_; - input [8:0] i; - output [2:0] o; - input [1:0] s; - \$macc #( - .A_WIDTH(32'd4), - .B_WIDTH(32'd0), - .CONFIG(10'h282), - .CONFIG_WIDTH(32'd10), - .Y_WIDTH(32'd4) - ) _1_ ( - .A({ s, s }), - .B(), - .Y(_0_) - ); - \$shiftx #( - .A_SIGNED(32'd0), - .A_WIDTH(32'd9), - .B_SIGNED(32'd1), - .B_WIDTH(32'd5), - .Y_WIDTH(32'd3) - ) _2_ ( - .A(i), - .B({ 1'h0, _0_ }), - .Y(o) - ); -endmodule - -// Wrong constant $macc -module split_shiftx_test04(i, s, o); - wire [3:0] _0_; - input [8:0] i; - output [2:0] o; - input [1:0] s; - \$macc #( - .A_WIDTH(32'd4), - .B_WIDTH(32'd0), - .CONFIG(10'h282), - .CONFIG_WIDTH(32'd10), - .Y_WIDTH(32'd4) - ) _1_ ( - .A({ 2'h2, s }), - .B(), - .Y(_0_) - ); - \$shiftx #( - .A_SIGNED(32'd0), - .A_WIDTH(32'd9), - .B_SIGNED(32'd1), - .B_WIDTH(32'd5), - .Y_WIDTH(32'd3) - ) _2_ ( - .A(i), - .B({ 1'h0, _0_ }), - .Y(o) - ); -endmodule diff --git a/tests/various/split_shiftx.ys b/tests/various/split_shiftx.ys deleted file mode 100644 index 810348aa3..000000000 --- a/tests/various/split_shiftx.ys +++ /dev/null @@ -1,21 +0,0 @@ -read_verilog -icells split_shiftx.v -split_shiftx - -cd split_shiftx_test01 -select -assert-count 3 t:$shiftx -select -assert-count 0 t: t:$shiftx %n %i - -cd split_shiftx_test02 -select -assert-count 1 t:$shiftx -select -assert-count 1 t:$macc -select -assert-count 0 t: t:$shiftx t:$macc %u %n %i - -cd split_shiftx_test03 -select -assert-count 1 t:$shiftx -select -assert-count 1 t:$macc -select -assert-count 0 t: t:$shiftx t:$macc %u %n %i - -cd split_shiftx_test04 -select -assert-count 1 t:$shiftx -select -assert-count 1 t:$macc -select -assert-count 0 t: t:$shiftx t:$macc %u %n %i -- cgit v1.2.3 From ac10e7d96da4965751fd60a8dd42a8998c011c39 Mon Sep 17 00:00:00 2001 From: Udi Finkelstein Date: Fri, 3 May 2019 03:10:43 +0300 Subject: Initial implementation of elaboration system tasks (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen. --- tests/various/elab_sys_tasks.sv | 30 ++++++++++++++++++++++++++++++ tests/various/elab_sys_tasks.ys | 1 + 2 files changed, 31 insertions(+) create mode 100644 tests/various/elab_sys_tasks.sv create mode 100644 tests/various/elab_sys_tasks.ys (limited to 'tests') diff --git a/tests/various/elab_sys_tasks.sv b/tests/various/elab_sys_tasks.sv new file mode 100644 index 000000000..774d85b32 --- /dev/null +++ b/tests/various/elab_sys_tasks.sv @@ -0,0 +1,30 @@ +module test; +localparam X=1; +genvar i; +generate +if (X == 1) + $info("X is 1"); +if (X == 1) + $warning("X is 1"); +else + $error("X is not 1"); +case (X) + 1: $info("X is 1 in a case statement"); +endcase +//case (X-1) +// 1: $warn("X is 2"); +// default: $warn("X might be anything in a case statement"); +//endcase +for (i = 0; i < 3; i = i + 1) +begin + case(i) + 0: $info; + 1: $warning; + default: $info("default case statemnent"); + endcase +end + +$info("This is a standalone $info(). Next $info has no parameters"); +$info; +endgenerate +endmodule diff --git a/tests/various/elab_sys_tasks.ys b/tests/various/elab_sys_tasks.ys new file mode 100644 index 000000000..45bee3a60 --- /dev/null +++ b/tests/various/elab_sys_tasks.ys @@ -0,0 +1 @@ +read_verilog -sv elab_sys_tasks.sv -- cgit v1.2.3 From 9a468f81c412f8b63d25e739f28932815c6882fb Mon Sep 17 00:00:00 2001 From: Bogdan Vukobratovic Date: Tue, 28 May 2019 08:48:21 +0200 Subject: Optimizing DFFs whose initial value prevents their value from changing This is a proof of concept implementation that invokes SAT solver via Pass::call method. --- tests/opt/opt_ff_sat.v | 15 +++++++++++++++ tests/opt/opt_ff_sat.ys | 4 ++++ 2 files changed, 19 insertions(+) create mode 100644 tests/opt/opt_ff_sat.v create mode 100644 tests/opt/opt_ff_sat.ys (limited to 'tests') diff --git a/tests/opt/opt_ff_sat.v b/tests/opt/opt_ff_sat.v new file mode 100644 index 000000000..fc1e61980 --- /dev/null +++ b/tests/opt/opt_ff_sat.v @@ -0,0 +1,15 @@ +module top( + input clk, + input a, + output b + ); + reg b_reg; + initial begin + b_reg <= 0; + end + + assign b = b_reg; + always @(posedge clk) begin + b_reg <= a && b_reg; + end +endmodule diff --git a/tests/opt/opt_ff_sat.ys b/tests/opt/opt_ff_sat.ys new file mode 100644 index 000000000..13e4ad29b --- /dev/null +++ b/tests/opt/opt_ff_sat.ys @@ -0,0 +1,4 @@ +read_verilog opt_ff_sat.v +prep -flatten +opt_rmdff -sat +synth -- cgit v1.2.3 From 5f39c262c278f90f6bbb55d5969b970230876ef5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 28 May 2019 09:38:58 -0700 Subject: From master --- tests/tools/autotest.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index 1825990a9..920474a84 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -132,13 +132,13 @@ do fn=$(basename $fn) bn=$(basename $bn) + rm -f ${bn}_ref.fir if [[ "$ext" == "v" ]]; then egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext} else "$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn} frontend="verilog -noblackbox" fi - rm -f ${bn}_ref.fir if [ ! -f ../${bn}_tb.v ]; then "$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.v -- cgit v1.2.3 From 92197326b8fa406e94c952cfcb778611642a3e00 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 28 May 2019 12:43:07 -0700 Subject: Add abc9_test022 --- tests/simple_abc9/abc9.v | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'tests') diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index fb5b759fb..e666d1a6a 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -143,6 +143,7 @@ assign b = ~a; always @* d <= &c; endmodule +// Citation: https://github.com/alexforencich/verilog-ethernet module abc9_test021(clk, rst, s_eth_hdr_valid, s_eth_hdr_ready, s_eth_dest_mac, s_eth_src_mac, s_eth_type, s_eth_payload_axis_tdata, s_eth_payload_axis_tkeep, s_eth_payload_axis_tvalid, s_eth_payload_axis_tready, s_eth_payload_axis_tlast, s_eth_payload_axis_tid, s_eth_payload_axis_tdest, s_eth_payload_axis_tuser, m_eth_hdr_valid, m_eth_hdr_ready, m_eth_dest_mac, m_eth_src_mac, m_eth_type, m_eth_payload_axis_tdata, m_eth_payload_axis_tkeep, m_eth_payload_axis_tvalid, m_eth_payload_axis_tready, m_eth_payload_axis_tlast, m_eth_payload_axis_tid, m_eth_payload_axis_tdest, m_eth_payload_axis_tuser); input clk; output [47:0] m_eth_dest_mac; @@ -215,3 +216,24 @@ endmodule (* abc_box_id=1 *) module MUXF8(input I0, I1, S, output O); endmodule + +// Citation: https://github.com/alexforencich/verilog-ethernet +// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test022" abc9.v -q +// returns before b4321a31 +// Warning: Wire abc9_test022.\m_eth_payload_axis_tkeep [7] is used but has no +// driver. +// Warning: Wire abc9_test022.\m_eth_payload_axis_tkeep [3] is used but has no +// driver. +module abc9_test022 +( + input wire clk, + input wire i, + output wire [7:0] m_eth_payload_axis_tkeep +); + +reg [7:0] m_eth_payload_axis_tkeep_reg = 8'd0; +assign m_eth_payload_axis_tkeep = m_eth_payload_axis_tkeep_reg; +always @(posedge clk) + m_eth_payload_axis_tkeep_reg <= i ? 8'hff : 8'h0f; + +endmodule -- cgit v1.2.3 From aa2380c17a7c97d4c3835cd6d78310cf4961c4f8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 29 May 2019 15:24:38 -0700 Subject: Add abc_test024 --- tests/simple_abc9/abc9.v | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) (limited to 'tests') diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index e666d1a6a..7af2ace01 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -230,10 +230,23 @@ module abc9_test022 input wire i, output wire [7:0] m_eth_payload_axis_tkeep ); - -reg [7:0] m_eth_payload_axis_tkeep_reg = 8'd0; -assign m_eth_payload_axis_tkeep = m_eth_payload_axis_tkeep_reg; -always @(posedge clk) - m_eth_payload_axis_tkeep_reg <= i ? 8'hff : 8'h0f; - + reg [7:0] m_eth_payload_axis_tkeep_reg = 8'd0; + assign m_eth_payload_axis_tkeep = m_eth_payload_axis_tkeep_reg; + always @(posedge clk) + m_eth_payload_axis_tkeep_reg <= i ? 8'hff : 8'h0f; +endmodule + +// Citation: https://github.com/riscv/riscv-bitmanip +// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test024" abc9.v -q +// returns before 14233843 +// Warning: Wire abc9_test024.\dout [1] is used but has no driver. +module abc9_test024 #( + parameter integer N = 2, + parameter integer M = 2 +) ( + input [7:0] din, + output [M-1:0] dout +); + wire [2*M-1:0] mask = {M{1'b1}}; + assign dout = (mask << din[N-1:0]) >> M; endmodule -- cgit v1.2.3 From 25befbf5425458cf8cc5ee89635ad7e5f42d5778 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 29 May 2019 15:26:33 -0700 Subject: Rename to #23 --- tests/simple_abc9/abc9.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'tests') diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 7af2ace01..2752ff8cc 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -237,10 +237,10 @@ module abc9_test022 endmodule // Citation: https://github.com/riscv/riscv-bitmanip -// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test024" abc9.v -q +// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test023" abc9.v -q // returns before 14233843 -// Warning: Wire abc9_test024.\dout [1] is used but has no driver. -module abc9_test024 #( +// Warning: Wire abc9_test023.\dout [1] is used but has no driver. +module abc9_test023 #( parameter integer N = 2, parameter integer M = 2 ) ( -- cgit v1.2.3 From 5739cf52650ccb3627868d9c9d7e02888efad12b Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Mon, 3 Jun 2019 09:12:51 +0200 Subject: Added tests for attributes Signed-off-by: Maciej Kurc --- tests/simple/attrib01_module.v | 21 ++++++++++++++++++++ tests/simple/attrib02_port_decl.v | 25 +++++++++++++++++++++++ tests/simple/attrib03_parameter.v | 28 ++++++++++++++++++++++++++ tests/simple/attrib04_net_var.v | 32 ++++++++++++++++++++++++++++++ tests/simple/attrib05_port_conn.v.DISABLED | 21 ++++++++++++++++++++ tests/simple/attrib06_operator_suffix.v | 23 +++++++++++++++++++++ tests/simple/attrib07_func_call.v.DISABLED | 21 ++++++++++++++++++++ tests/simple/attrib08_mod_inst.v | 22 ++++++++++++++++++++ tests/simple/attrib09_case.v | 26 ++++++++++++++++++++++++ 9 files changed, 219 insertions(+) create mode 100644 tests/simple/attrib01_module.v create mode 100644 tests/simple/attrib02_port_decl.v create mode 100644 tests/simple/attrib03_parameter.v create mode 100644 tests/simple/attrib04_net_var.v create mode 100644 tests/simple/attrib05_port_conn.v.DISABLED create mode 100644 tests/simple/attrib06_operator_suffix.v create mode 100644 tests/simple/attrib07_func_call.v.DISABLED create mode 100644 tests/simple/attrib08_mod_inst.v create mode 100644 tests/simple/attrib09_case.v (limited to 'tests') diff --git a/tests/simple/attrib01_module.v b/tests/simple/attrib01_module.v new file mode 100644 index 000000000..adef34f5b --- /dev/null +++ b/tests/simple/attrib01_module.v @@ -0,0 +1,21 @@ +module bar(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output reg out; + + always @(posedge clk) + if (rst) out <= 1'd0; + else out <= ~inp; + +endmodule + +module foo(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output wire out; + + bar bar_instance (clk, rst, inp, out); +endmodule + diff --git a/tests/simple/attrib02_port_decl.v b/tests/simple/attrib02_port_decl.v new file mode 100644 index 000000000..3505e7265 --- /dev/null +++ b/tests/simple/attrib02_port_decl.v @@ -0,0 +1,25 @@ +module bar(clk, rst, inp, out); + (* this_is_clock = 1 *) + input wire clk; + (* this_is_reset = 1 *) + input wire rst; + input wire inp; + (* an_output_register = 1*) + output reg out; + + always @(posedge clk) + if (rst) out <= 1'd0; + else out <= ~inp; + +endmodule + +module foo(clk, rst, inp, out); + (* this_is_the_master_clock *) + input wire clk; + input wire rst; + input wire inp; + output wire out; + + bar bar_instance (clk, rst, inp, out); +endmodule + diff --git a/tests/simple/attrib03_parameter.v b/tests/simple/attrib03_parameter.v new file mode 100644 index 000000000..562d225cd --- /dev/null +++ b/tests/simple/attrib03_parameter.v @@ -0,0 +1,28 @@ +module bar(clk, rst, inp, out); + + (* bus_width *) + parameter WIDTH = 2; + + (* an_attribute_on_localparam = 55 *) + localparam INCREMENT = 5; + + input wire clk; + input wire rst; + input wire [WIDTH-1:0] inp; + output reg [WIDTH-1:0] out; + + always @(posedge clk) + if (rst) out <= 0; + else out <= inp + INCREMENT; + +endmodule + +module foo(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire [7:0] inp; + output wire [7:0] out; + + bar # (.WIDTH(8)) bar_instance (clk, rst, inp, out); +endmodule + diff --git a/tests/simple/attrib04_net_var.v b/tests/simple/attrib04_net_var.v new file mode 100644 index 000000000..8b5523406 --- /dev/null +++ b/tests/simple/attrib04_net_var.v @@ -0,0 +1,32 @@ +module bar(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output reg out; + + (* this_is_a_prescaler *) + reg [7:0] counter; + + (* temp_wire *) + wire out_val; + + always @(posedge clk) + counter <= counter + 1; + + assign out_val = inp ^ counter[4]; + + always @(posedge clk) + if (rst) out <= 1'd0; + else out <= out_val; + +endmodule + +module foo(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output wire out; + + bar bar_instance (clk, rst, inp, out); +endmodule + diff --git a/tests/simple/attrib05_port_conn.v.DISABLED b/tests/simple/attrib05_port_conn.v.DISABLED new file mode 100644 index 000000000..e20e66319 --- /dev/null +++ b/tests/simple/attrib05_port_conn.v.DISABLED @@ -0,0 +1,21 @@ +module bar(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output reg out; + + always @(posedge clk) + if (rst) out <= 1'd0; + else out <= ~inp; + +endmodule + +module foo(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output wire out; + + bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out); +endmodule + diff --git a/tests/simple/attrib06_operator_suffix.v b/tests/simple/attrib06_operator_suffix.v new file mode 100644 index 000000000..e21173c58 --- /dev/null +++ b/tests/simple/attrib06_operator_suffix.v @@ -0,0 +1,23 @@ +module bar(clk, rst, inp_a, inp_b, out); + input wire clk; + input wire rst; + input wire [7:0] inp_a; + input wire [7:0] inp_b; + output reg [7:0] out; + + always @(posedge clk) + if (rst) out <= 0; + else out <= inp_a + (* ripple_adder *) inp_b; + +endmodule + +module foo(clk, rst, inp_a, inp_b, out); + input wire clk; + input wire rst; + input wire [7:0] inp_a; + input wire [7:0] inp_b; + output wire [7:0] out; + + bar bar_instance (clk, rst, inp_a, inp_b, out); +endmodule + diff --git a/tests/simple/attrib07_func_call.v.DISABLED b/tests/simple/attrib07_func_call.v.DISABLED new file mode 100644 index 000000000..f55ef2316 --- /dev/null +++ b/tests/simple/attrib07_func_call.v.DISABLED @@ -0,0 +1,21 @@ +function [7:0] do_add; + input [7:0] inp_a; + input [7:0] inp_b; + + do_add = inp_a + inp_b; + +endfunction + +module foo(clk, rst, inp_a, inp_b, out); + input wire clk; + input wire rst; + input wire [7:0] inp_a; + input wire [7:0] inp_b; + output wire [7:0] out; + + always @(posedge clk) + if (rst) out <= 0; + else out <= do_add (* combinational_adder *) (inp_a, inp_b); + +endmodule + diff --git a/tests/simple/attrib08_mod_inst.v b/tests/simple/attrib08_mod_inst.v new file mode 100644 index 000000000..c5a32234e --- /dev/null +++ b/tests/simple/attrib08_mod_inst.v @@ -0,0 +1,22 @@ +module bar(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output reg out; + + always @(posedge clk) + if (rst) out <= 1'd0; + else out <= ~inp; + +endmodule + +module foo(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output wire out; + + (* my_module_instance = 99 *) + bar bar_instance (clk, rst, inp, out); +endmodule + diff --git a/tests/simple/attrib09_case.v b/tests/simple/attrib09_case.v new file mode 100644 index 000000000..8551bf9d0 --- /dev/null +++ b/tests/simple/attrib09_case.v @@ -0,0 +1,26 @@ +module bar(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire [1:0] inp; + output reg [1:0] out; + + always @(inp) + (* full_case, parallel_case *) + case(inp) + 2'd0: out <= 2'd3; + 2'd1: out <= 2'd2; + 2'd2: out <= 2'd1; + 2'd3: out <= 2'd0; + endcase + +endmodule + +module foo(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire [1:0] inp; + output wire [1:0] out; + + bar bar_instance (clk, rst, inp, out); +endmodule + -- cgit v1.2.3 From b79bd5b3ca086718e308c75cbece0b07bbe48733 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Tue, 4 Jun 2019 10:42:42 +0200 Subject: Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog. Signed-off-by: Maciej Kurc --- tests/various/attrib05_port_conn.v | 21 +++++++++++++++++++++ tests/various/attrib05_port_conn.ys | 2 ++ tests/various/attrib07_func_call.v | 21 +++++++++++++++++++++ tests/various/attrib07_func_call.ys | 2 ++ 4 files changed, 46 insertions(+) create mode 100644 tests/various/attrib05_port_conn.v create mode 100644 tests/various/attrib05_port_conn.ys create mode 100644 tests/various/attrib07_func_call.v create mode 100644 tests/various/attrib07_func_call.ys (limited to 'tests') diff --git a/tests/various/attrib05_port_conn.v b/tests/various/attrib05_port_conn.v new file mode 100644 index 000000000..e20e66319 --- /dev/null +++ b/tests/various/attrib05_port_conn.v @@ -0,0 +1,21 @@ +module bar(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output reg out; + + always @(posedge clk) + if (rst) out <= 1'd0; + else out <= ~inp; + +endmodule + +module foo(clk, rst, inp, out); + input wire clk; + input wire rst; + input wire inp; + output wire out; + + bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out); +endmodule + diff --git a/tests/various/attrib05_port_conn.ys b/tests/various/attrib05_port_conn.ys new file mode 100644 index 000000000..27a016733 --- /dev/null +++ b/tests/various/attrib05_port_conn.ys @@ -0,0 +1,2 @@ +# Read and parse Verilog file +read_verilog attrib05_port_conn.v diff --git a/tests/various/attrib07_func_call.v b/tests/various/attrib07_func_call.v new file mode 100644 index 000000000..f55ef2316 --- /dev/null +++ b/tests/various/attrib07_func_call.v @@ -0,0 +1,21 @@ +function [7:0] do_add; + input [7:0] inp_a; + input [7:0] inp_b; + + do_add = inp_a + inp_b; + +endfunction + +module foo(clk, rst, inp_a, inp_b, out); + input wire clk; + input wire rst; + input wire [7:0] inp_a; + input wire [7:0] inp_b; + output wire [7:0] out; + + always @(posedge clk) + if (rst) out <= 0; + else out <= do_add (* combinational_adder *) (inp_a, inp_b); + +endmodule + diff --git a/tests/various/attrib07_func_call.ys b/tests/various/attrib07_func_call.ys new file mode 100644 index 000000000..774827651 --- /dev/null +++ b/tests/various/attrib07_func_call.ys @@ -0,0 +1,2 @@ +# Read and parse Verilog file +read_verilog attrib07_func_call.v -- cgit v1.2.3 From 88f59770932720cfc1e987c98e53faedd7388ed8 Mon Sep 17 00:00:00 2001 From: tux3 Date: Wed, 5 Jun 2019 00:47:54 +0200 Subject: SystemVerilog support for implicit named port connections This is the `foo foo(.port1, .port2);` SystemVerilog syntax introduced in IEEE1800-2005. --- tests/simple/run-test.sh | 3 ++- tests/tools/autotest.sh | 15 +++++++++++++-- tests/various/implicit_ports.sv | 19 +++++++++++++++++++ tests/various/implicit_ports.ys | 8 ++++++++ 4 files changed, 42 insertions(+), 3 deletions(-) create mode 100644 tests/various/implicit_ports.sv create mode 100644 tests/various/implicit_ports.ys (limited to 'tests') diff --git a/tests/simple/run-test.sh b/tests/simple/run-test.sh index aaa1cf940..967ac49f2 100755 --- a/tests/simple/run-test.sh +++ b/tests/simple/run-test.sh @@ -17,4 +17,5 @@ if ! which iverilog > /dev/null ; then exit 1 fi -exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v +shopt -s nullglob +exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.{sv,v} diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index 920474a84..0a511f29c 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -89,6 +89,13 @@ done compile_and_run() { exe="$1"; output="$2"; shift 2 + ext=${1##*.} + if [ "$ext" == "sv" ]; then + language_gen="-g2012" + else + language_gen="-g2005" + fi + if $use_modelsim; then altver=$( ls -v /opt/altera/ | grep '^[0-9]' | tail -n1; ) /opt/altera/$altver/modelsim_ase/bin/vlib work @@ -99,7 +106,7 @@ compile_and_run() { /opt/Xilinx/Vivado/$xilver/bin/xvlog $xinclude_opts -d outfile=\"$output\" "$@" /opt/Xilinx/Vivado/$xilver/bin/xelab -R work.testbench else - iverilog $include_opts -Doutfile=\"$output\" -s testbench -o "$exe" "$@" + iverilog $language_gen $include_opts -Doutfile=\"$output\" -s testbench -o "$exe" "$@" vvp -n "$exe" fi } @@ -110,7 +117,7 @@ for fn do bn=${fn%.*} ext=${fn##*.} - if [[ "$ext" != "v" ]] && [[ "$ext" != "aag" ]] && [[ "$ext" != "aig" ]]; then + if [[ "$ext" != "v" ]] && [[ "$ext" != "sv" ]] && [[ "$ext" != "aag" ]] && [[ "$ext" != "aig" ]]; then echo "Invalid argument: $fn" >&2 exit 1 fi @@ -123,6 +130,10 @@ do echo -n "Test: $bn " fi + if [ "$ext" == sv ]; then + frontend="$frontend -sv" + fi + rm -f ${bn}.{err,log,skip} mkdir -p ${bn}.out rm -rf ${bn}.out/* diff --git a/tests/various/implicit_ports.sv b/tests/various/implicit_ports.sv new file mode 100644 index 000000000..6a766bd51 --- /dev/null +++ b/tests/various/implicit_ports.sv @@ -0,0 +1,19 @@ +// Test implicit port connections +module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] result); + assign cout = cin; + assign result = a + b; +endmodule + +module named_ports(output [2:0] alu_result, output cout); + wire [2:0] a = 3'b010, b = 3'b100; + wire cin = 1; + + alu alu ( + .a(a), + .b, // Implicit connection is equivalent to .b(b) + .cin(), // Explicitely unconnected + .cout(cout), + .result(alu_result) + ); +endmodule + diff --git a/tests/various/implicit_ports.ys b/tests/various/implicit_ports.ys new file mode 100644 index 000000000..7b4764921 --- /dev/null +++ b/tests/various/implicit_ports.ys @@ -0,0 +1,8 @@ +read_verilog -sv implicit_ports.sv +proc; opt + +flatten +select -module named_ports + +sat -verify -prove alu_result 6 +sat -verify -set-all-undef cout -- cgit v1.2.3 From 3e76e3a6fa4355e7223b10bba394f986d6821551 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 6 Jun 2019 11:54:38 -0700 Subject: Add tests, fix for != --- tests/various/muxpack.v | 36 ++++++++++++++++++++++++++++++++++++ tests/various/muxpack.ys | 42 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 78 insertions(+) create mode 100644 tests/various/muxpack.v create mode 100644 tests/various/muxpack.ys (limited to 'tests') diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v new file mode 100644 index 000000000..abc87ba44 --- /dev/null +++ b/tests/various/muxpack.v @@ -0,0 +1,36 @@ +module mux_if_unbal_4_1 #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); +always @* + if (s == 0) o <= i[0*W+:W]; + else if (s == 1) o <= i[1*W+:W]; + else if (s == 2) o <= i[2*W+:W]; + else if (s == 3) o <= i[3*W+:W]; + else o <= {W{1'bx}}; + +endmodule + +module mux_if_unbal_5_3 #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); +always @* begin + o <= {W{1'bx}}; + if (s == 0) o <= i[0*W+:W]; + if (s == 1) o <= i[1*W+:W]; + if (s == 2) o <= i[2*W+:W]; + if (s == 3) o <= i[3*W+:W]; + if (s == 4) o <= i[4*W+:W]; +end + +endmodule + +module mux_if_unbal_5_3_invert #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); +always @* + if (s != 0) + if (s != 1) + if (s != 2) + if (s != 3) + if (s != 4) o <= i[4*W+:W]; + else o <= i[0*W+:W]; + else o <= i[3*W+:W]; + else o <= i[2*W+:W]; + else o <= i[1*W+:W]; + else o <= {W{1'bx}}; + +endmodule diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys new file mode 100644 index 000000000..58c01cf05 --- /dev/null +++ b/tests/various/muxpack.ys @@ -0,0 +1,42 @@ +read_verilog muxpack.v +design -save read +hierarchy -top mux_if_unbal_4_1 +prep +design -save gold +muxpack +opt +stat +select -assert-count 1 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top mux_if_unbal_5_3 +prep +design -save gold +muxpack +opt +stat +select -assert-count 1 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top mux_if_unbal_5_3_invert +prep +design -save gold +muxpack +opt +stat +select -assert-count 1 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter -- cgit v1.2.3 From 5d4eca5a298d2f98de220cfd0efe5452ab4052d8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 6 Jun 2019 11:59:41 -0700 Subject: Add a few more special case tests --- tests/various/muxpack.v | 23 +++++++++++++++++++++++ tests/various/muxpack.ys | 28 ++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+) (limited to 'tests') diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index abc87ba44..333908fcb 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -34,3 +34,26 @@ always @* else o <= {W{1'bx}}; endmodule + +module mux_if_unbal_5_3_width_mismatch #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); +always @* begin + o <= {W{1'bx}}; + if (s == 0) o <= i[0*W+:W]; + if (s == 1) o <= i[1*W+:W]; + if (s == 2) o[W-2:0] <= i[2*W+:W-1]; + if (s == 3) o <= i[3*W+:W]; + if (s == 4) o <= i[4*W+:W]; +end + +endmodule + +module mux_if_unbal_5_3_missing #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); +always @* begin + if (s == 0) o <= i[0*W+:W]; +// else if (s == 1) o <= i[1*W+:W]; +// else if (s == 2) o <= i[2*W+:W]; + else if (s == 3) o <= i[3*W+:W]; + else o <= {W{1'bx}}; +end + +endmodule diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index 58c01cf05..174eea74b 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -40,3 +40,31 @@ design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top mux_if_unbal_5_3_width_mismatch +prep +design -save gold +muxpack +opt +stat +select -assert-count 2 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top mux_if_unbal_5_3_missing +prep +design -save gold +muxpack +opt +stat +select -assert-count 1 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter -- cgit v1.2.3 From b8620f7b3dde4460e5a8ed3ea7fd7aef54aa7da1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 6 Jun 2019 12:03:44 -0700 Subject: One more and tidy up --- tests/various/muxpack.v | 18 +++++++++++++----- tests/various/muxpack.ys | 16 +++++++++++++++- 2 files changed, 28 insertions(+), 6 deletions(-) (limited to 'tests') diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index 333908fcb..c2c2537a0 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -5,7 +5,6 @@ always @* else if (s == 2) o <= i[2*W+:W]; else if (s == 3) o <= i[3*W+:W]; else o <= {W{1'bx}}; - endmodule module mux_if_unbal_5_3 #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); @@ -17,7 +16,6 @@ always @* begin if (s == 3) o <= i[3*W+:W]; if (s == 4) o <= i[4*W+:W]; end - endmodule module mux_if_unbal_5_3_invert #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); @@ -32,7 +30,6 @@ always @* else o <= i[2*W+:W]; else o <= i[1*W+:W]; else o <= {W{1'bx}}; - endmodule module mux_if_unbal_5_3_width_mismatch #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); @@ -44,10 +41,9 @@ always @* begin if (s == 3) o <= i[3*W+:W]; if (s == 4) o <= i[4*W+:W]; end - endmodule -module mux_if_unbal_5_3_missing #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); +module mux_if_unbal_4_1_missing #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); always @* begin if (s == 0) o <= i[0*W+:W]; // else if (s == 1) o <= i[1*W+:W]; @@ -55,5 +51,17 @@ always @* begin else if (s == 3) o <= i[3*W+:W]; else o <= {W{1'bx}}; end +endmodule +module mux_if_unbal_5_3_order #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); +always @* begin + o <= {W{1'bx}}; + if (s == 3) o <= i[3*W+:W]; + if (s == 2) o <= i[2*W+:W]; + if (s == 1) o <= i[1*W+:W]; + if (s == 4) o <= i[4*W+:W]; + if (s == 0) o <= i[0*W+:W]; +end endmodule + + diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index 174eea74b..a967ddfef 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -56,7 +56,21 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter design -load read -hierarchy -top mux_if_unbal_5_3_missing +hierarchy -top mux_if_unbal_4_1_missing +prep +design -save gold +muxpack +opt +stat +select -assert-count 1 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top mux_if_unbal_5_3_order prep design -save gold muxpack -- cgit v1.2.3 From 705388eb24022d2a310ae72cd81e67a2f0ce7586 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 6 Jun 2019 12:44:06 -0700 Subject: Add non exclusive test --- tests/various/muxpack.v | 20 ++++++++++++++++++++ tests/various/muxpack.ys | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) (limited to 'tests') diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index c2c2537a0..e847fef27 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -64,4 +64,24 @@ always @* begin end endmodule +module mux_if_unbal_4_1_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); +always @* + if (s == 0) o <= i[0*W+:W]; + else if (s == 1) o <= i[1*W+:W]; + else if (s == 2) o <= i[2*W+:W]; + else if (s == 3) o <= i[3*W+:W]; + else if (s == 0) o <= {W{1'b0}}; + else o <= {W{1'bx}}; +endmodule +module mux_if_unbal_5_3_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); +always @* begin + o <= {W{1'bx}}; + if (s == 0) o <= i[0*W+:W]; + if (s == 1) o <= i[1*W+:W]; + if (s == 2) o <= i[2*W+:W]; + if (s == 3) o <= i[3*W+:W]; + if (s == 4) o <= i[4*W+:W]; + if (s == 0) o <= i[2*W+:W]; +end +endmodule diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index a967ddfef..178860b88 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -6,6 +6,7 @@ design -save gold muxpack opt stat +select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate design -import gold -as gold @@ -20,6 +21,7 @@ design -save gold muxpack opt stat +select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate design -import gold -as gold @@ -34,6 +36,7 @@ design -save gold muxpack opt stat +select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate design -import gold -as gold @@ -48,6 +51,7 @@ design -save gold muxpack opt stat +select -assert-count 0 t:$mux select -assert-count 2 t:$pmux design -stash gate design -import gold -as gold @@ -62,6 +66,7 @@ design -save gold muxpack opt stat +select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate design -import gold -as gold @@ -76,6 +81,37 @@ design -save gold muxpack opt stat +select -assert-count 0 t:$mux +select -assert-count 1 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top mux_if_unbal_4_1_nonexcl +prep +design -save gold +muxpack +opt +stat +select -assert-count 0 t:$mux +select -assert-count 1 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top mux_if_unbal_5_3_nonexcl +prep +design -save gold +muxpack +opt +stat +select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate design -import gold -as gold -- cgit v1.2.3 From ccdf989025e57da7dfd5ab609676ebe3cfb2c2d6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 6 Jun 2019 13:51:22 -0700 Subject: Support cascading $pmux.A with $mux.A and $mux.B --- tests/various/muxpack.v | 25 +++++++++++++++++++++++++ tests/various/muxpack.ys | 15 +++++++++++++++ 2 files changed, 40 insertions(+) (limited to 'tests') diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index e847fef27..fe0150532 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -85,3 +85,28 @@ always @* begin if (s == 0) o <= i[2*W+:W]; end endmodule + +module mux_case_unbal_7_7#(parameter N=7, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); +always @* begin + o <= {W{1'bx}}; + case (s) + 0: o <= i[0*W+:W]; + default: + case (s) + 1: o <= i[1*W+:W]; + 2: o <= i[2*W+:W]; + default: + case (s) + 3: o <= i[3*W+:W]; + 4: o <= i[4*W+:W]; + 5: o <= i[5*W+:W]; + default: + case (s) + 6: o <= i[6*W+:W]; + default: o <= i[7*W+:W]; + endcase + endcase + endcase + endcase +end +endmodule diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index 178860b88..4dcb9ed89 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -118,3 +118,18 @@ design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top mux_case_unbal_7_7 +prep +design -save gold +muxpack +opt +stat +select -assert-count 0 t:$mux +select -assert-count 1 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter -- cgit v1.2.3 From 0a66720f6f67b087fe6342d01d45944506240942 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 6 Jun 2019 14:01:42 -0700 Subject: Fix warnings --- tests/various/muxpack.v | 4 ++-- tests/various/muxpack.ys | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'tests') diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index fe0150532..7c189fff8 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -74,7 +74,7 @@ always @* else o <= {W{1'bx}}; endmodule -module mux_if_unbal_5_3_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); +module mux_if_unbal_5_3_nonexcl #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); always @* begin o <= {W{1'bx}}; if (s == 0) o <= i[0*W+:W]; @@ -86,7 +86,7 @@ always @* begin end endmodule -module mux_case_unbal_7_7#(parameter N=7, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); +module mux_case_unbal_8_7#(parameter N=8, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); always @* begin o <= {W{1'bx}}; case (s) diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index 4dcb9ed89..0c5b82818 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -120,7 +120,7 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter design -load read -hierarchy -top mux_case_unbal_7_7 +hierarchy -top mux_case_unbal_8_7 prep design -save gold muxpack -- cgit v1.2.3 From 5c277c6325b78bfe18cf294b63ea69ff272e69c5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 6 Jun 2019 14:21:34 -0700 Subject: Fix and test for balanced case --- tests/various/muxpack.v | 26 ++++++++++++++++++++++++++ tests/various/muxpack.ys | 15 +++++++++++++++ 2 files changed, 41 insertions(+) (limited to 'tests') diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index 7c189fff8..f1bd5ea8e 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -110,3 +110,29 @@ always @* begin endcase end endmodule + +module mux_if_bal_8_2 #(parameter N=8, parameter W=2) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); +always @* + if (s[0] == 1'b0) + if (s[1] == 1'b0) + if (s[2] == 1'b0) + o <= i[0*W+:W]; + else + o <= i[1*W+:W]; + else + if (s[2] == 1'b0) + o <= i[2*W+:W]; + else + o <= i[3*W+:W]; + else + if (s[1] == 1'b0) + if (s[2] == 1'b0) + o <= i[4*W+:W]; + else + o <= i[5*W+:W]; + else + if (s[2] == 1'b0) + o <= i[6*W+:W]; + else + o <= i[7*W+:W]; +endmodule diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index 0c5b82818..9ea743b9f 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -133,3 +133,18 @@ design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top mux_if_bal_8_2 +prep +design -save gold +muxpack +opt +stat +select -assert-count 7 t:$mux +select -assert-count 0 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter -- cgit v1.2.3 From a0b57f2a6ffae3b5770e38bf5a9af0df50db8522 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 7 Jun 2019 11:46:16 +0200 Subject: Cleanup tux3-implicit_named_connection Signed-off-by: Clifford Wolf --- tests/simple/implicit_ports.sv | 16 ++++++++++++++++ tests/various/implicit_ports.sv | 19 ------------------- tests/various/implicit_ports.ys | 8 -------- 3 files changed, 16 insertions(+), 27 deletions(-) create mode 100644 tests/simple/implicit_ports.sv delete mode 100644 tests/various/implicit_ports.sv delete mode 100644 tests/various/implicit_ports.ys (limited to 'tests') diff --git a/tests/simple/implicit_ports.sv b/tests/simple/implicit_ports.sv new file mode 100644 index 000000000..8b0a6f386 --- /dev/null +++ b/tests/simple/implicit_ports.sv @@ -0,0 +1,16 @@ +// Test implicit port connections +module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] result); + assign cout = cin; + assign result = a + b; +endmodule + +module named_ports(input [2:0] a, b, output [2:0] alu_result, output cout); + wire cin = 1; + alu alu ( + .a(a), + .b, // Implicit connection is equivalent to .b(b) + .cin(), // Explicitely unconnected + .cout(cout), + .result(alu_result) + ); +endmodule diff --git a/tests/various/implicit_ports.sv b/tests/various/implicit_ports.sv deleted file mode 100644 index 6a766bd51..000000000 --- a/tests/various/implicit_ports.sv +++ /dev/null @@ -1,19 +0,0 @@ -// Test implicit port connections -module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] result); - assign cout = cin; - assign result = a + b; -endmodule - -module named_ports(output [2:0] alu_result, output cout); - wire [2:0] a = 3'b010, b = 3'b100; - wire cin = 1; - - alu alu ( - .a(a), - .b, // Implicit connection is equivalent to .b(b) - .cin(), // Explicitely unconnected - .cout(cout), - .result(alu_result) - ); -endmodule - diff --git a/tests/various/implicit_ports.ys b/tests/various/implicit_ports.ys deleted file mode 100644 index 7b4764921..000000000 --- a/tests/various/implicit_ports.ys +++ /dev/null @@ -1,8 +0,0 @@ -read_verilog -sv implicit_ports.sv -proc; opt - -flatten -select -module named_ports - -sat -verify -prove alu_result 6 -sat -verify -set-all-undef cout -- cgit v1.2.3 From f01a61f093528e5111e5dac8aedbf8c7c468be1c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Fri, 7 Jun 2019 13:12:25 +0200 Subject: Rename implicit_ports.sv test to implicit_ports.v Signed-off-by: Clifford Wolf --- tests/simple/implicit_ports.sv | 16 ---------------- tests/simple/implicit_ports.v | 16 ++++++++++++++++ 2 files changed, 16 insertions(+), 16 deletions(-) delete mode 100644 tests/simple/implicit_ports.sv create mode 100644 tests/simple/implicit_ports.v (limited to 'tests') diff --git a/tests/simple/implicit_ports.sv b/tests/simple/implicit_ports.sv deleted file mode 100644 index 8b0a6f386..000000000 --- a/tests/simple/implicit_ports.sv +++ /dev/null @@ -1,16 +0,0 @@ -// Test implicit port connections -module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] result); - assign cout = cin; - assign result = a + b; -endmodule - -module named_ports(input [2:0] a, b, output [2:0] alu_result, output cout); - wire cin = 1; - alu alu ( - .a(a), - .b, // Implicit connection is equivalent to .b(b) - .cin(), // Explicitely unconnected - .cout(cout), - .result(alu_result) - ); -endmodule diff --git a/tests/simple/implicit_ports.v b/tests/simple/implicit_ports.v new file mode 100644 index 000000000..8b0a6f386 --- /dev/null +++ b/tests/simple/implicit_ports.v @@ -0,0 +1,16 @@ +// Test implicit port connections +module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] result); + assign cout = cin; + assign result = a + b; +endmodule + +module named_ports(input [2:0] a, b, output [2:0] alu_result, output cout); + wire cin = 1; + alu alu ( + .a(a), + .b, // Implicit connection is equivalent to .b(b) + .cin(), // Explicitely unconnected + .cout(cout), + .result(alu_result) + ); +endmodule -- cgit v1.2.3 From 0f6e914ef63d06ae77b54d246b61118c19647f26 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 7 Jun 2019 08:34:58 -0700 Subject: Another muxpack test --- tests/various/muxpack.v | 17 +++++++++++++++++ tests/various/muxpack.ys | 15 +++++++++++++++ 2 files changed, 32 insertions(+) (limited to 'tests') diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index f1bd5ea8e..41dfed396 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -136,3 +136,20 @@ always @* else o <= i[7*W+:W]; endmodule + +module mux_if_bal_5_1 #(parameter N=5, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); +always @* + if (s[0] == 1'b0) + if (s[1] == 1'b0) + if (s[2] == 1'b0) + o <= i[0*W+:W]; + else + o <= i[1*W+:W]; + else + if (s[2] == 1'b0) + o <= i[2*W+:W]; + else + o <= i[3*W+:W]; + else + o <= i[4*W+:W]; +endmodule diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index 9ea743b9f..dd3c143d8 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -148,3 +148,18 @@ design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top mux_if_bal_5_1 +prep +design -save gold +muxpack +opt +stat +select -assert-count 2 t:$mux +select -assert-count 1 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter -- cgit v1.2.3 From 1b113a05742377f5b18d52bc5bf50b1991e88c19 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 7 Jun 2019 11:05:25 -0700 Subject: Add symbols to AIGER test inputs for ABC --- tests/aiger/and.aag | 5 ----- tests/aiger/and.aig | 3 --- tests/aiger/and_.aag | 8 ++++++++ tests/aiger/and_.aig | 5 +++++ tests/aiger/buffer.aag | 2 ++ tests/aiger/buffer.aig | 2 ++ tests/aiger/cnt1.aag | 1 + tests/aiger/cnt1.aig | 1 + tests/aiger/cnt1e.aag | 1 + tests/aiger/cnt1e.aig | 3 ++- tests/aiger/false.aag | 1 + tests/aiger/false.aig | 1 + tests/aiger/inverter.aag | 2 ++ tests/aiger/inverter.aig | 2 ++ tests/aiger/notcnt1e.aag | 1 + tests/aiger/notcnt1e.aig | 3 ++- tests/aiger/or.aag | 5 ----- tests/aiger/or.aig | 3 --- tests/aiger/or_.aag | 8 ++++++++ tests/aiger/or_.aig | 5 +++++ tests/aiger/toggle.aag | 2 ++ tests/aiger/toggle.aig | 2 ++ tests/aiger/true.aag | 1 + tests/aiger/true.aig | 1 + 24 files changed, 50 insertions(+), 18 deletions(-) delete mode 100644 tests/aiger/and.aag delete mode 100644 tests/aiger/and.aig create mode 100644 tests/aiger/and_.aag create mode 100644 tests/aiger/and_.aig delete mode 100644 tests/aiger/or.aag delete mode 100644 tests/aiger/or.aig create mode 100644 tests/aiger/or_.aag create mode 100644 tests/aiger/or_.aig (limited to 'tests') diff --git a/tests/aiger/and.aag b/tests/aiger/and.aag deleted file mode 100644 index d1ef2c5a5..000000000 --- a/tests/aiger/and.aag +++ /dev/null @@ -1,5 +0,0 @@ -aag 3 2 0 1 1 -2 -4 -6 -6 2 4 diff --git a/tests/aiger/and.aig b/tests/aiger/and.aig deleted file mode 100644 index da0fa0719..000000000 --- a/tests/aiger/and.aig +++ /dev/null @@ -1,3 +0,0 @@ -aig 3 2 0 1 1 -6 - \ No newline at end of file diff --git a/tests/aiger/and_.aag b/tests/aiger/and_.aag new file mode 100644 index 000000000..cadd505f0 --- /dev/null +++ b/tests/aiger/and_.aag @@ -0,0 +1,8 @@ +aag 3 2 0 1 1 +2 +4 +6 +6 2 4 +i0 pi0 +i1 pi1 +o0 po0 diff --git a/tests/aiger/and_.aig b/tests/aiger/and_.aig new file mode 100644 index 000000000..13c7a0c17 --- /dev/null +++ b/tests/aiger/and_.aig @@ -0,0 +1,5 @@ +aig 3 2 0 1 1 +6 +i0 pi0 +i1 pi1 +o0 po0 diff --git a/tests/aiger/buffer.aag b/tests/aiger/buffer.aag index 94a6fb1ed..211106ed6 100644 --- a/tests/aiger/buffer.aag +++ b/tests/aiger/buffer.aag @@ -1,3 +1,5 @@ aag 1 1 0 1 0 2 2 +i0 pi0 +o0 po0 diff --git a/tests/aiger/buffer.aig b/tests/aiger/buffer.aig index 0c715fdeb..01df6f1cf 100644 --- a/tests/aiger/buffer.aig +++ b/tests/aiger/buffer.aig @@ -1,2 +1,4 @@ aig 1 1 0 1 0 2 +i0 pi0 +o0 po0 diff --git a/tests/aiger/cnt1.aag b/tests/aiger/cnt1.aag index ce4f28fcb..75598862c 100644 --- a/tests/aiger/cnt1.aag +++ b/tests/aiger/cnt1.aag @@ -1,3 +1,4 @@ aag 1 0 1 0 0 1 2 3 2 +b0 po0 diff --git a/tests/aiger/cnt1.aig b/tests/aiger/cnt1.aig index 8d0ba13b1..6fcf62522 100644 --- a/tests/aiger/cnt1.aig +++ b/tests/aiger/cnt1.aig @@ -1,3 +1,4 @@ aig 1 0 1 0 0 1 3 2 +b0 po0 diff --git a/tests/aiger/cnt1e.aag b/tests/aiger/cnt1e.aag index 6db3f0ffd..35cd5a482 100644 --- a/tests/aiger/cnt1e.aag +++ b/tests/aiger/cnt1e.aag @@ -6,3 +6,4 @@ aag 5 1 1 0 3 1 8 4 2 10 9 7 b0 AIGER_NEVER +i0 po0 diff --git a/tests/aiger/cnt1e.aig b/tests/aiger/cnt1e.aig index d8d159f11..7284dd42a 100644 --- a/tests/aiger/cnt1e.aig +++ b/tests/aiger/cnt1e.aig @@ -1,4 +1,5 @@ aig 5 1 1 0 3 1 10 4 -b0 AIGER_NEVER +i0 po0 +b0 AIGER_NEVER diff --git a/tests/aiger/false.aag b/tests/aiger/false.aag index 421e64a91..bab4a06a6 100644 --- a/tests/aiger/false.aag +++ b/tests/aiger/false.aag @@ -1,2 +1,3 @@ aag 0 0 0 1 0 0 +o0 po0 diff --git a/tests/aiger/false.aig b/tests/aiger/false.aig index ad7d039fa..4dc442d7b 100644 --- a/tests/aiger/false.aig +++ b/tests/aiger/false.aig @@ -1,2 +1,3 @@ aig 0 0 0 1 0 0 +o0 po0 diff --git a/tests/aiger/inverter.aag b/tests/aiger/inverter.aag index ff7c28542..428bad9e4 100644 --- a/tests/aiger/inverter.aag +++ b/tests/aiger/inverter.aag @@ -1,3 +1,5 @@ aag 1 1 0 1 0 2 3 +i0 pi0 +o0 po0 diff --git a/tests/aiger/inverter.aig b/tests/aiger/inverter.aig index 525d82392..5bec90ae3 100644 --- a/tests/aiger/inverter.aig +++ b/tests/aiger/inverter.aig @@ -1,2 +1,4 @@ aig 1 1 0 1 0 3 +i0 pi0 +o0 po0 diff --git a/tests/aiger/notcnt1e.aag b/tests/aiger/notcnt1e.aag index 141c864f7..2ed645d84 100644 --- a/tests/aiger/notcnt1e.aag +++ b/tests/aiger/notcnt1e.aag @@ -6,3 +6,4 @@ aag 5 1 1 0 3 1 8 4 2 10 9 7 b0 AIGER_NEVER +i0 pi0 diff --git a/tests/aiger/notcnt1e.aig b/tests/aiger/notcnt1e.aig index 7c85a7290..fd7e94508 100644 --- a/tests/aiger/notcnt1e.aig +++ b/tests/aiger/notcnt1e.aig @@ -1,4 +1,5 @@ aig 5 1 1 0 3 1 10 5 -b0 AIGER_NEVER +i0 pi0 +b0 AIGER_NEVER diff --git a/tests/aiger/or.aag b/tests/aiger/or.aag deleted file mode 100644 index f780e339f..000000000 --- a/tests/aiger/or.aag +++ /dev/null @@ -1,5 +0,0 @@ -aag 3 2 0 1 1 -2 -4 -7 -6 3 5 diff --git a/tests/aiger/or.aig b/tests/aiger/or.aig deleted file mode 100644 index 75c9e4480..000000000 --- a/tests/aiger/or.aig +++ /dev/null @@ -1,3 +0,0 @@ -aig 3 2 0 1 1 -7 - \ No newline at end of file diff --git a/tests/aiger/or_.aag b/tests/aiger/or_.aag new file mode 100644 index 000000000..0f619dba3 --- /dev/null +++ b/tests/aiger/or_.aag @@ -0,0 +1,8 @@ +aag 3 2 0 1 1 +2 +4 +7 +6 3 5 +i0 pi0 +i1 pi1 +o0 po0 diff --git a/tests/aiger/or_.aig b/tests/aiger/or_.aig new file mode 100644 index 000000000..051687512 --- /dev/null +++ b/tests/aiger/or_.aig @@ -0,0 +1,5 @@ +aig 3 2 0 1 1 +7 +i0 pi0 +i1 pi1 +o0 po0 diff --git a/tests/aiger/toggle.aag b/tests/aiger/toggle.aag index 09651012d..b1a1582d7 100644 --- a/tests/aiger/toggle.aag +++ b/tests/aiger/toggle.aag @@ -2,3 +2,5 @@ aag 1 0 1 2 0 2 3 2 3 +o0 po0 +o1 po1 diff --git a/tests/aiger/toggle.aig b/tests/aiger/toggle.aig index b69e21aaf..68b41763f 100644 --- a/tests/aiger/toggle.aig +++ b/tests/aiger/toggle.aig @@ -2,3 +2,5 @@ aig 1 0 1 2 0 3 2 3 +o0 po0 +o1 po1 diff --git a/tests/aiger/true.aag b/tests/aiger/true.aag index 366893648..66a9eab46 100644 --- a/tests/aiger/true.aag +++ b/tests/aiger/true.aag @@ -1,2 +1,3 @@ aag 0 0 0 1 0 1 +o0 po0 diff --git a/tests/aiger/true.aig b/tests/aiger/true.aig index 10086f389..f9bad6000 100644 --- a/tests/aiger/true.aig +++ b/tests/aiger/true.aig @@ -1,2 +1,3 @@ aig 0 0 0 1 0 1 +o0 po0 -- cgit v1.2.3 From ebe29b66593414d0317879359d1f1d1f61a9ecc4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 7 Jun 2019 11:05:36 -0700 Subject: Use ABC to convert AIGER to Verilog, then sat against Yosys --- tests/aiger/run-test.sh | 36 +++++++++++++++--------------------- 1 file changed, 15 insertions(+), 21 deletions(-) (limited to 'tests') diff --git a/tests/aiger/run-test.sh b/tests/aiger/run-test.sh index e0a34f023..70300d305 100755 --- a/tests/aiger/run-test.sh +++ b/tests/aiger/run-test.sh @@ -1,24 +1,18 @@ #!/bin/bash -OPTIND=1 -seed="" # default to no seed specified -while getopts "S:" opt -do - case "$opt" in - S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space - seed="SEED=$arg" ;; - esac +set -e +for aig in *.aig; do + ../../yosys-abc -c "read -c $aig; write ${aig%.*}_ref.v" + ../../yosys -p " +read_verilog ${aig%.*}_ref.v +prep +design -stash gold +read_aiger -clk_name clock $aig +prep +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports -seq 16 miter +" done -shift "$((OPTIND-1))" - -# check for Icarus Verilog -if ! which iverilog > /dev/null ; then - echo "$0: Error: Icarus Verilog 'iverilog' not found." - exit 1 -fi - -echo "===== AAG ======" -${MAKE:-make} -f ../tools/autotest.mk $seed *.aag EXTRA_FLAGS="-f aiger" - -echo "===== AIG ======" -exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.aig EXTRA_FLAGS="-f aiger" -- cgit v1.2.3 From abc40924ed5dc4aba91c7f1e83ca90f54e9eb455 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 7 Jun 2019 11:06:57 -0700 Subject: Use ABC to convert from AIGER to Verilog --- tests/tools/autotest.sh | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index 0a511f29c..23964a751 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -146,9 +146,10 @@ do rm -f ${bn}_ref.fir if [[ "$ext" == "v" ]]; then egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext} + elif [[ "$ext" == "aig" ]] || [[ "$ext" == "aag" ]]; then + "$toolsdir"/../../yosys-abc -c "read_aiger ../${fn}; write ${bn}_ref.v" else - "$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn} - frontend="verilog -noblackbox" + cp ../${fn} ${bn}_ref.${ext} fi if [ ! -f ../${bn}_tb.v ]; then -- cgit v1.2.3 From 65924fd12f48b4ec5a4d51efeea977992d033ecf Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 7 Jun 2019 11:28:05 -0700 Subject: Test *.aag too, by using *.aig as reference --- tests/aiger/run-test.sh | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'tests') diff --git a/tests/aiger/run-test.sh b/tests/aiger/run-test.sh index 70300d305..e56d0fa80 100755 --- a/tests/aiger/run-test.sh +++ b/tests/aiger/run-test.sh @@ -1,6 +1,25 @@ #!/bin/bash set -e + +for aag in *.aag; do + # Since ABC cannot read *.aag, read the *.aig instead + # (which would have been created by the reference aig2aig utility) + ../../yosys-abc -c "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v" + ../../yosys -p " +read_verilog ${aag%.*}_ref.v +prep +design -stash gold +read_aiger -clk_name clock $aag +prep +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports -seq 16 miter +" +done + for aig in *.aig; do ../../yosys-abc -c "read -c $aig; write ${aig%.*}_ref.v" ../../yosys -p " -- cgit v1.2.3 From e263bc249b905195120fbc074c6f80d03fb21cf8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 7 Jun 2019 11:54:29 -0700 Subject: Add nonexclusive test from @cliffordwolf --- tests/various/muxpack.v | 13 +++++++++++++ tests/various/muxpack.ys | 15 +++++++++++++++ 2 files changed, 28 insertions(+) (limited to 'tests') diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index 41dfed396..f3c25db8d 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -153,3 +153,16 @@ always @* else o <= i[4*W+:W]; endmodule + +module cliffordwolf_nonexclusive_select ( + input wire x, y, z, + input wire a, b, c, d, + output reg o +); + always @* begin + o = a; + if (x) o = b; + if (y) o = c; + if (z) o = d; + end +endmodule diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index dd3c143d8..7c3fe5070 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -163,3 +163,18 @@ design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top cliffordwolf_nonexclusive_select +prep +design -save gold +muxpack +opt +stat +select -assert-count 0 t:$mux +select -assert-count 1 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter -- cgit v1.2.3 From 1da12c5071a738504d22e68d66cab7c5c5afb07e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 7 Jun 2019 12:12:11 -0700 Subject: Add @cliffordwolf freduce testcase --- tests/various/muxpack.v | 13 +++++++++++++ tests/various/muxpack.ys | 17 +++++++++++++++++ 2 files changed, 30 insertions(+) (limited to 'tests') diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index f3c25db8d..d45ce4045 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -166,3 +166,16 @@ module cliffordwolf_nonexclusive_select ( if (z) o = d; end endmodule + +module cliffordwolf_freduce ( + input wire [1:0] s, + input wire a, b, c, d, + output reg [3:0] o +); + always @* begin + o = {4{a}}; + if (s == 0) o = {3{b}}; + if (s == 1) o = {2{c}}; + if (s == 2) o = d; + end +endmodule diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index 7c3fe5070..afdacdf30 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -178,3 +178,20 @@ design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top cliffordwolf_freduce +prep +design -save gold +proc; opt; freduce; opt +write_verilog -noexpr -norename +muxpack +opt +stat +select -assert-count 0 t:$mux +select -assert-count 1 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter -- cgit v1.2.3 From b959bf79c004fdf81ccc397d5aa774b67a09d6da Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 7 Jun 2019 15:35:15 -0700 Subject: Add nonexcl case test, comment out two others --- tests/various/muxpack.v | 18 ++++++++++++++ tests/various/muxpack.ys | 61 +++++++++++++++++++++++++++++++----------------- 2 files changed, 57 insertions(+), 22 deletions(-) (limited to 'tests') diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index d45ce4045..3a1086dbf 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -179,3 +179,21 @@ module cliffordwolf_freduce ( if (s == 2) o = d; end endmodule + +module case_nonexclusive_select ( + input wire [1:0] x, y, + input wire a, b, c, d, e, + output reg o +); + always @* begin + case (x) + 0, 2: o = b; + 1: o = c; + default: begin + o = a; + if (y == 0) o = d; + if (y == 1) o = e; + end + endcase + end +endmodule diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index afdacdf30..579dad8d3 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -1,5 +1,6 @@ read_verilog muxpack.v design -save read + hierarchy -top mux_if_unbal_4_1 prep design -save gold @@ -29,20 +30,21 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter -design -load read -hierarchy -top mux_if_unbal_5_3_invert -prep -design -save gold -muxpack -opt -stat -select -assert-count 0 t:$mux -select -assert-count 1 t:$pmux -design -stash gate -design -import gold -as gold -design -import gate -as gate -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter +# TODO: Currently ExclusiveDatabase only analyses $eq cells +#design -load read +#hierarchy -top mux_if_unbal_5_3_invert +#prep +#design -save gold +#muxpack +#opt +#stat +#select -assert-count 0 t:$mux +#select -assert-count 1 t:$pmux +#design -stash gate +#design -import gold -as gold +#design -import gate -as gate +#miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -show-ports miter design -load read hierarchy -top mux_if_unbal_5_3_width_mismatch @@ -156,8 +158,8 @@ design -save gold muxpack opt stat -select -assert-count 2 t:$mux -select -assert-count 1 t:$pmux +select -assert-count 4 t:$mux +select -assert-count 0 t:$pmux design -stash gate design -import gold -as gold design -import gate -as gate @@ -171,25 +173,40 @@ design -save gold muxpack opt stat -select -assert-count 0 t:$mux -select -assert-count 1 t:$pmux +select -assert-count 3 t:$mux +select -assert-count 0 t:$pmux design -stash gate design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter +#design -load read +#hierarchy -top cliffordwolf_freduce +#prep +#design -save gold +#proc; opt; freduce; opt +#show +#muxpack +#opt +#stat +#select -assert-count 0 t:$mux +#select -assert-count 1 t:$pmux +#design -stash gate +#design -import gold -as gold +#design -import gate -as gate +#miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -show-ports miter + design -load read -hierarchy -top cliffordwolf_freduce +hierarchy -top case_nonexclusive_select prep design -save gold -proc; opt; freduce; opt -write_verilog -noexpr -norename muxpack opt stat select -assert-count 0 t:$mux -select -assert-count 1 t:$pmux +select -assert-count 2 t:$pmux design -stash gate design -import gold -as gold design -import gate -as gate -- cgit v1.2.3 From a91ea6612a73568782c80bd12ce2875353e2b5c5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 10 Jun 2019 10:27:55 -0700 Subject: Add some more comments --- tests/aiger/run-test.sh | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/aiger/run-test.sh b/tests/aiger/run-test.sh index e56d0fa80..f52eb4ac1 100755 --- a/tests/aiger/run-test.sh +++ b/tests/aiger/run-test.sh @@ -2,9 +2,14 @@ set -e +# NB: *.aag and *.aig must contain a symbol table naming the primary +# inputs and outputs, otherwise ABC and Yosys will name them +# arbitrarily (and inconsistently with each other). + for aag in *.aag; do # Since ABC cannot read *.aag, read the *.aig instead - # (which would have been created by the reference aig2aig utility) + # (which would have been created by the reference aig2aig utility, + # available from http://fmv.jku.at/aiger/) ../../yosys-abc -c "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v" ../../yosys -p " read_verilog ${aag%.*}_ref.v -- cgit v1.2.3 From c314ca3c51579a9c5305cbf9a69635e123db0423 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 10 Jun 2019 16:16:26 -0700 Subject: Add test --- tests/various/shregmap.v | 22 ++++++++++++++++++++++ tests/various/shregmap.ys | 31 +++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+) create mode 100644 tests/various/shregmap.v create mode 100644 tests/various/shregmap.ys (limited to 'tests') diff --git a/tests/various/shregmap.v b/tests/various/shregmap.v new file mode 100644 index 000000000..56e05c2c0 --- /dev/null +++ b/tests/various/shregmap.v @@ -0,0 +1,22 @@ +module shregmap_test(input i, clk, output [1:0] q); +reg head = 1'b0; +reg [3:0] shift1 = 4'b0000; +reg [3:0] shift2 = 4'b0000; + +always @(posedge clk) begin + head <= i; + shift1 <= {shift1[2:0], head}; + shift2 <= {shift2[2:0], head}; +end + +assign q = {shift2[3], shift1[3]}; +endmodule + +module $__SHREG_DFF_P_(input C, D, output Q); +parameter DEPTH = 1; +parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}}; +reg [DEPTH-1:0] r = INIT; +always @(posedge C) + r <= { r[DEPTH-2:0], D }; +assign Q = r[DEPTH-1]; +endmodule diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys new file mode 100644 index 000000000..ca7f47015 --- /dev/null +++ b/tests/various/shregmap.ys @@ -0,0 +1,31 @@ +read_verilog shregmap.v +design -copy-to model $__SHREG_DFF_P_ +hierarchy -top shregmap_test +prep +design -save gold + +techmap +shregmap -init + +opt + +stat +# show -width +select -assert-count 1 t:$_DFF_P_ +select -assert-count 2 t:$__SHREG_DFF_P_ + +design -stash gate + +design -import gold -as gold +design -import gate -as gate +design -copy-from model -as $__SHREG_DFF_P_ \$__SHREG_DFF_P_ +prep + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports -seq 5 miter + +design -load gold +stat + +design -load gate +stat -- cgit v1.2.3 From 45c2a5f87694a83e0cf96477ede02567a93b32a8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 12 Jun 2019 08:34:06 -0700 Subject: Add shregmap -tech xilinx test --- tests/various/shregmap.v | 28 +++++++++++++++++++++++++++- tests/various/shregmap.ys | 37 ++++++++++++++++++++++++++++++++++++- 2 files changed, 63 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/various/shregmap.v b/tests/various/shregmap.v index 56e05c2c0..604c2c976 100644 --- a/tests/various/shregmap.v +++ b/tests/various/shregmap.v @@ -1,4 +1,4 @@ -module shregmap_test(input i, clk, output [1:0] q); +module shregmap_static_test(input i, clk, output [1:0] q); reg head = 1'b0; reg [3:0] shift1 = 4'b0000; reg [3:0] shift2 = 4'b0000; @@ -20,3 +20,29 @@ always @(posedge C) r <= { r[DEPTH-2:0], D }; assign Q = r[DEPTH-1]; endmodule + +module shregmap_variable_test(input i, clk, input [1:0] l1, l2, output [1:0] q); +reg head = 1'b0; +reg [3:0] shift1 = 4'b0000; +reg [3:0] shift2 = 4'b0000; + +always @(posedge clk) begin + head <= i; + shift1 <= {shift1[2:0], head}; + shift2 <= {shift2[2:0], head}; +end + +assign q = {shift2[l2], shift1[l1]}; +endmodule + +module $__XILINX_SHREG_(input C, D, input [1:0] L, output Q); +parameter CLKPOL = 1; +parameter ENPOL = 1; +parameter DEPTH = 1; +parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}}; +reg [DEPTH-1:0] r = INIT; +wire clk = C ^ CLKPOL; +always @(posedge C) + r <= { r[DEPTH-2:0], D }; +assign Q = r[L]; +endmodule diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys index ca7f47015..d644a88aa 100644 --- a/tests/various/shregmap.ys +++ b/tests/various/shregmap.ys @@ -1,6 +1,8 @@ read_verilog shregmap.v +design -save read + design -copy-to model $__SHREG_DFF_P_ -hierarchy -top shregmap_test +hierarchy -top shregmap_static_test prep design -save gold @@ -29,3 +31,36 @@ stat design -load gate stat + +########## + +design -load read +design -copy-to model $__XILINX_SHREG_ +hierarchy -top shregmap_variable_test +prep +design -save gold + +simplemap t:$dff t:$dffe +shregmap -tech xilinx + +stat +# show -width +write_verilog -noexpr -norename +select -assert-count 1 t:$_DFF_P_ +select -assert-count 2 t:$__XILINX_SHREG_ + +design -stash gate + +design -import gold -as gold +design -import gate -as gate +design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_ +prep + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports -seq 5 miter + +design -load gold +stat + +design -load gate +stat -- cgit v1.2.3 From 86efe9a616b70ffa64bb344d83aa42956e5fd470 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 12 Jun 2019 09:01:15 -0700 Subject: Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux" This reverts commit 2223ca91b0cc559bb876e8e97372a8f77da1603e, reversing changes made to eaee250a6e63e58dfef63fa30c4120db78223e24. --- tests/various/muxpack.v | 26 -------------------------- tests/various/muxpack.ys | 15 --------------- 2 files changed, 41 deletions(-) (limited to 'tests') diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index f1bd5ea8e..7c189fff8 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -110,29 +110,3 @@ always @* begin endcase end endmodule - -module mux_if_bal_8_2 #(parameter N=8, parameter W=2) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); -always @* - if (s[0] == 1'b0) - if (s[1] == 1'b0) - if (s[2] == 1'b0) - o <= i[0*W+:W]; - else - o <= i[1*W+:W]; - else - if (s[2] == 1'b0) - o <= i[2*W+:W]; - else - o <= i[3*W+:W]; - else - if (s[1] == 1'b0) - if (s[2] == 1'b0) - o <= i[4*W+:W]; - else - o <= i[5*W+:W]; - else - if (s[2] == 1'b0) - o <= i[6*W+:W]; - else - o <= i[7*W+:W]; -endmodule diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index 9ea743b9f..0c5b82818 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -133,18 +133,3 @@ design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter - -design -load read -hierarchy -top mux_if_bal_8_2 -prep -design -save gold -muxpack -opt -stat -select -assert-count 7 t:$mux -select -assert-count 0 t:$pmux -design -stash gate -design -import gold -as gold -design -import gate -as gate -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter -- cgit v1.2.3 From 2cbcd6224c0293a3abdf00f51c515fc556d9d3e1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 12 Jun 2019 09:05:02 -0700 Subject: Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux" This reverts commit a138381ac3f2c820d187f08531ffd823d6cbcfd5, reversing changes made to b77c5da76919f7f99f171a0a2775896fbc8debc2. --- tests/various/shregmap.v | 22 ---------------------- tests/various/shregmap.ys | 31 ------------------------------- 2 files changed, 53 deletions(-) delete mode 100644 tests/various/shregmap.v delete mode 100644 tests/various/shregmap.ys (limited to 'tests') diff --git a/tests/various/shregmap.v b/tests/various/shregmap.v deleted file mode 100644 index 56e05c2c0..000000000 --- a/tests/various/shregmap.v +++ /dev/null @@ -1,22 +0,0 @@ -module shregmap_test(input i, clk, output [1:0] q); -reg head = 1'b0; -reg [3:0] shift1 = 4'b0000; -reg [3:0] shift2 = 4'b0000; - -always @(posedge clk) begin - head <= i; - shift1 <= {shift1[2:0], head}; - shift2 <= {shift2[2:0], head}; -end - -assign q = {shift2[3], shift1[3]}; -endmodule - -module $__SHREG_DFF_P_(input C, D, output Q); -parameter DEPTH = 1; -parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}}; -reg [DEPTH-1:0] r = INIT; -always @(posedge C) - r <= { r[DEPTH-2:0], D }; -assign Q = r[DEPTH-1]; -endmodule diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys deleted file mode 100644 index ca7f47015..000000000 --- a/tests/various/shregmap.ys +++ /dev/null @@ -1,31 +0,0 @@ -read_verilog shregmap.v -design -copy-to model $__SHREG_DFF_P_ -hierarchy -top shregmap_test -prep -design -save gold - -techmap -shregmap -init - -opt - -stat -# show -width -select -assert-count 1 t:$_DFF_P_ -select -assert-count 2 t:$__SHREG_DFF_P_ - -design -stash gate - -design -import gold -as gold -design -import gate -as gate -design -copy-from model -as $__SHREG_DFF_P_ \$__SHREG_DFF_P_ -prep - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports -seq 5 miter - -design -load gold -stat - -design -load gate -stat -- cgit v1.2.3 From 2e7b3eee400a4d845398be8e15ca023672f05270 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 12 Jun 2019 15:43:43 -0700 Subject: Add a couple more tests --- tests/simple_abc9/abc9.v | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'tests') diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 2752ff8cc..0b83c34a3 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -250,3 +250,15 @@ module abc9_test023 #( wire [2*M-1:0] mask = {M{1'b1}}; assign dout = (mask << din[N-1:0]) >> M; endmodule + +module abc9_test024(input [3:0] i, output [3:0] o); +abc9_test024_sub a(i[1:0], o[1:0]); +endmodule + +module abc9_test024_sub(input [1:0] i, output [1:0] o); +assign o = i; +endmodule + +module abc9_test025(input [3:0] i, output [3:0] o); +abc9_test024_sub a(i[2:1], o[2:1]); +endmodule -- cgit v1.2.3 From 9f275c1437cb48c28b717f0996edab9da9e73aa0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 12 Jun 2019 16:33:05 -0700 Subject: Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux" This reverts commit 2223ca91b0cc559bb876e8e97372a8f77da1603e, reversing changes made to eaee250a6e63e58dfef63fa30c4120db78223e24. --- tests/various/muxpack.v | 112 --------------------------------------- tests/various/muxpack.ys | 135 ----------------------------------------------- 2 files changed, 247 deletions(-) delete mode 100644 tests/various/muxpack.v delete mode 100644 tests/various/muxpack.ys (limited to 'tests') diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v deleted file mode 100644 index 7c189fff8..000000000 --- a/tests/various/muxpack.v +++ /dev/null @@ -1,112 +0,0 @@ -module mux_if_unbal_4_1 #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); -always @* - if (s == 0) o <= i[0*W+:W]; - else if (s == 1) o <= i[1*W+:W]; - else if (s == 2) o <= i[2*W+:W]; - else if (s == 3) o <= i[3*W+:W]; - else o <= {W{1'bx}}; -endmodule - -module mux_if_unbal_5_3 #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); -always @* begin - o <= {W{1'bx}}; - if (s == 0) o <= i[0*W+:W]; - if (s == 1) o <= i[1*W+:W]; - if (s == 2) o <= i[2*W+:W]; - if (s == 3) o <= i[3*W+:W]; - if (s == 4) o <= i[4*W+:W]; -end -endmodule - -module mux_if_unbal_5_3_invert #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); -always @* - if (s != 0) - if (s != 1) - if (s != 2) - if (s != 3) - if (s != 4) o <= i[4*W+:W]; - else o <= i[0*W+:W]; - else o <= i[3*W+:W]; - else o <= i[2*W+:W]; - else o <= i[1*W+:W]; - else o <= {W{1'bx}}; -endmodule - -module mux_if_unbal_5_3_width_mismatch #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); -always @* begin - o <= {W{1'bx}}; - if (s == 0) o <= i[0*W+:W]; - if (s == 1) o <= i[1*W+:W]; - if (s == 2) o[W-2:0] <= i[2*W+:W-1]; - if (s == 3) o <= i[3*W+:W]; - if (s == 4) o <= i[4*W+:W]; -end -endmodule - -module mux_if_unbal_4_1_missing #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); -always @* begin - if (s == 0) o <= i[0*W+:W]; -// else if (s == 1) o <= i[1*W+:W]; -// else if (s == 2) o <= i[2*W+:W]; - else if (s == 3) o <= i[3*W+:W]; - else o <= {W{1'bx}}; -end -endmodule - -module mux_if_unbal_5_3_order #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); -always @* begin - o <= {W{1'bx}}; - if (s == 3) o <= i[3*W+:W]; - if (s == 2) o <= i[2*W+:W]; - if (s == 1) o <= i[1*W+:W]; - if (s == 4) o <= i[4*W+:W]; - if (s == 0) o <= i[0*W+:W]; -end -endmodule - -module mux_if_unbal_4_1_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); -always @* - if (s == 0) o <= i[0*W+:W]; - else if (s == 1) o <= i[1*W+:W]; - else if (s == 2) o <= i[2*W+:W]; - else if (s == 3) o <= i[3*W+:W]; - else if (s == 0) o <= {W{1'b0}}; - else o <= {W{1'bx}}; -endmodule - -module mux_if_unbal_5_3_nonexcl #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); -always @* begin - o <= {W{1'bx}}; - if (s == 0) o <= i[0*W+:W]; - if (s == 1) o <= i[1*W+:W]; - if (s == 2) o <= i[2*W+:W]; - if (s == 3) o <= i[3*W+:W]; - if (s == 4) o <= i[4*W+:W]; - if (s == 0) o <= i[2*W+:W]; -end -endmodule - -module mux_case_unbal_8_7#(parameter N=8, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); -always @* begin - o <= {W{1'bx}}; - case (s) - 0: o <= i[0*W+:W]; - default: - case (s) - 1: o <= i[1*W+:W]; - 2: o <= i[2*W+:W]; - default: - case (s) - 3: o <= i[3*W+:W]; - 4: o <= i[4*W+:W]; - 5: o <= i[5*W+:W]; - default: - case (s) - 6: o <= i[6*W+:W]; - default: o <= i[7*W+:W]; - endcase - endcase - endcase - endcase -end -endmodule diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys deleted file mode 100644 index 0c5b82818..000000000 --- a/tests/various/muxpack.ys +++ /dev/null @@ -1,135 +0,0 @@ -read_verilog muxpack.v -design -save read -hierarchy -top mux_if_unbal_4_1 -prep -design -save gold -muxpack -opt -stat -select -assert-count 0 t:$mux -select -assert-count 1 t:$pmux -design -stash gate -design -import gold -as gold -design -import gate -as gate -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter - -design -load read -hierarchy -top mux_if_unbal_5_3 -prep -design -save gold -muxpack -opt -stat -select -assert-count 0 t:$mux -select -assert-count 1 t:$pmux -design -stash gate -design -import gold -as gold -design -import gate -as gate -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter - -design -load read -hierarchy -top mux_if_unbal_5_3_invert -prep -design -save gold -muxpack -opt -stat -select -assert-count 0 t:$mux -select -assert-count 1 t:$pmux -design -stash gate -design -import gold -as gold -design -import gate -as gate -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter - -design -load read -hierarchy -top mux_if_unbal_5_3_width_mismatch -prep -design -save gold -muxpack -opt -stat -select -assert-count 0 t:$mux -select -assert-count 2 t:$pmux -design -stash gate -design -import gold -as gold -design -import gate -as gate -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter - -design -load read -hierarchy -top mux_if_unbal_4_1_missing -prep -design -save gold -muxpack -opt -stat -select -assert-count 0 t:$mux -select -assert-count 1 t:$pmux -design -stash gate -design -import gold -as gold -design -import gate -as gate -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter - -design -load read -hierarchy -top mux_if_unbal_5_3_order -prep -design -save gold -muxpack -opt -stat -select -assert-count 0 t:$mux -select -assert-count 1 t:$pmux -design -stash gate -design -import gold -as gold -design -import gate -as gate -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter - -design -load read -hierarchy -top mux_if_unbal_4_1_nonexcl -prep -design -save gold -muxpack -opt -stat -select -assert-count 0 t:$mux -select -assert-count 1 t:$pmux -design -stash gate -design -import gold -as gold -design -import gate -as gate -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter - -design -load read -hierarchy -top mux_if_unbal_5_3_nonexcl -prep -design -save gold -muxpack -opt -stat -select -assert-count 0 t:$mux -select -assert-count 1 t:$pmux -design -stash gate -design -import gold -as gold -design -import gate -as gate -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter - -design -load read -hierarchy -top mux_case_unbal_8_7 -prep -design -save gold -muxpack -opt -stat -select -assert-count 0 t:$mux -select -assert-count 1 t:$pmux -design -stash gate -design -import gold -as gold -design -import gate -as gate -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter -- cgit v1.2.3 From fa5fc3f6afd9eb27c1f52244b60cbeb77aa2e26c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 19 Jun 2019 12:12:08 +0200 Subject: Add defvalue test, minor autotest fixes for .sv files Signed-off-by: Clifford Wolf --- tests/simple/defvalue.sv | 22 ++++++++++++++++++++++ tests/tools/autotest.sh | 29 +++++++++++++++-------------- 2 files changed, 37 insertions(+), 14 deletions(-) create mode 100644 tests/simple/defvalue.sv (limited to 'tests') diff --git a/tests/simple/defvalue.sv b/tests/simple/defvalue.sv new file mode 100644 index 000000000..b0a087ecb --- /dev/null +++ b/tests/simple/defvalue.sv @@ -0,0 +1,22 @@ +module top(input clock, input [3:0] delta, output [3:0] cnt1, cnt2); + cnt #(1) foo (.clock, .cnt(cnt1), .delta); + cnt #(2) bar (.clock, .cnt(cnt2)); +endmodule + +module cnt #( + parameter integer initval = 0 +) ( + input clock, + output logic [3:0] cnt = initval, +`ifdef __ICARUS__ + input [3:0] delta +`else + input [3:0] delta = 10 +`endif +); +`ifdef __ICARUS__ + assign (weak0, weak1) delta = 10; +`endif + always @(posedge clock) + cnt <= cnt + delta; +endmodule diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index 23964a751..96d9cdda9 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -89,8 +89,7 @@ done compile_and_run() { exe="$1"; output="$2"; shift 2 - ext=${1##*.} - if [ "$ext" == "sv" ]; then + if [ "${2##*.}" == "sv" ]; then language_gen="-g2012" else language_gen="-g2005" @@ -142,23 +141,25 @@ do cd ${bn}.out fn=$(basename $fn) bn=$(basename $bn) + refext=v rm -f ${bn}_ref.fir if [[ "$ext" == "v" ]]; then egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext} elif [[ "$ext" == "aig" ]] || [[ "$ext" == "aag" ]]; then - "$toolsdir"/../../yosys-abc -c "read_aiger ../${fn}; write ${bn}_ref.v" + "$toolsdir"/../../yosys-abc -c "read_aiger ../${fn}; write ${bn}_ref.${refext}" else - cp ../${fn} ${bn}_ref.${ext} + refext=$ext + cp ../${fn} ${bn}_ref.${refext} fi if [ ! -f ../${bn}_tb.v ]; then - "$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.v + "$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.${refext} else cp ../${bn}_tb.v ${bn}_tb.v fi if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi - compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs \ + compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.${refext} $libs \ "$toolsdir"/../../techlibs/common/simlib.v \ "$toolsdir"/../../techlibs/common/simcells.v if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi @@ -175,25 +176,25 @@ do test_count=$(( test_count + 1 )) } - if [ "$frontend" = "verific" -o "$frontend" = "verific_gates" ] && grep -q VERIFIC-SKIP ${bn}_ref.v; then + if [ "$frontend" = "verific" -o "$frontend" = "verific_gates" ] && grep -q VERIFIC-SKIP ${bn}_ref.${refext}; then touch ../${bn}.skip return fi if [ -n "$scriptfiles" ]; then - test_passes -f "$frontend $include_opts" ${bn}_ref.v $scriptfiles + test_passes -f "$frontend $include_opts" ${bn}_ref.${refext} $scriptfiles elif [ -n "$scriptopt" ]; then - test_passes -f "$frontend $include_opts" -p "$scriptopt" ${bn}_ref.v + test_passes -f "$frontend $include_opts" -p "$scriptopt" ${bn}_ref.${refext} elif [ "$frontend" = "verific" ]; then - test_passes -p "verific -vlog2k ${bn}_ref.v; verific -import -all; opt; memory;;" + test_passes -p "verific -vlog2k ${bn}_ref.${refext}; verific -import -all; opt; memory;;" elif [ "$frontend" = "verific_gates" ]; then - test_passes -p "verific -vlog2k ${bn}_ref.v; verific -import -gates -all; opt; memory;;" + test_passes -p "verific -vlog2k ${bn}_ref.${refext}; verific -import -gates -all; opt; memory;;" else - test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.v - test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.v + test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.${refext} + test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.${refext} if [ -n "$firrtl2verilog" ]; then if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then - "$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt; memory; opt; fsm; opt -full -fine; pmuxtree" ${bn}_ref.v + "$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt; memory; opt; fsm; opt -full -fine; pmuxtree" ${bn}_ref.${refext} $firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.fir.v fi -- cgit v1.2.3 From c330379870a48209534807d1c021ce2a20ccf880 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 19 Jun 2019 12:20:35 +0200 Subject: Make tests/aiger less chatty Signed-off-by: Clifford Wolf --- tests/aiger/run-test.sh | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'tests') diff --git a/tests/aiger/run-test.sh b/tests/aiger/run-test.sh index f52eb4ac1..5246c1b48 100755 --- a/tests/aiger/run-test.sh +++ b/tests/aiger/run-test.sh @@ -10,8 +10,9 @@ for aag in *.aag; do # Since ABC cannot read *.aag, read the *.aig instead # (which would have been created by the reference aig2aig utility, # available from http://fmv.jku.at/aiger/) - ../../yosys-abc -c "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v" - ../../yosys -p " + echo "Checking $aag." + ../../yosys-abc -q "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v" + ../../yosys -qp " read_verilog ${aag%.*}_ref.v prep design -stash gold @@ -26,8 +27,9 @@ sat -verify -prove-asserts -show-ports -seq 16 miter done for aig in *.aig; do - ../../yosys-abc -c "read -c $aig; write ${aig%.*}_ref.v" - ../../yosys -p " + echo "Checking $aig." + ../../yosys-abc -q "read -c $aig; write ${aig%.*}_ref.v" + ../../yosys -qp " read_verilog ${aig%.*}_ref.v prep design -stash gold -- cgit v1.2.3 From 8b8af10f5e612eb1a39320e20b2d1d6f1e7d45df Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tobias=20W=C3=B6lfel?= Date: Wed, 19 Jun 2019 12:47:48 +0200 Subject: Unpacked array declaration using size Allows fixed-sized array dimension specified by a single number. This commit is based on the work from PeterCrozier https://github.com/YosysHQ/yosys/pull/560. But is split out of the original work. --- tests/various/unpacked_arrays.sv | 4 ++++ tests/various/unpacked_arrays.ys | 2 ++ 2 files changed, 6 insertions(+) create mode 100644 tests/various/unpacked_arrays.sv create mode 100644 tests/various/unpacked_arrays.ys (limited to 'tests') diff --git a/tests/various/unpacked_arrays.sv b/tests/various/unpacked_arrays.sv new file mode 100644 index 000000000..2f4ed0d3f --- /dev/null +++ b/tests/various/unpacked_arrays.sv @@ -0,0 +1,4 @@ +module unpacked_arrays; + reg array_range [0:7]; + reg array_size [8]; +endmodule diff --git a/tests/various/unpacked_arrays.ys b/tests/various/unpacked_arrays.ys new file mode 100644 index 000000000..419152d9c --- /dev/null +++ b/tests/various/unpacked_arrays.ys @@ -0,0 +1,2 @@ +read_verilog -sv unpacked_arrays.sv +stat -- cgit v1.2.3 From 6a6dd5e0575950174e3abde7a13a3e3be73e5299 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 20 Jun 2019 12:06:07 +0200 Subject: Add proper test for SV-style arrays Signed-off-by: Clifford Wolf --- tests/simple/arrays02.sv | 16 ++++++++++++++++ tests/various/unpacked_arrays.sv | 4 ---- tests/various/unpacked_arrays.ys | 2 -- 3 files changed, 16 insertions(+), 6 deletions(-) create mode 100644 tests/simple/arrays02.sv delete mode 100644 tests/various/unpacked_arrays.sv delete mode 100644 tests/various/unpacked_arrays.ys (limited to 'tests') diff --git a/tests/simple/arrays02.sv b/tests/simple/arrays02.sv new file mode 100644 index 000000000..76c2a7388 --- /dev/null +++ b/tests/simple/arrays02.sv @@ -0,0 +1,16 @@ +module uut_arrays02(clock, we, addr, wr_data, rd_data); + +input clock, we; +input [3:0] addr, wr_data; +output [3:0] rd_data; +reg [3:0] rd_data; + +reg [3:0] memory [16]; + +always @(posedge clock) begin + if (we) + memory[addr] <= wr_data; + rd_data <= memory[addr]; +end + +endmodule diff --git a/tests/various/unpacked_arrays.sv b/tests/various/unpacked_arrays.sv deleted file mode 100644 index 2f4ed0d3f..000000000 --- a/tests/various/unpacked_arrays.sv +++ /dev/null @@ -1,4 +0,0 @@ -module unpacked_arrays; - reg array_range [0:7]; - reg array_size [8]; -endmodule diff --git a/tests/various/unpacked_arrays.ys b/tests/various/unpacked_arrays.ys deleted file mode 100644 index 419152d9c..000000000 --- a/tests/various/unpacked_arrays.ys +++ /dev/null @@ -1,2 +0,0 @@ -read_verilog -sv unpacked_arrays.sv -stat -- cgit v1.2.3 From 2454ad99bf49afe752d6fd1c1567f59ee9e26736 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 20 Jun 2019 13:44:21 +0200 Subject: Refactor "opt_rmdff -sat" Signed-off-by: Clifford Wolf --- tests/opt/opt_ff_sat.v | 25 +++++++++++-------------- tests/opt/opt_ff_sat.ys | 1 + 2 files changed, 12 insertions(+), 14 deletions(-) (limited to 'tests') diff --git a/tests/opt/opt_ff_sat.v b/tests/opt/opt_ff_sat.v index fc1e61980..5a0a6fe37 100644 --- a/tests/opt/opt_ff_sat.v +++ b/tests/opt/opt_ff_sat.v @@ -1,15 +1,12 @@ -module top( - input clk, - input a, - output b - ); - reg b_reg; - initial begin - b_reg <= 0; - end - - assign b = b_reg; - always @(posedge clk) begin - b_reg <= a && b_reg; - end +module top ( + input clk, + output reg [7:0] cnt +); + initial cnt = 0; + always @(posedge clk) begin + if (cnt < 20) + cnt <= cnt + 1; + else + cnt <= 0; + end endmodule diff --git a/tests/opt/opt_ff_sat.ys b/tests/opt/opt_ff_sat.ys index 13e4ad29b..4e7cc6ca4 100644 --- a/tests/opt/opt_ff_sat.ys +++ b/tests/opt/opt_ff_sat.ys @@ -2,3 +2,4 @@ read_verilog opt_ff_sat.v prep -flatten opt_rmdff -sat synth +select -assert-count 5 t:$_DFF_P_ -- cgit v1.2.3 From a8c85d1b4b810e2ea31770e37e1414b7f1a15283 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 20 Jun 2019 14:27:57 +0200 Subject: Update some .gitignore files Signed-off-by: Clifford Wolf --- tests/aiger/.gitignore | 3 +-- tests/various/.gitignore | 3 ++- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'tests') diff --git a/tests/aiger/.gitignore b/tests/aiger/.gitignore index 073f46157..9a26bb8f4 100644 --- a/tests/aiger/.gitignore +++ b/tests/aiger/.gitignore @@ -1,2 +1 @@ -*.log -*.out +/*_ref.v diff --git a/tests/various/.gitignore b/tests/various/.gitignore index 397b4a762..7b3e8c68e 100644 --- a/tests/various/.gitignore +++ b/tests/various/.gitignore @@ -1 +1,2 @@ -*.log +/*.log +/*.out -- cgit v1.2.3 From b98276fa61be7a1c589d6dac661d31982cfab16b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 20 Jun 2019 10:10:43 -0700 Subject: Add test --- tests/various/signext.ys | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 tests/various/signext.ys (limited to 'tests') diff --git a/tests/various/signext.ys b/tests/various/signext.ys new file mode 100644 index 000000000..26dab13a6 --- /dev/null +++ b/tests/various/signext.ys @@ -0,0 +1,24 @@ + +read_verilog -formal < Date: Thu, 20 Jun 2019 10:15:04 -0700 Subject: Remove leftover comment --- tests/various/signext.ys | 3 --- 1 file changed, 3 deletions(-) (limited to 'tests') diff --git a/tests/various/signext.ys b/tests/various/signext.ys index 26dab13a6..ae44a0e06 100644 --- a/tests/various/signext.ys +++ b/tests/various/signext.ys @@ -5,9 +5,6 @@ assign o = 1'bx; endmodule EOT - -## Example usage for "pmuxtree" and "muxcover" - proc ## Equivalence checking -- cgit v1.2.3 From d0bbf9e4d4a508179b55a0cc7793d984f3318f7c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 20 Jun 2019 12:43:59 -0700 Subject: Extend sign extension tests --- tests/various/signext.ys | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) (limited to 'tests') diff --git a/tests/various/signext.ys b/tests/various/signext.ys index ae44a0e06..0c8d671e7 100644 --- a/tests/various/signext.ys +++ b/tests/various/signext.ys @@ -1,7 +1,13 @@ read_verilog -formal < Date: Thu, 20 Jun 2019 16:07:22 -0700 Subject: Add test --- tests/simple/generate.v | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'tests') diff --git a/tests/simple/generate.v b/tests/simple/generate.v index 3c55682cb..0e353ad9b 100644 --- a/tests/simple/generate.v +++ b/tests/simple/generate.v @@ -148,3 +148,14 @@ generate endgenerate assign out = steps[WIDTH].outer[0].val; endmodule + +// ------------------------------------------ + +module gen_test6(output [3:0] o); +generate + genvar i; + for (i = 3; i >= 0; i = i-1) begin + assign o[i] = 1'b0; + end +endgenerate +endmodule -- cgit v1.2.3 From 014606affe3f1753ac16d2afd684967d72d83746 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 20 Jun 2019 17:29:45 -0700 Subject: Fix issue with part of PI being 1'bx --- tests/simple_abc9/abc9.v | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'tests') diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 0b83c34a3..64b625efe 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -262,3 +262,8 @@ endmodule module abc9_test025(input [3:0] i, output [3:0] o); abc9_test024_sub a(i[2:1], o[2:1]); endmodule + +module abc9_test026(output [3:0] o, p); +assign o = { 1'b1, 1'bx }; +assign p = { 1'b1, 1'bx, 1'b0 }; +endmodule -- cgit v1.2.3 From 75375a3fbce622b5c4cb6f4464379bb0e66a1107 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 19 Jun 2019 10:07:34 -0700 Subject: Add test --- tests/various/muxcover.ys | 137 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 136 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/various/muxcover.ys b/tests/various/muxcover.ys index 7ac460f13..d55a35b8c 100644 --- a/tests/various/muxcover.ys +++ b/tests/various/muxcover.ys @@ -13,7 +13,7 @@ read_verilog -formal < Date: Wed, 19 Jun 2019 10:15:41 -0700 Subject: Missing a `clean` and `opt_expr -mux_bool` in test --- tests/various/muxcover.ys | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'tests') diff --git a/tests/various/muxcover.ys b/tests/various/muxcover.ys index d55a35b8c..8ef619b46 100644 --- a/tests/various/muxcover.ys +++ b/tests/various/muxcover.ys @@ -115,6 +115,8 @@ design -save gold techmap muxcover -mux4=150 -mux8=200 +clean +opt_expr -mux_bool select -assert-count 0 t:$_MUX_ select -assert-count 0 t:$_MUX4_ select -assert-count 1 t:$_MUX8_ @@ -171,6 +173,8 @@ design -save gold techmap muxcover -mux4=150 -mux8=200 -mux16=250 +clean +opt_expr -mux_bool select -assert-count 0 t:$_MUX_ select -assert-count 0 t:$_MUX4_ select -assert-count 0 t:$_MUX8_ -- cgit v1.2.3 From 6ec816098153c733b97410ebc6aef166db8affd8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 21 Jun 2019 11:45:53 -0700 Subject: Add more muxpack tests, with overlapping entries --- tests/various/muxpack.v | 55 +++++++++++++++++++++++++++++++++++++++++++++++- tests/various/muxpack.ys | 30 ++++++++++++++++++++++++++ 2 files changed, 84 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index 3a1086dbf..7a658d754 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -187,7 +187,9 @@ module case_nonexclusive_select ( ); always @* begin case (x) - 0, 2: o = b; + //0, 2: o = b; + 0: o = b; + 2: o = b; 1: o = c; default: begin o = a; @@ -197,3 +199,54 @@ module case_nonexclusive_select ( endcase end endmodule + +module case_nonoverlap ( + input wire [2:0] x, + input wire a, b, c, d, e, f, g, + output reg o +); + always @* begin + case (x) + //0, 2: o = b; // Creates $reduce_or + //0: o = b; 2: o = b; // Creates $reduce_or + 0: o = b; + 2: o = f; + 1: o = c; + default: + case (x) + //3, 4: o = d; // Creates $reduce_or + //3: o = d; 4: o = d; // Creates $reduce_or + 3: o = d; + 4: o = g; + 5: o = e; + default: o = 1'b0; + endcase + endcase + end +endmodule + +module case_overlap ( + input wire [2:0] x, + input wire a, b, c, d, e, f, g, + output reg o +); + always @* begin + case (x) + //0, 2: o = b; // Creates $reduce_or + //0: o = b; 2: o = b; // Creates $reduce_or + 0: o = b; + 2: o = f; + 1: o = c; + default: + case (x) + //3, 4: o = d; // Creates $reduce_or + //3: o = d; 4: o = d; // Creates $reduce_or + 2: o = 1'b1; // Overlaps with previous $pmux + 3: o = d; + 4: o = g; + 5: o = e; + default: o = 1'b0; + endcase + endcase + end +endmodule diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index 579dad8d3..ef8a6dab9 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -212,3 +212,33 @@ design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top case_nonoverlap +prep +design -save gold +muxpack +opt +stat +select -assert-count 0 t:$mux +select -assert-count 1 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top case_overlap +prep +design -save gold +muxpack +#opt # Do not opt otherwise $pmux's overlapping entry will get removed +stat +select -assert-count 0 t:$mux +select -assert-count 1 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter -- cgit v1.2.3 From ae8305ffcc0c812488163bcc35365d473ce1345d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 21 Jun 2019 12:13:00 -0700 Subject: Fix testcase --- tests/various/muxpack.ys | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'tests') diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index ef8a6dab9..de5eec87f 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -230,13 +230,14 @@ sat -verify -prove-asserts -show-ports miter design -load read hierarchy -top case_overlap -prep +#prep # Do not prep otherwise $pmux's overlapping entry will get removed +proc design -save gold muxpack -#opt # Do not opt otherwise $pmux's overlapping entry will get removed +opt stat select -assert-count 0 t:$mux -select -assert-count 1 t:$pmux +select -assert-count 2 t:$pmux design -stash gate design -import gold -as gold design -import gate -as gate -- cgit v1.2.3 From 32f637ffdb0c0641b51227fad92bc80e284740d2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 21 Jun 2019 12:31:04 -0700 Subject: Add more tests --- tests/various/muxpack.v | 47 +++++++++++++++++++++++++++-------------------- tests/various/muxpack.ys | 25 ++++++++++++++++++++++++- 2 files changed, 51 insertions(+), 21 deletions(-) (limited to 'tests') diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index 7a658d754..33ece1f16 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -187,7 +187,6 @@ module case_nonexclusive_select ( ); always @* begin case (x) - //0, 2: o = b; 0: o = b; 2: o = b; 1: o = c; @@ -202,22 +201,16 @@ endmodule module case_nonoverlap ( input wire [2:0] x, - input wire a, b, c, d, e, f, g, + input wire a, b, c, d, e, output reg o ); always @* begin case (x) - //0, 2: o = b; // Creates $reduce_or - //0: o = b; 2: o = b; // Creates $reduce_or - 0: o = b; - 2: o = f; + 0, 2: o = b; // Creates $reduce_or 1: o = c; default: case (x) - //3, 4: o = d; // Creates $reduce_or - //3: o = d; 4: o = d; // Creates $reduce_or - 3: o = d; - 4: o = g; + 3: o = d; 4: o = d; // Creates $reduce_or 5: o = e; default: o = 1'b0; endcase @@ -227,23 +220,37 @@ endmodule module case_overlap ( input wire [2:0] x, - input wire a, b, c, d, e, f, g, + input wire a, b, c, d, e, output reg o ); always @* begin case (x) - //0, 2: o = b; // Creates $reduce_or - //0: o = b; 2: o = b; // Creates $reduce_or - 0: o = b; - 2: o = f; + 0, 2: o = b; // Creates $reduce_or + 1: o = c; + default: + case (x) + 0: o = 1'b1; // OVERLAP! + 3, 4: o = d; // Creates $reduce_or + 5: o = e; + default: o = 1'b0; + endcase + endcase + end +endmodule + +module case_overlap2 ( + input wire [2:0] x, + input wire a, b, c, d, e, + output reg o +); + always @* begin + case (x) + 0: o = b; 2: o = b; // Creates $reduce_or 1: o = c; default: case (x) - //3, 4: o = d; // Creates $reduce_or - //3: o = d; 4: o = d; // Creates $reduce_or - 2: o = 1'b1; // Overlaps with previous $pmux - 3: o = d; - 4: o = g; + 0: o = d; 2: o = d; // Creates $reduce_or + 3: o = d; 4: o = d; // Creates $reduce_or 5: o = e; default: o = 1'b0; endcase diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index de5eec87f..af23fcec8 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -215,8 +215,11 @@ sat -verify -prove-asserts -show-ports miter design -load read hierarchy -top case_nonoverlap -prep +#prep # Do not prep otherwise $pmux's overlapping entry will get removed +proc design -save gold +opt -fast -mux_undef +select -assert-count 2 t:$pmux muxpack opt stat @@ -233,6 +236,26 @@ hierarchy -top case_overlap #prep # Do not prep otherwise $pmux's overlapping entry will get removed proc design -save gold +opt -fast -mux_undef +select -assert-count 2 t:$pmux +muxpack +opt +stat +select -assert-count 0 t:$mux +select -assert-count 2 t:$pmux +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + +design -load read +hierarchy -top case_overlap2 +#prep # Do not prep otherwise $pmux's overlapping entry will get removed +proc +design -save gold +opt -fast -mux_undef +select -assert-count 2 t:$pmux muxpack opt stat -- cgit v1.2.3 From a701a2accf36abb6d0d1a90dc1811eb15708d5db Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 24 Jun 2019 18:32:58 -0700 Subject: Add test --- tests/memories/issue00710.v | 17 +++++++++++++++++ tests/memories/run-test.sh | 6 +++++- 2 files changed, 22 insertions(+), 1 deletion(-) create mode 100644 tests/memories/issue00710.v (limited to 'tests') diff --git a/tests/memories/issue00710.v b/tests/memories/issue00710.v new file mode 100644 index 000000000..7a5fad1c2 --- /dev/null +++ b/tests/memories/issue00710.v @@ -0,0 +1,17 @@ +// expect-wr-ports 1 +// expect-rd-ports 1 +// expect-rd-clk \clk + +module top(input clk, input we, re, reset, input [7:0] addr, wdata, output reg [7:0] rdata); + +reg [7:0] bram[0:255]; +(* keep *) reg dummy; + +always @(posedge clk) + if (reset) + dummy <= 1'b0; + else if (re) + rdata <= bram[addr]; + else if (we) + bram[addr] <= wdata; +endmodule diff --git a/tests/memories/run-test.sh b/tests/memories/run-test.sh index 734a96682..d0537bb98 100755 --- a/tests/memories/run-test.sh +++ b/tests/memories/run-test.sh @@ -14,7 +14,7 @@ shift "$((OPTIND-1))" bash ../tools/autotest.sh $seed -G *.v -for f in `egrep -l 'expect-(wr|rd)-ports' *.v`; do +for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do echo -n "Testing expectations for $f .." ../../yosys -qp "proc; opt; memory -nomap;; dump -outfile ${f%.v}.dmp t:\$mem" $f if grep -q expect-wr-ports $f; then @@ -25,6 +25,10 @@ for f in `egrep -l 'expect-(wr|rd)-ports' *.v`; do grep -q "parameter \\\\RD_PORTS $(gawk '/expect-rd-ports/ { print $3; }' $f)\$" ${f%.v}.dmp || { echo " ERROR: Unexpected number of read ports."; false; } fi + if grep -q expect-rd-clk $f; then + grep -q "connect \\\\RD_CLK \\$(gawk '/expect-rd-clk/ { print $3; }' $f)\$" ${f%.v}.dmp || + { echo " ERROR: Unexpected read clock."; false; } + fi echo " ok." done -- cgit v1.2.3 From 9dca024a30e5f6cfb06e1abb584ce1320fb81f16 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 24 Jun 2019 21:52:53 -0700 Subject: Add tests/various/abc9.{v,ys} with SCC test --- tests/various/abc9.v | 5 +++++ tests/various/abc9.ys | 14 ++++++++++++++ 2 files changed, 19 insertions(+) create mode 100644 tests/various/abc9.v create mode 100644 tests/various/abc9.ys (limited to 'tests') diff --git a/tests/various/abc9.v b/tests/various/abc9.v new file mode 100644 index 000000000..8271cd249 --- /dev/null +++ b/tests/various/abc9.v @@ -0,0 +1,5 @@ +module abc9_test027(output reg o); +initial o = 1'b0; +always @* + o <= ~o; +endmodule diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys new file mode 100644 index 000000000..922f7005d --- /dev/null +++ b/tests/various/abc9.ys @@ -0,0 +1,14 @@ +read_verilog abc9.v +proc +design -save gold + +abc9 -lut 4 +check +design -stash gate + +design -import gold -as gold +design -import gate -as gate + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + -- cgit v1.2.3 From ab6e8ce0f00bc9fcf38dc62ae9de26405f7b59d7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 25 Jun 2019 08:43:58 -0700 Subject: Add testcase from #335, fixed by #1130 --- tests/memories/issue00335.v | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 tests/memories/issue00335.v (limited to 'tests') diff --git a/tests/memories/issue00335.v b/tests/memories/issue00335.v new file mode 100644 index 000000000..f3b6e5dfe --- /dev/null +++ b/tests/memories/issue00335.v @@ -0,0 +1,28 @@ +// expect-wr-ports 1 +// expect-rd-ports 1 +// expect-rd-clk \clk + +module ram2 (input clk, + input sel, + input we, + input [SIZE-1:0] adr, + input [63:0] dat_i, + output reg [63:0] dat_o); + parameter SIZE = 5; // Address size + + reg [63:0] mem [0:(1 << SIZE)-1]; + integer i; + + initial begin + for (i = 0; i < (1< Date: Wed, 26 Jun 2019 18:17:52 +0100 Subject: tests: Check that Icarus can parse arch sim models Signed-off-by: David Shah --- tests/arch/run-test.sh | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100755 tests/arch/run-test.sh (limited to 'tests') diff --git a/tests/arch/run-test.sh b/tests/arch/run-test.sh new file mode 100755 index 000000000..fc4175be8 --- /dev/null +++ b/tests/arch/run-test.sh @@ -0,0 +1,8 @@ +#!/bin/bash + +set -e + +echo "Running syntax check on arch sim models" +for arch in ../../techlibs/*; do + find $arch -name cells_sim.v -print0 | xargs -0 -n1 -r iverilog -t null -I$arch +done -- cgit v1.2.3 From 3910bc2ea63fa5ed0f3c961126866639058f651d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 27 Jun 2019 06:01:50 -0700 Subject: Copy tests from eddie/fix1132 --- tests/various/muxcover.ys | 320 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 320 insertions(+) (limited to 'tests') diff --git a/tests/various/muxcover.ys b/tests/various/muxcover.ys index 8ef619b46..67e9625e6 100644 --- a/tests/various/muxcover.ys +++ b/tests/various/muxcover.ys @@ -188,3 +188,323 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter +## MUX2 in MUX4 :: https://github.com/YosysHQ/yosys/issues/1132 + +design -reset +read_verilog -formal < Date: Thu, 27 Jun 2019 11:02:52 -0700 Subject: Add #1135 testcase --- tests/various/pmux2shiftx.v | 10 ++++++++++ tests/various/pmux2shiftx.ys | 21 ++++++++++++++++----- 2 files changed, 26 insertions(+), 5 deletions(-) (limited to 'tests') diff --git a/tests/various/pmux2shiftx.v b/tests/various/pmux2shiftx.v index fec84187b..563394080 100644 --- a/tests/various/pmux2shiftx.v +++ b/tests/various/pmux2shiftx.v @@ -32,3 +32,13 @@ module pmux2shiftx_test ( endcase end endmodule + +module issue01135(input [7:0] i, output o); +always @* +case (i[6:3]) + 4: o <= i[0]; + 3: o <= i[2]; + 7: o <= i[3]; + default: o <= 1'b0; +endcase +endmodule diff --git a/tests/various/pmux2shiftx.ys b/tests/various/pmux2shiftx.ys index deb134083..51ee2f7be 100644 --- a/tests/various/pmux2shiftx.ys +++ b/tests/various/pmux2shiftx.ys @@ -1,4 +1,7 @@ read_verilog pmux2shiftx.v +design -save read + +hierarchy -top pmux2shiftx_test prep design -save gold @@ -21,8 +24,16 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter -design -load gold -stat - -design -load gate -stat +#design -load gold +#stat +# +#design -load gate +#stat + +design -load read +hierarchy -top issue01135 +proc +pmux2shiftx -norange +opt -full +select -assert-count 0 t:$shift* +select -assert-count 1 t:$pmux -- cgit v1.2.3 From ab7c4319058bbae8758cda9f246c92c324dfafbf Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 27 Jun 2019 11:13:49 -0700 Subject: Add simcells.v, simlib.v, and some output --- tests/arch/run-test.sh | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/arch/run-test.sh b/tests/arch/run-test.sh index fc4175be8..5292d1615 100755 --- a/tests/arch/run-test.sh +++ b/tests/arch/run-test.sh @@ -4,5 +4,15 @@ set -e echo "Running syntax check on arch sim models" for arch in ../../techlibs/*; do - find $arch -name cells_sim.v -print0 | xargs -0 -n1 -r iverilog -t null -I$arch + find $arch -name cells_sim.v | while read path; do + echo -n "Test $path ->" + iverilog -t null -I$arch $path + echo " ok" + done +done + +for path in "../../techlibs/common/simcells.v" "../../techlibs/common/simlib.v"; do + echo -n "Test $path ->" + iverilog -t null $path + echo " ok" done -- cgit v1.2.3 From 6c256b8cda66e2ba128d5fa3ba344fe4717711f8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 27 Jun 2019 11:20:15 -0700 Subject: Merge origin/master --- tests/various/muxcover.ys | 320 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 320 insertions(+) (limited to 'tests') diff --git a/tests/various/muxcover.ys b/tests/various/muxcover.ys index 8ef619b46..67e9625e6 100644 --- a/tests/various/muxcover.ys +++ b/tests/various/muxcover.ys @@ -188,3 +188,323 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter +## MUX2 in MUX4 :: https://github.com/YosysHQ/yosys/issues/1132 + +design -reset +read_verilog -formal < Date: Thu, 27 Jun 2019 22:54:09 -0400 Subject: tests: use optional ABCEXTERNAL when specified Commits 65924fd1, abc40924, and ebe29b66 hard-code the invocation of yosys-abc, which fails if ABCEXTERNAL was specified during the build. Allow tests to utilize an optional, externally specified abc binary. Signed-off-by: Gabriel Somlo --- tests/aiger/run-test.sh | 14 ++++++++++++-- tests/memories/run-test.sh | 6 ++++-- tests/tools/autotest.sh | 7 +++++-- 3 files changed, 21 insertions(+), 6 deletions(-) (limited to 'tests') diff --git a/tests/aiger/run-test.sh b/tests/aiger/run-test.sh index 5246c1b48..deaf48a3d 100755 --- a/tests/aiger/run-test.sh +++ b/tests/aiger/run-test.sh @@ -2,6 +2,16 @@ set -e +OPTIND=1 +abcprog="../../yosys-abc" # default to built-in version of abc +while getopts "A:" opt +do + case "$opt" in + A) abcprog="$OPTARG" ;; + esac +done +shift "$((OPTIND-1))" + # NB: *.aag and *.aig must contain a symbol table naming the primary # inputs and outputs, otherwise ABC and Yosys will name them # arbitrarily (and inconsistently with each other). @@ -11,7 +21,7 @@ for aag in *.aag; do # (which would have been created by the reference aig2aig utility, # available from http://fmv.jku.at/aiger/) echo "Checking $aag." - ../../yosys-abc -q "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v" + $abcprog -q "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v" ../../yosys -qp " read_verilog ${aag%.*}_ref.v prep @@ -28,7 +38,7 @@ done for aig in *.aig; do echo "Checking $aig." - ../../yosys-abc -q "read -c $aig; write ${aig%.*}_ref.v" + $abcprog -q "read -c $aig; write ${aig%.*}_ref.v" ../../yosys -qp " read_verilog ${aig%.*}_ref.v prep diff --git a/tests/memories/run-test.sh b/tests/memories/run-test.sh index d0537bb98..76acaa9cd 100755 --- a/tests/memories/run-test.sh +++ b/tests/memories/run-test.sh @@ -4,15 +4,17 @@ set -e OPTIND=1 seed="" # default to no seed specified -while getopts "S:" opt +abcopt="" +while getopts "A:S:" opt do case "$opt" in + A) abcopt="-A $OPTARG" ;; S) seed="-S $OPTARG" ;; esac done shift "$((OPTIND-1))" -bash ../tools/autotest.sh $seed -G *.v +bash ../tools/autotest.sh $abcopt $seed -G *.v for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do echo -n "Testing expectations for $f .." diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index 96d9cdda9..7b64b357f 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -23,12 +23,13 @@ warn_iverilog_git=false # The tests are skipped if firrtl2verilog is the empty string (the default). firrtl2verilog="" xfirrtl="../xfirrtl" +abcprog="$toolsdir/../../yosys-abc" if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdata ]; then ( set -ex; ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1 fi -while getopts xmGl:wkjvref:s:p:n:S:I:-: opt; do +while getopts xmGl:wkjvref:s:p:n:S:I:A:-: opt; do case "$opt" in x) use_xsim=true ;; @@ -65,6 +66,8 @@ while getopts xmGl:wkjvref:s:p:n:S:I:-: opt; do include_opts="$include_opts -I $OPTARG" xinclude_opts="$xinclude_opts -i $OPTARG" minclude_opts="$minclude_opts +incdir+$OPTARG" ;; + A) + abcprog="$OPTARG" ;; -) case "${OPTARG}" in xfirrtl) @@ -147,7 +150,7 @@ do if [[ "$ext" == "v" ]]; then egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext} elif [[ "$ext" == "aig" ]] || [[ "$ext" == "aag" ]]; then - "$toolsdir"/../../yosys-abc -c "read_aiger ../${fn}; write ${bn}_ref.${refext}" + $abcprog -c "read_aiger ../${fn}; write ${bn}_ref.${refext}" else refext=$ext cp ../${fn} ${bn}_ref.${refext} -- cgit v1.2.3 From dc677c791de438a493ad5e0101987da29c6a6d0f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 28 Jun 2019 10:12:48 -0700 Subject: Add test from #1144, and try reading without '-specify' flag --- tests/various/specify.v | 14 ++++++++++++++ tests/various/specify.ys | 2 ++ 2 files changed, 16 insertions(+) (limited to 'tests') diff --git a/tests/various/specify.v b/tests/various/specify.v index afc421da8..b1f399267 100644 --- a/tests/various/specify.v +++ b/tests/various/specify.v @@ -28,3 +28,17 @@ module test2 ( (B => Q) = 1.5; endspecify endmodule + +module issue01144(input clk, d, output q); +specify + // Fails: + (posedge clk => (q +: d)) = (3,1); + (/*posedge*/ clk => (q +: d)) = (3,1); + (posedge clk *> (q +: d)) = (3,1); + (/*posedge*/ clk *> (q +: d)) = (3,1); + + // Works: + (/*posedge*/ clk => q) = (3,1); + (/*posedge*/ clk *> q) = (3,1); +endspecify +endmodule diff --git a/tests/various/specify.ys b/tests/various/specify.ys index a5ca07219..a2b6038e4 100644 --- a/tests/various/specify.ys +++ b/tests/various/specify.ys @@ -54,3 +54,5 @@ equiv_struct equiv_induct -seq 5 equiv_status -assert design -reset + +read_verilog specify.v -- cgit v1.2.3 From 2c6aaef3db87fe7955eded675fac452705e5cd48 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 28 Jun 2019 13:32:09 -0700 Subject: Add test --- tests/various/script.ys | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 tests/various/script.ys (limited to 'tests') diff --git a/tests/various/script.ys b/tests/various/script.ys new file mode 100644 index 000000000..6044ad9b3 --- /dev/null +++ b/tests/various/script.ys @@ -0,0 +1,17 @@ +read_verilog -formal < Date: Fri, 28 Jun 2019 13:41:32 -0700 Subject: Try command in another module --- tests/various/script.ys | 3 +++ 1 file changed, 3 insertions(+) (limited to 'tests') diff --git a/tests/various/script.ys b/tests/various/script.ys index 6044ad9b3..9ccc727eb 100644 --- a/tests/various/script.ys +++ b/tests/various/script.ys @@ -6,6 +6,9 @@ read_verilog -formal < Date: Fri, 28 Jun 2019 14:18:56 -0700 Subject: autotest.sh to define _AUTOTB when test_autotb --- tests/tools/autotest.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index 7b64b357f..4d3478628 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -157,7 +157,7 @@ do fi if [ ! -f ../${bn}_tb.v ]; then - "$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.${refext} + "$toolsdir"/../../yosys -f "$frontend $include_opts -D_AUTOTB" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.${refext} else cp ../${bn}_tb.v ${bn}_tb.v fi -- cgit v1.2.3 From 04459cb30aff2341d6de43f7eefe5acaa4bb1db1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sun, 30 Jun 2019 11:48:01 -0700 Subject: Comment out invalid syntax --- tests/various/specify.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/various/specify.v b/tests/various/specify.v index b1f399267..985879f85 100644 --- a/tests/various/specify.v +++ b/tests/various/specify.v @@ -33,9 +33,9 @@ module issue01144(input clk, d, output q); specify // Fails: (posedge clk => (q +: d)) = (3,1); - (/*posedge*/ clk => (q +: d)) = (3,1); + //(/*posedge*/ clk => (q +: d)) = (3,1); // Invalid syntax (posedge clk *> (q +: d)) = (3,1); - (/*posedge*/ clk *> (q +: d)) = (3,1); + //(/*posedge*/ clk *> (q +: d)) = (3,1); // Invalid syntax // Works: (/*posedge*/ clk => q) = (3,1); -- cgit v1.2.3 From d45936fe5f2c6fd1e6f371b2fc3d6d820868ef72 Mon Sep 17 00:00:00 2001 From: David Shah Date: Tue, 2 Jul 2019 13:27:37 +0100 Subject: memory_dff: Fix checking of feedback mux input when more than one mux Signed-off-by: David Shah --- tests/memories/read_two_mux.v | 16 ++++++++++++++++ tests/memories/run-test.sh | 4 ++++ 2 files changed, 20 insertions(+) create mode 100644 tests/memories/read_two_mux.v (limited to 'tests') diff --git a/tests/memories/read_two_mux.v b/tests/memories/read_two_mux.v new file mode 100644 index 000000000..4f2e7e1cd --- /dev/null +++ b/tests/memories/read_two_mux.v @@ -0,0 +1,16 @@ +// expect-wr-ports 1 +// expect-rd-ports 1 +// expect-no-rd-clk + +module top(input clk, input we, re, reset, input [7:0] addr, wdata, output reg [7:0] rdata); + +reg [7:0] bram[0:255]; +(* keep *) reg dummy; + +always @(posedge clk) begin + rdata <= re ? (reset ? 8'b0 : bram[addr]) : rdata; + if (we) + bram[addr] <= wdata; +end + +endmodule diff --git a/tests/memories/run-test.sh b/tests/memories/run-test.sh index 76acaa9cd..8d1a8b413 100755 --- a/tests/memories/run-test.sh +++ b/tests/memories/run-test.sh @@ -31,6 +31,10 @@ for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do grep -q "connect \\\\RD_CLK \\$(gawk '/expect-rd-clk/ { print $3; }' $f)\$" ${f%.v}.dmp || { echo " ERROR: Unexpected read clock."; false; } fi + if grep -q expect-no-rd-clk $f; then + grep -q "connect \\\\RD_CLK 1'x\$" ${f%.v}.dmp || + { echo " ERROR: Expected no read clock."; false; } + fi echo " ok." done -- cgit v1.2.3 From 90382a0f6d1ad7dfd14ced95051e5e76de89491c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 2 Jul 2019 08:19:23 -0700 Subject: Update test too --- tests/various/script.ys | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/various/script.ys b/tests/various/script.ys index 9ccc727eb..4152145e8 100644 --- a/tests/various/script.ys +++ b/tests/various/script.ys @@ -13,8 +13,8 @@ read_verilog -formal < Date: Tue, 2 Jul 2019 08:22:31 -0700 Subject: Update test for Pass::call_on_module() --- tests/various/script.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/various/script.ys b/tests/various/script.ys index 4152145e8..66b7b5caa 100644 --- a/tests/various/script.ys +++ b/tests/various/script.ys @@ -9,7 +9,7 @@ read_verilog -formal < Date: Tue, 2 Jul 2019 19:13:40 -0700 Subject: Add test --- tests/various/abc9.v | 4 ++++ tests/various/abc9.ys | 10 ++++++++++ 2 files changed, 14 insertions(+) (limited to 'tests') diff --git a/tests/various/abc9.v b/tests/various/abc9.v index 8271cd249..a08b613a8 100644 --- a/tests/various/abc9.v +++ b/tests/various/abc9.v @@ -3,3 +3,7 @@ initial o = 1'b0; always @* o <= ~o; endmodule + +module abc9_test028(input i, output o); +unknown u(~i, o); +endmodule diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys index 922f7005d..a84b637d9 100644 --- a/tests/various/abc9.ys +++ b/tests/various/abc9.ys @@ -1,4 +1,6 @@ read_verilog abc9.v +design -save read +hierarchy -top abc9_test027 proc design -save gold @@ -12,3 +14,11 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter +design -load read +hierarchy -top abc9_test028 +proc + +abc9 -lut 4 +select -assert-count 1 t:$lut r:LUT=1 r:WIDTH=1 %i %i +select -assert-count 1 t:unknown +select -assert-none t:$lut t:unknown %% t: %D -- cgit v1.2.3 From ba365679082cff2b9879eef5349bfdf2b5291449 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 3 Jul 2019 11:22:10 +0200 Subject: Some cleanups in "ignore specify parser" Signed-off-by: Clifford Wolf --- tests/various/specify.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/various/specify.v b/tests/various/specify.v index 985879f85..73a59eb7a 100644 --- a/tests/various/specify.v +++ b/tests/various/specify.v @@ -7,7 +7,7 @@ module test ( if (EN) Q <= D; specify - if (EN) (CLK *> (Q : D)) = (1, 2:3:4); + if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4); $setup(D, posedge CLK &&& EN, 5); $hold(posedge CLK, D &&& EN, 6); endspecify -- cgit v1.2.3 From 1f173210ebbf2cd5b5714e351ed40b6141d90b14 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 3 Jul 2019 11:25:05 +0200 Subject: Fix tests/various/specify.v Signed-off-by: Clifford Wolf --- tests/various/specify.v | 9 ++------- tests/various/specify.ys | 2 +- 2 files changed, 3 insertions(+), 8 deletions(-) (limited to 'tests') diff --git a/tests/various/specify.v b/tests/various/specify.v index 73a59eb7a..5d44d78f7 100644 --- a/tests/various/specify.v +++ b/tests/various/specify.v @@ -7,9 +7,11 @@ module test ( if (EN) Q <= D; specify +`ifndef SKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4); $setup(D, posedge CLK &&& EN, 5); $hold(posedge CLK, D &&& EN, 6); +`endif endspecify endmodule @@ -31,14 +33,7 @@ endmodule module issue01144(input clk, d, output q); specify - // Fails: (posedge clk => (q +: d)) = (3,1); - //(/*posedge*/ clk => (q +: d)) = (3,1); // Invalid syntax (posedge clk *> (q +: d)) = (3,1); - //(/*posedge*/ clk *> (q +: d)) = (3,1); // Invalid syntax - - // Works: - (/*posedge*/ clk => q) = (3,1); - (/*posedge*/ clk *> q) = (3,1); endspecify endmodule diff --git a/tests/various/specify.ys b/tests/various/specify.ys index a2b6038e4..00597e1e2 100644 --- a/tests/various/specify.ys +++ b/tests/various/specify.ys @@ -55,4 +55,4 @@ equiv_induct -seq 5 equiv_status -assert design -reset -read_verilog specify.v +read_verilog -DSKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS specify.v -- cgit v1.2.3 From f8512864cd2b9c0c17d71d4196dbf3f25ec554d1 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 9 Jul 2019 20:58:01 +0200 Subject: Add tests/simple_abc9/.gitignore Signed-off-by: Clifford Wolf --- tests/simple_abc9/.gitignore | 3 +++ 1 file changed, 3 insertions(+) create mode 100644 tests/simple_abc9/.gitignore (limited to 'tests') diff --git a/tests/simple_abc9/.gitignore b/tests/simple_abc9/.gitignore new file mode 100644 index 000000000..598951333 --- /dev/null +++ b/tests/simple_abc9/.gitignore @@ -0,0 +1,3 @@ +*.v +*.log +*.out -- cgit v1.2.3 From 3dd92fcd15bc3f1448a97e6bb7c997d36781b55c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 9 Jul 2019 20:58:28 +0200 Subject: Improve tests/various/run-test.sh Signed-off-by: Clifford Wolf --- tests/various/run-test.sh | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) (limited to 'tests') diff --git a/tests/various/run-test.sh b/tests/various/run-test.sh index d49553ede..92b905765 100755 --- a/tests/various/run-test.sh +++ b/tests/various/run-test.sh @@ -4,11 +4,9 @@ for x in *.ys; do echo "Running $x.." ../../yosys -ql ${x%.ys}.log $x done -# Run any .sh files in this directory (with the exception of the file - run-test.sh -shell_tests=$(echo *.sh | sed -e 's/run-test.sh//') -if [ "$shell_tests" ]; then - for s in $shell_tests; do - echo "Running $s.." - bash $s - done -fi +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "Running $s.." + bash $s + fi +done -- cgit v1.2.3 From c18b23f0559f2232186ce3b97b4ffb64877abd5c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 9 Jul 2019 20:58:59 +0200 Subject: Add tests/various/async.{sh,v} Signed-off-by: Clifford Wolf --- tests/various/async.sh | 6 ++++ tests/various/async.v | 82 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 88 insertions(+) create mode 100644 tests/various/async.sh create mode 100644 tests/various/async.v (limited to 'tests') diff --git a/tests/various/async.sh b/tests/various/async.sh new file mode 100644 index 000000000..423034eb8 --- /dev/null +++ b/tests/various/async.sh @@ -0,0 +1,6 @@ +#!/bin/bash +set -ex +../../yosys -q -o async_syn.v -p 'synth; rename uut syn' async.v +iverilog -o async_sim -DTESTBENCH async.v async_syn.v +vvp -N async_sim > async.out +rm -f async_syn.v async_sim async.out async.vcd diff --git a/tests/various/async.v b/tests/various/async.v new file mode 100644 index 000000000..229b5b939 --- /dev/null +++ b/tests/various/async.v @@ -0,0 +1,82 @@ +`define MAXQ 2 +module uut ( + input clk, + input d, r, e, + output [`MAXQ:0] q +); + reg q0; + always @(posedge clk) begin + if (r) + q0 <= 0; + else if (e) + q0 <= d; + end + + reg q1; + always @(posedge clk, posedge r) begin + if (r) + q1 <= 0; + else if (e) + q1 <= d; + end + + reg q2; + always @(posedge clk, negedge r) begin + if (!r) + q2 <= 0; + else if (!e) + q2 <= d; + end + + assign q = {q2, q1, q0}; +endmodule + +`ifdef TESTBENCH +module testbench; + reg clk; + always #5 clk = (clk === 1'b0); + + reg d, r, e; + + wire [`MAXQ:0] q_uut; + uut uut (.clk(clk), .d(d), .r(r), .e(e), .q(q_uut)); + + wire [`MAXQ:0] q_syn; + syn syn (.clk(clk), .d(d), .r(r), .e(e), .q(q_syn)); + + task printq; + reg [5*8-1:0] msg; + begin + msg = "OK"; + if (q_uut != q_syn) msg = "SYN"; + $display("%6t %b %b %s", $time, q_uut, q_syn, msg); + if (msg != "OK") $stop; + end + endtask + + initial if(0) begin + $dumpfile("async.vcd"); + $dumpvars(0, testbench); + end + + initial begin + @(posedge clk); + d <= 0; + r <= 0; + e <= 0; + @(posedge clk); + e <= 1; + @(posedge clk); + e <= 0; + repeat (10000) begin + @(posedge clk); + printq; + d <= $random; + r <= $random; + e <= $random; + end + $display("OK"); + $finish; + end +endmodule +`endif -- cgit v1.2.3 From 513862148211401fe71fb7966c81773042665acd Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 9 Jul 2019 22:21:25 +0200 Subject: Improve tests/various/async, disable failing ffl test Signed-off-by: Clifford Wolf --- tests/various/async.sh | 9 +++++++-- tests/various/async.v | 36 +++++++++++++++++++++++++++++++----- 2 files changed, 38 insertions(+), 7 deletions(-) (limited to 'tests') diff --git a/tests/various/async.sh b/tests/various/async.sh index 423034eb8..7c41d6d94 100644 --- a/tests/various/async.sh +++ b/tests/various/async.sh @@ -1,6 +1,11 @@ #!/bin/bash set -ex ../../yosys -q -o async_syn.v -p 'synth; rename uut syn' async.v -iverilog -o async_sim -DTESTBENCH async.v async_syn.v +../../yosys -q -o async_prp.v -p 'prep; rename uut prp' async.v +../../yosys -q -o async_a2s.v -p 'prep; async2sync; rename uut a2s' async.v +../../yosys -q -o async_ffl.v -p 'prep; clk2fflogic; rename uut ffl' async.v +iverilog -o async_sim -DTESTBENCH async.v async_???.v vvp -N async_sim > async.out -rm -f async_syn.v async_sim async.out async.vcd +tail async.out +grep PASS async.out +rm -f async_???.v async_sim async.out async.vcd diff --git a/tests/various/async.v b/tests/various/async.v index 229b5b939..1e32a06b5 100644 --- a/tests/various/async.v +++ b/tests/various/async.v @@ -32,9 +32,23 @@ module uut ( endmodule `ifdef TESTBENCH +module \$ff #( + parameter integer WIDTH = 1 +) ( + input [WIDTH-1:0] D, + output reg [WIDTH-1:0] Q +); + wire sysclk = testbench.sysclk; + always @(posedge sysclk) + Q <= D; +endmodule + module testbench; + reg sysclk; + always #5 sysclk = (sysclk === 1'b0); + reg clk; - always #5 clk = (clk === 1'b0); + always @(posedge sysclk) clk = (clk === 1'b0); reg d, r, e; @@ -44,13 +58,25 @@ module testbench; wire [`MAXQ:0] q_syn; syn syn (.clk(clk), .d(d), .r(r), .e(e), .q(q_syn)); + wire [`MAXQ:0] q_prp; + prp prp (.clk(clk), .d(d), .r(r), .e(e), .q(q_prp)); + + wire [`MAXQ:0] q_a2s; + a2s a2s (.clk(clk), .d(d), .r(r), .e(e), .q(q_a2s)); + + wire [`MAXQ:0] q_ffl; + ffl ffl (.clk(clk), .d(d), .r(r), .e(e), .q(q_ffl)); + task printq; reg [5*8-1:0] msg; begin msg = "OK"; - if (q_uut != q_syn) msg = "SYN"; - $display("%6t %b %b %s", $time, q_uut, q_syn, msg); - if (msg != "OK") $stop; + if (q_uut !== q_syn) msg = "SYN"; + if (q_uut !== q_prp) msg = "PRP"; + if (q_uut !== q_a2s) msg = "A2S"; + // if (q_uut !== q_ffl) msg = "FFL"; + $display("%6t %b %b %b %b %b %s", $time, q_uut, q_syn, q_prp, q_a2s, q_ffl, msg); + if (msg != "OK") $finish; end endtask @@ -75,7 +101,7 @@ module testbench; r <= $random; e <= $random; end - $display("OK"); + $display("PASS"); $finish; end endmodule -- cgit v1.2.3 From 9546ccdbd348b1dc056884a536246801cdf1c4f1 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 9 Jul 2019 22:44:39 +0200 Subject: Fix tests/various/async FFL test Signed-off-by: Clifford Wolf --- tests/various/async.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/various/async.v b/tests/various/async.v index 1e32a06b5..c27e30c4b 100644 --- a/tests/various/async.v +++ b/tests/various/async.v @@ -74,7 +74,7 @@ module testbench; if (q_uut !== q_syn) msg = "SYN"; if (q_uut !== q_prp) msg = "PRP"; if (q_uut !== q_a2s) msg = "A2S"; - // if (q_uut !== q_ffl) msg = "FFL"; + if (q_uut !== q_ffl) msg = "FFL"; $display("%6t %b %b %b %b %b %s", $time, q_uut, q_syn, q_prp, q_a2s, q_ffl, msg); if (msg != "OK") $finish; end -- cgit v1.2.3 From 41243a53b384a9ecfadd7b424c9e22c7c84fb721 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 12 Jul 2019 21:00:13 -0700 Subject: Update test with more accurate LUT mask --- tests/various/abc9.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys index a84b637d9..5c9a4075d 100644 --- a/tests/various/abc9.ys +++ b/tests/various/abc9.ys @@ -19,6 +19,6 @@ hierarchy -top abc9_test028 proc abc9 -lut 4 -select -assert-count 1 t:$lut r:LUT=1 r:WIDTH=1 %i %i +select -assert-count 1 t:$lut r:LUT=2'b01 r:WIDTH=1 %i %i select -assert-count 1 t:unknown select -assert-none t:$lut t:unknown %% t: %D -- cgit v1.2.3 From dd10d2b00d6760f2d09f55c90591855afcae409e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 16 Jul 2019 12:11:59 -0700 Subject: Add tests for cmp2lut on LUT6 --- tests/lut/map_cmp.v | 47 ++++++++++++++++++++++++----------------------- tests/lut/run-test.sh | 5 +++++ 2 files changed, 29 insertions(+), 23 deletions(-) (limited to 'tests') diff --git a/tests/lut/map_cmp.v b/tests/lut/map_cmp.v index 5e413f894..0014eb9ac 100644 --- a/tests/lut/map_cmp.v +++ b/tests/lut/map_cmp.v @@ -1,29 +1,30 @@ module top(...); - input [3:0] a; + parameter LUT_WIDTH = 4; // Multiples of 2 only + input [LUT_WIDTH-1:0] a; - output o1_1 = 4'b1010 <= a; - output o1_2 = 4'b1010 < a; - output o1_3 = 4'b1010 >= a; - output o1_4 = 4'b1010 > a; - output o1_5 = 4'b1010 == a; - output o1_6 = 4'b1010 != a; + output o1_1 = {(LUT_WIDTH/2){2'b10}} <= a; + output o1_2 = {(LUT_WIDTH/2){2'b10}} < a; + output o1_3 = {(LUT_WIDTH/2){2'b10}} >= a; + output o1_4 = {(LUT_WIDTH/2){2'b10}} > a; + output o1_5 = {(LUT_WIDTH/2){2'b10}} == a; + output o1_6 = {(LUT_WIDTH/2){2'b10}} != a; - output o2_1 = a <= 4'b1010; - output o2_2 = a < 4'b1010; - output o2_3 = a >= 4'b1010; - output o2_4 = a > 4'b1010; - output o2_5 = a == 4'b1010; - output o2_6 = a != 4'b1010; + output o2_1 = a <= {(LUT_WIDTH/2){2'b10}}; + output o2_2 = a < {(LUT_WIDTH/2){2'b10}}; + output o2_3 = a >= {(LUT_WIDTH/2){2'b10}}; + output o2_4 = a > {(LUT_WIDTH/2){2'b10}}; + output o2_5 = a == {(LUT_WIDTH/2){2'b10}}; + output o2_6 = a != {(LUT_WIDTH/2){2'b10}}; - output o3_1 = 4'sb0101 <= $signed(a); - output o3_2 = 4'sb0101 < $signed(a); - output o3_3 = 4'sb0101 >= $signed(a); - output o3_4 = 4'sb0101 > $signed(a); - output o3_5 = 4'sb0101 == $signed(a); - output o3_6 = 4'sb0101 != $signed(a); + output o3_1 = {(LUT_WIDTH/2){2'sb01}} <= $signed(a); + output o3_2 = {(LUT_WIDTH/2){2'sb01}} < $signed(a); + output o3_3 = {(LUT_WIDTH/2){2'sb01}} >= $signed(a); + output o3_4 = {(LUT_WIDTH/2){2'sb01}} > $signed(a); + output o3_5 = {(LUT_WIDTH/2){2'sb01}} == $signed(a); + output o3_6 = {(LUT_WIDTH/2){2'sb01}} != $signed(a); - output o4_1 = $signed(a) <= 4'sb0000; - output o4_2 = $signed(a) < 4'sb0000; - output o4_3 = $signed(a) >= 4'sb0000; - output o4_4 = $signed(a) > 4'sb0000; + output o4_1 = $signed(a) <= {LUT_WIDTH{1'sb0}}; + output o4_2 = $signed(a) < {LUT_WIDTH{1'sb0}}; + output o4_3 = $signed(a) >= {LUT_WIDTH{1'sb0}}; + output o4_4 = $signed(a) > {LUT_WIDTH{1'sb0}}; endmodule diff --git a/tests/lut/run-test.sh b/tests/lut/run-test.sh index 207417fa6..f8964f146 100755 --- a/tests/lut/run-test.sh +++ b/tests/lut/run-test.sh @@ -4,3 +4,8 @@ for x in *.v; do echo "Running $x.." ../../yosys -q -s check_map.ys -l ${x%.v}.log $x done + +for x in map_cmp.v; do + echo "Running $x.." + ../../yosys -q -s check_map_lut6.ys -l ${x%.v}_lut6.log $x +done -- cgit v1.2.3 From 8a2a2cd035d5fe931899256711ed972fd1da3a3b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 16 Jul 2019 12:44:26 -0700 Subject: Forgot to commit --- tests/lut/check_map_lut6.ys | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 tests/lut/check_map_lut6.ys (limited to 'tests') diff --git a/tests/lut/check_map_lut6.ys b/tests/lut/check_map_lut6.ys new file mode 100644 index 000000000..8a32e4d10 --- /dev/null +++ b/tests/lut/check_map_lut6.ys @@ -0,0 +1,7 @@ +chparam -set LUT_WIDTH 6 top +simplemap +equiv_opt -assert techmap -D LUT_WIDTH=6 -map +/cmp2lut.v +design -load postopt +equiv_opt -assert techmap -D LUT_WIDTH=6 -map +/gate2lut.v +design -load postopt +select -assert-count 0 t:* t:$lut %d -- cgit v1.2.3