From 8de17877d4073a6e593ea650b8eca0488f653d24 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 3 Dec 2019 14:48:00 -0800
Subject: Add testcase

---
 tests/arch/ice40/ice40_opt.ys | 60 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 60 insertions(+)

(limited to 'tests')

diff --git a/tests/arch/ice40/ice40_opt.ys b/tests/arch/ice40/ice40_opt.ys
index b17c69c91..58c33acaa 100644
--- a/tests/arch/ice40/ice40_opt.ys
+++ b/tests/arch/ice40/ice40_opt.ys
@@ -24,3 +24,63 @@ equiv_opt -assert -map +/ice40/cells_map.v -map +/ice40/cells_sim.v ice40_opt
 design -load postopt
 select -assert-count 1 t:*
 select -assert-count 1 t:$lut
+
+# https://github.com/YosysHQ/yosys/issues/1543
+design -reset
+read_verilog <<EOT
+module delay_element (input wire clk, input wire reset, input wire enable,
+                      input wire chainin,  output wire chainout, output reg latch);
+
+
+   reg                           const_zero = 0;
+   reg                           const_one = 1;
+
+    wire                         delay_tap;
+
+
+   //carry logic
+   (* keep *) SB_CARRY carry ( .CO(chainout), .I0(const_zero),
+                    .I1(const_one), .CI(chainin));
+
+
+   //flip flop latch
+   (* keep *) SB_DFFER flipflop( .Q(latch), .C(clk), .E(enable),
+                      .D(delay_tap), .R(reset));
+
+
+   //LUT table
+   // the LUT should just echo the carry in (I3)
+   // carry I0 = LUT I1
+   // carry I1 = LUT I2
+   // carry in = LUT I3
+   // LUT_INIT[0] = 0
+   // LUT_INIT[1] = 0
+   // LUT_INIT[2] = 0
+   // LUT_INIT[3] = 0
+   // LUT_INIT[4] = 0
+   // LUT_INIT[5] = 0
+   // LUT_INIT[6] = 0
+   // LUT_INIT[7] = 0
+   // LUT_INIT[8] = 1
+   // LUT_INIT[9] = 1
+   // LUT_INIT[10] = 1
+   // LUT_INIT[11] = 1
+   // LUT_INIT[12] = 1
+   // LUT_INIT[13] = 1
+   // LUT_INIT[14] = 1
+   // LUT_INIT[15] = 1
+
+   (* keep *) SB_LUT4 lut( .O(delay_tap), .I0(const_zero), .I1(const_zero),
+                .I2(const_one), .I3(chainin));
+
+   //TODO: is this the right way round??
+   defparam lut.LUT_INIT=16'hFF00;
+
+
+endmodule // delay_element
+EOT
+
+synth_ice40
+select -assert-count 1 t:SB_LUT4
+select -assert-count 1 t:SB_CARRY
+select -assert-count 1 t:SB_CARRY a:keep %i
-- 
cgit v1.2.3


From 67f1ce2d4340c359137ac00e4ca085e6711986f3 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 3 Dec 2019 14:51:39 -0800
Subject: Check SB_CARRY name also preserved

---
 tests/arch/ice40/ice40_opt.ys | 1 +
 1 file changed, 1 insertion(+)

(limited to 'tests')

diff --git a/tests/arch/ice40/ice40_opt.ys b/tests/arch/ice40/ice40_opt.ys
index 58c33acaa..860e2e211 100644
--- a/tests/arch/ice40/ice40_opt.ys
+++ b/tests/arch/ice40/ice40_opt.ys
@@ -84,3 +84,4 @@ synth_ice40
 select -assert-count 1 t:SB_LUT4
 select -assert-count 1 t:SB_CARRY
 select -assert-count 1 t:SB_CARRY a:keep %i
+select -assert-count 1 t:SB_CARRY c:carry %i
-- 
cgit v1.2.3


From d8fbf88980d6ccd22e2aa3f34c4ff2a39aeed9df Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 5 Dec 2019 07:01:02 -0800
Subject: Add WIP test for unwrapping $__ICE40_CARRY_WRAPPER

---
 tests/arch/ice40/wrapcarry.ys | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

(limited to 'tests')

diff --git a/tests/arch/ice40/wrapcarry.ys b/tests/arch/ice40/wrapcarry.ys
index 10c029e68..a4b0d357a 100644
--- a/tests/arch/ice40/wrapcarry.ys
+++ b/tests/arch/ice40/wrapcarry.ys
@@ -20,3 +20,33 @@ EOT
 
 ice40_wrapcarry
 select -assert-count 1 t:$__ICE40_CARRY_WRAPPER
+
+design -reset
+read_verilog <<EOT
+module top(input A, B, CI, output O, CO);
+    (* foo = "bar", answer = 42 *)
+	SB_CARRY carry (
+		.I0(A),
+		.I1(B),
+		.CI(CI),
+		.CO(CO)
+	);
+    (* keep, blah="blah", answer = 43 *)
+	SB_LUT4 #(
+		.LUT_INIT(16'b 0110_1001_1001_0110)
+	) adder (
+		.I0(1'b0),
+		.I1(A),
+		.I2(B),
+		.I3(1'b0),
+		.O(O)
+	);
+endmodule
+EOT
+
+ice40_wrapcarry
+select -assert-count 1 t:$__ICE40_CARRY_WRAPPER
+select -assert-count 0 t:* t:$__ICE40_CARRY_WRAPPER %d
+select -assert-count 1 a:foo=bar a:answer=42 %i a:keep %i a:blah=blah %i
+techmap -map +/ice40/cells_map.v
+#TODO: Check unwrapped attributes
-- 
cgit v1.2.3


From 946d5854c0b2e63a3757a0fbdf41276255967bc8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 6 Dec 2019 17:27:47 -0800
Subject: Drop keep=0 attributes on SB_CARRY

---
 tests/arch/ice40/wrapcarry.ys | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/arch/ice40/wrapcarry.ys b/tests/arch/ice40/wrapcarry.ys
index a4b0d357a..579335b27 100644
--- a/tests/arch/ice40/wrapcarry.ys
+++ b/tests/arch/ice40/wrapcarry.ys
@@ -24,7 +24,7 @@ select -assert-count 1 t:$__ICE40_CARRY_WRAPPER
 design -reset
 read_verilog <<EOT
 module top(input A, B, CI, output O, CO);
-    (* foo = "bar", answer = 42 *)
+    (* foo = "bar", answer = 42, keep=0 *)
 	SB_CARRY carry (
 		.I0(A),
 		.I1(B),
@@ -47,6 +47,6 @@ EOT
 ice40_wrapcarry
 select -assert-count 1 t:$__ICE40_CARRY_WRAPPER
 select -assert-count 0 t:* t:$__ICE40_CARRY_WRAPPER %d
-select -assert-count 1 a:foo=bar a:answer=42 %i a:keep %i a:blah=blah %i
+select -assert-count 1 a:foo=bar a:answer=42 %i a:keep=1 %i a:blah=blah %i
 techmap -map +/ice40/cells_map.v
 #TODO: Check unwrapped attributes
-- 
cgit v1.2.3


From e05372778a26e5cbc5166f208eddc6a1b42ed198 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 9 Dec 2019 11:48:28 -0800
Subject: ice40_wrapcarry to really preserve attributes via -unwrap option

---
 tests/arch/ice40/ice40_wrapcarry.ys | 54 +++++++++++++++++++++++++++++++++++++
 tests/arch/ice40/wrapcarry.ys       | 52 -----------------------------------
 2 files changed, 54 insertions(+), 52 deletions(-)
 create mode 100644 tests/arch/ice40/ice40_wrapcarry.ys
 delete mode 100644 tests/arch/ice40/wrapcarry.ys

(limited to 'tests')

diff --git a/tests/arch/ice40/ice40_wrapcarry.ys b/tests/arch/ice40/ice40_wrapcarry.ys
new file mode 100644
index 000000000..fb9fccc3a
--- /dev/null
+++ b/tests/arch/ice40/ice40_wrapcarry.ys
@@ -0,0 +1,54 @@
+read_verilog <<EOT
+module top(input A, B, CI, output O, CO);
+	SB_CARRY carry (
+		.I0(A),
+		.I1(B),
+		.CI(CI),
+		.CO(CO)
+	);
+	SB_LUT4 #(
+		.LUT_INIT(16'b 0110_1001_1001_0110)
+	) adder (
+		.I0(1'b0),
+		.I1(A),
+		.I2(B),
+		.I3(1'b0),
+		.O(O)
+	);
+endmodule
+EOT
+
+ice40_wrapcarry
+select -assert-count 1 t:$__ICE40_CARRY_WRAPPER
+
+design -reset
+read_verilog <<EOT
+module top(input A, B, CI, output O, CO);
+    (* foo = "bar", answer = 42, keep=0 *)
+	SB_CARRY carry (
+		.I0(A),
+		.I1(B),
+		.CI(CI),
+		.CO(CO)
+	);
+    (* keep, blah="blah", answer = 43 *)
+	SB_LUT4 #(
+		.LUT_INIT(16'b 0110_1001_1001_0110)
+	) adder (
+		.I0(1'b0),
+		.I1(A),
+		.I2(B),
+		.I3(1'b0),
+		.O(O)
+	);
+endmodule
+EOT
+
+ice40_wrapcarry
+select -assert-count 1 t:$__ICE40_CARRY_WRAPPER
+select -assert-count 0 t:* t:$__ICE40_CARRY_WRAPPER %d
+select -assert-count 1 a:keep=1 a:SB_CARRY.\foo=bar %i a:SB_CARRY.\answer=42 %i a:SB_LUT4.\blah=blah %i a:SB_LUT4.\answer=43 %i
+
+ice40_wrapcarry -unwrap
+select -assert-count 1 c:carry a:src=<<EOT:3 %i a:keep=0 %i a:foo=bar %i a:answer=42 %i
+select -assert-count 1 c:adder a:src=<<EOT:10 %i a:keep=1 %i a:blah=blah %i a:answer=43 %i
diff --git a/tests/arch/ice40/wrapcarry.ys b/tests/arch/ice40/wrapcarry.ys
deleted file mode 100644
index 579335b27..000000000
--- a/tests/arch/ice40/wrapcarry.ys
+++ /dev/null
@@ -1,52 +0,0 @@
-read_verilog <<EOT
-module top(input A, B, CI, output O, CO);
-	SB_CARRY carry (
-		.I0(A),
-		.I1(B),
-		.CI(CI),
-		.CO(CO)
-	);
-	SB_LUT4 #(
-		.LUT_INIT(16'b 0110_1001_1001_0110)
-	) adder (
-		.I0(1'b0),
-		.I1(A),
-		.I2(B),
-		.I3(1'b0),
-		.O(O)
-	);
-endmodule
-EOT
-
-ice40_wrapcarry
-select -assert-count 1 t:$__ICE40_CARRY_WRAPPER
-
-design -reset
-read_verilog <<EOT
-module top(input A, B, CI, output O, CO);
-    (* foo = "bar", answer = 42, keep=0 *)
-	SB_CARRY carry (
-		.I0(A),
-		.I1(B),
-		.CI(CI),
-		.CO(CO)
-	);
-    (* keep, blah="blah", answer = 43 *)
-	SB_LUT4 #(
-		.LUT_INIT(16'b 0110_1001_1001_0110)
-	) adder (
-		.I0(1'b0),
-		.I1(A),
-		.I2(B),
-		.I3(1'b0),
-		.O(O)
-	);
-endmodule
-EOT
-
-ice40_wrapcarry
-select -assert-count 1 t:$__ICE40_CARRY_WRAPPER
-select -assert-count 0 t:* t:$__ICE40_CARRY_WRAPPER %d
-select -assert-count 1 a:foo=bar a:answer=42 %i a:keep=1 %i a:blah=blah %i
-techmap -map +/ice40/cells_map.v
-#TODO: Check unwrapped attributes
-- 
cgit v1.2.3


From eff858cd33403a13736ac74cce6964648306e594 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 9 Dec 2019 14:20:35 -0800
Subject: unmap $__ICE40_CARRY_WRAPPER in test

---
 tests/arch/ice40/ice40_opt.ys | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/arch/ice40/ice40_opt.ys b/tests/arch/ice40/ice40_opt.ys
index 860e2e211..5186d4800 100644
--- a/tests/arch/ice40/ice40_opt.ys
+++ b/tests/arch/ice40/ice40_opt.ys
@@ -1,3 +1,23 @@
+read_verilog -icells -formal <<EOT
+module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3);
+  parameter LUT = 0;
+  SB_CARRY carry (
+    .I0(A),
+    .I1(B),
+    .CI(CI),
+    .CO(CO)
+  );
+  \$lut #(
+    .WIDTH(4),
+    .LUT(LUT)
+  ) lut (
+    .A({I0,A,B,I3}),
+    .Y(O)
+  );
+endmodule
+EOT
+design -stash unmap
+
 read_verilog -icells -formal <<EOT
 module top(input CI, I0, output [1:0] CO, output O);
     wire A = 1'b0, B = 1'b0;
@@ -20,7 +40,7 @@ module top(input CI, I0, output [1:0] CO, output O);
 endmodule
 EOT
 
-equiv_opt -assert -map +/ice40/cells_map.v -map +/ice40/cells_sim.v ice40_opt
+equiv_opt -assert -map %unmap -map +/ice40/cells_sim.v ice40_opt
 design -load postopt
 select -assert-count 1 t:*
 select -assert-count 1 t:$lut
-- 
cgit v1.2.3