From 11f330ed223f524cbbdbe2433599990a69b8f380 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Tue, 3 Sep 2019 11:53:37 +0300 Subject: Add tests for ECP5 architecture --- tests/ecp5/.gitignore | 2 + tests/ecp5/add_sub.v | 13 + tests/ecp5/add_sub.ys | 8 + tests/ecp5/adffs.v | 91 ++ tests/ecp5/adffs.ys | 10 + tests/ecp5/alu.v | 19 + tests/ecp5/alu.ys | 11 + tests/ecp5/counter.v | 17 + tests/ecp5/counter.ys | 11 + tests/ecp5/dffs.v | 37 + tests/ecp5/dffs.ys | 9 + tests/ecp5/div_mod.v | 13 + tests/ecp5/div_mod.ys | 12 + tests/ecp5/dpram.v | 23 + tests/ecp5/dpram.ys | 18 + tests/ecp5/dpram_synth.v | 165 ++++ tests/ecp5/fsm.v | 73 ++ tests/ecp5/fsm.ys | 13 + tests/ecp5/latches.v | 58 ++ tests/ecp5/latches.ys | 17 + tests/ecp5/latches_synth.v | 109 +++ tests/ecp5/logic.v | 18 + tests/ecp5/logic.ys | 7 + tests/ecp5/macc.v | 25 + tests/ecp5/macc.ys | 15 + tests/ecp5/memory.v | 21 + tests/ecp5/memory.ys | 21 + tests/ecp5/memory_synth.v | 2121 ++++++++++++++++++++++++++++++++++++++++++++ tests/ecp5/mul.v | 11 + tests/ecp5/mul.ys | 11 + tests/ecp5/mux.v | 100 +++ tests/ecp5/mux.ys | 11 + tests/ecp5/rom.v | 18 + tests/ecp5/rom.ys | 9 + tests/ecp5/run-test.sh | 20 + tests/ecp5/shifter.v | 22 + tests/ecp5/shifter.ys | 9 + tests/ecp5/tribuf.v | 23 + tests/ecp5/tribuf.ys | 9 + 39 files changed, 3200 insertions(+) create mode 100644 tests/ecp5/.gitignore create mode 100644 tests/ecp5/add_sub.v create mode 100644 tests/ecp5/add_sub.ys create mode 100644 tests/ecp5/adffs.v create mode 100644 tests/ecp5/adffs.ys create mode 100644 tests/ecp5/alu.v create mode 100644 tests/ecp5/alu.ys create mode 100644 tests/ecp5/counter.v create mode 100644 tests/ecp5/counter.ys create mode 100644 tests/ecp5/dffs.v create mode 100644 tests/ecp5/dffs.ys create mode 100644 tests/ecp5/div_mod.v create mode 100644 tests/ecp5/div_mod.ys create mode 100644 tests/ecp5/dpram.v create mode 100644 tests/ecp5/dpram.ys create mode 100644 tests/ecp5/dpram_synth.v create mode 100644 tests/ecp5/fsm.v create mode 100644 tests/ecp5/fsm.ys create mode 100644 tests/ecp5/latches.v create mode 100644 tests/ecp5/latches.ys create mode 100644 tests/ecp5/latches_synth.v create mode 100644 tests/ecp5/logic.v create mode 100644 tests/ecp5/logic.ys create mode 100644 tests/ecp5/macc.v create mode 100644 tests/ecp5/macc.ys create mode 100644 tests/ecp5/memory.v create mode 100644 tests/ecp5/memory.ys create mode 100644 tests/ecp5/memory_synth.v create mode 100644 tests/ecp5/mul.v create mode 100644 tests/ecp5/mul.ys create mode 100644 tests/ecp5/mux.v create mode 100644 tests/ecp5/mux.ys create mode 100644 tests/ecp5/rom.v create mode 100644 tests/ecp5/rom.ys create mode 100755 tests/ecp5/run-test.sh create mode 100644 tests/ecp5/shifter.v create mode 100644 tests/ecp5/shifter.ys create mode 100644 tests/ecp5/tribuf.v create mode 100644 tests/ecp5/tribuf.ys (limited to 'tests') diff --git a/tests/ecp5/.gitignore b/tests/ecp5/.gitignore new file mode 100644 index 000000000..1d329c933 --- /dev/null +++ b/tests/ecp5/.gitignore @@ -0,0 +1,2 @@ +*.log +/run-test.mk diff --git a/tests/ecp5/add_sub.v b/tests/ecp5/add_sub.v new file mode 100644 index 000000000..177c32e30 --- /dev/null +++ b/tests/ecp5/add_sub.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x + y; +assign B = x - y; + +endmodule diff --git a/tests/ecp5/add_sub.ys b/tests/ecp5/add_sub.ys new file mode 100644 index 000000000..03aec6694 --- /dev/null +++ b/tests/ecp5/add_sub.ys @@ -0,0 +1,8 @@ +read_verilog add_sub.v +hierarchy -top top +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 10 t:LUT4 +select -assert-none t:LUT4 %% t:* %D + diff --git a/tests/ecp5/adffs.v b/tests/ecp5/adffs.v new file mode 100644 index 000000000..93c8bf52c --- /dev/null +++ b/tests/ecp5/adffs.v @@ -0,0 +1,91 @@ +module adff + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge clr ) + if ( clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module adffn + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, negedge clr ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module dffsr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge pre, posedge clr ) + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module ndffnsnr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( negedge clk, negedge pre, negedge clr ) + if ( !clr ) + q <= 1'b0; + else if ( !pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2,b3 +); + +dffsr u_dffsr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b ) + ); + +ndffnsnr u_ndffnsnr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b1 ) + ); + +adff u_adff ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b2 ) + ); + +adffn u_adffn ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b3 ) + ); + +endmodule diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys new file mode 100644 index 000000000..7ec2b0114 --- /dev/null +++ b/tests/ecp5/adffs.ys @@ -0,0 +1,10 @@ +read_verilog adffs.v +proc +async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 4 t:TRELLIS_FF +select -assert-count 7 t:LUT4 +select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D diff --git a/tests/ecp5/alu.v b/tests/ecp5/alu.v new file mode 100644 index 000000000..f82cc2e21 --- /dev/null +++ b/tests/ecp5/alu.v @@ -0,0 +1,19 @@ +module top ( + input clock, + input [31:0] dinA, dinB, + input [2:0] opcode, + output reg [31:0] dout +); + always @(posedge clock) begin + case (opcode) + 0: dout <= dinA + dinB; + 1: dout <= dinA - dinB; + 2: dout <= dinA >> dinB; + 3: dout <= $signed(dinA) >>> dinB; + 4: dout <= dinA << dinB; + 5: dout <= dinA & dinB; + 6: dout <= dinA | dinB; + 7: dout <= dinA ^ dinB; + endcase + end +endmodule diff --git a/tests/ecp5/alu.ys b/tests/ecp5/alu.ys new file mode 100644 index 000000000..bd859efc4 --- /dev/null +++ b/tests/ecp5/alu.ys @@ -0,0 +1,11 @@ +read_verilog alu.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 62 t:SB_CARRY +select -assert-count 32 t:SB_DFF +select -assert-count 655 t:SB_LUT4 +select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D diff --git a/tests/ecp5/counter.v b/tests/ecp5/counter.v new file mode 100644 index 000000000..52852f8ac --- /dev/null +++ b/tests/ecp5/counter.v @@ -0,0 +1,17 @@ +module top ( +out, +clk, +reset +); + output [7:0] out; + input clk, reset; + reg [7:0] out; + + always @(posedge clk, posedge reset) + if (reset) begin + out <= 8'b0 ; + end else + out <= out + 1; + + +endmodule diff --git a/tests/ecp5/counter.ys b/tests/ecp5/counter.ys new file mode 100644 index 000000000..c65c21622 --- /dev/null +++ b/tests/ecp5/counter.ys @@ -0,0 +1,11 @@ +read_verilog counter.v +hierarchy -top top +proc +flatten +equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 6 t:SB_CARRY +select -assert-count 8 t:SB_DFFR +select -assert-count 8 t:SB_LUT4 +select -assert-none t:SB_CARRY t:SB_DFFR t:SB_LUT4 %% t:* %D diff --git a/tests/ecp5/dffs.v b/tests/ecp5/dffs.v new file mode 100644 index 000000000..d97840c43 --- /dev/null +++ b/tests/ecp5/dffs.v @@ -0,0 +1,37 @@ +module dff + ( input d, clk, output reg q ); + always @( posedge clk ) + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule + +module top ( +input clk, +input en, +input a, +output b,b1, +); + +dff u_dff ( + .clk (clk ), + .d (a ), + .q (b ) + ); + +dffe u_ndffe ( + .clk (clk ), + .en (en), + .d (a ), + .q (b1 ) + ); + +endmodule diff --git a/tests/ecp5/dffs.ys b/tests/ecp5/dffs.ys new file mode 100644 index 000000000..5510bb440 --- /dev/null +++ b/tests/ecp5/dffs.ys @@ -0,0 +1,9 @@ +read_verilog dffs.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 2 t:TRELLIS_FF +select -assert-none t:TRELLIS_FF %% t:* %D diff --git a/tests/ecp5/div_mod.v b/tests/ecp5/div_mod.v new file mode 100644 index 000000000..64a36707d --- /dev/null +++ b/tests/ecp5/div_mod.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x % y; +assign B = x / y; + +endmodule diff --git a/tests/ecp5/div_mod.ys b/tests/ecp5/div_mod.ys new file mode 100644 index 000000000..fb13be5d5 --- /dev/null +++ b/tests/ecp5/div_mod.ys @@ -0,0 +1,12 @@ +read_verilog div_mod.v +hierarchy -top top +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 28 t:CCU2C +select -assert-count 48 t:L6MUX21 +select -assert-count 194 t:LUT4 +select -assert-count 84 t:PFUMX +select -assert-none t:LUT4 t:CCU2C t:L6MUX21 t:PFUMX %% t:* %D diff --git a/tests/ecp5/dpram.v b/tests/ecp5/dpram.v new file mode 100644 index 000000000..3ea4c1f27 --- /dev/null +++ b/tests/ecp5/dpram.v @@ -0,0 +1,23 @@ +/* +Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72]. +*/ +module top (din, write_en, waddr, wclk, raddr, rclk, dout); +parameter addr_width = 8; +parameter data_width = 8; +input [addr_width-1:0] waddr, raddr; +input [data_width-1:0] din; +input write_en, wclk, rclk; +output [data_width-1:0] dout; +reg [data_width-1:0] dout; +reg [data_width-1:0] mem [(1< run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/ecp5/shifter.v b/tests/ecp5/shifter.v new file mode 100644 index 000000000..c55632552 --- /dev/null +++ b/tests/ecp5/shifter.v @@ -0,0 +1,22 @@ +module top ( +out, +clk, +in +); + output [7:0] out; + input signed clk, in; + reg signed [7:0] out = 0; + + always @(posedge clk) + begin +`ifndef BUG + out <= out >> 1; + out[7] <= in; +`else + + out <= out << 1; + out[7] <= in; +`endif + end + +endmodule diff --git a/tests/ecp5/shifter.ys b/tests/ecp5/shifter.ys new file mode 100644 index 000000000..47d95d298 --- /dev/null +++ b/tests/ecp5/shifter.ys @@ -0,0 +1,9 @@ +read_verilog shifter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 8 t:SB_DFF +select -assert-none t:SB_DFF %% t:* %D diff --git a/tests/ecp5/tribuf.v b/tests/ecp5/tribuf.v new file mode 100644 index 000000000..870a02584 --- /dev/null +++ b/tests/ecp5/tribuf.v @@ -0,0 +1,23 @@ +module tristate (en, i, o); + input en; + input i; + output o; + + assign o = en ? i : 1'bz; + +endmodule + + +module top ( +input en, +input a, +output b +); + +tristate u_tri ( + .en (en ), + .i (a ), + .o (b ) + ); + +endmodule diff --git a/tests/ecp5/tribuf.ys b/tests/ecp5/tribuf.ys new file mode 100644 index 000000000..f454a0c02 --- /dev/null +++ b/tests/ecp5/tribuf.ys @@ -0,0 +1,9 @@ +read_verilog tribuf.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v -map +/simcells.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D -- cgit v1.2.3 From 55fbc1a355a6139872a176318356ecdb71a35f5d Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Tue, 3 Sep 2019 12:11:12 +0300 Subject: Uncomment sat command in memory.ys test. --- tests/ecp5/memory.ys | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/ecp5/memory.ys b/tests/ecp5/memory.ys index c90f1991e..9cc6bb5be 100644 --- a/tests/ecp5/memory.ys +++ b/tests/ecp5/memory.ys @@ -7,8 +7,7 @@ memory opt -full miter -equiv -flatten -make_assert -make_outputs gold gate miter -#ERROR: Called with -verify and proof did fail! -#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter +sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter design -load postopt cd top -- cgit v1.2.3 From a203c8569cb6fc7093a5d09e4c64d8e545f81e39 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Wed, 4 Sep 2019 12:15:52 +0300 Subject: Fix ecp5 tests - remove *_synth.v files and generation in scripts; - change synth_ice40 to synth_ecp5; --- tests/ecp5/alu.ys | 12 +- tests/ecp5/counter.ys | 9 +- tests/ecp5/dpram.ys | 1 - tests/ecp5/dpram_synth.v | 165 ---- tests/ecp5/fsm.ys | 15 +- tests/ecp5/latches.ys | 1 - tests/ecp5/latches_synth.v | 109 --- tests/ecp5/logic.ys | 6 +- tests/ecp5/memory.ys | 1 - tests/ecp5/memory_synth.v | 2121 -------------------------------------------- tests/ecp5/shifter.ys | 7 +- 11 files changed, 26 insertions(+), 2421 deletions(-) delete mode 100644 tests/ecp5/dpram_synth.v delete mode 100644 tests/ecp5/latches_synth.v delete mode 100644 tests/ecp5/memory_synth.v (limited to 'tests') diff --git a/tests/ecp5/alu.ys b/tests/ecp5/alu.ys index bd859efc4..d10cd63b2 100644 --- a/tests/ecp5/alu.ys +++ b/tests/ecp5/alu.ys @@ -2,10 +2,12 @@ read_verilog alu.v hierarchy -top top proc flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 62 t:SB_CARRY -select -assert-count 32 t:SB_DFF -select -assert-count 655 t:SB_LUT4 -select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D +select -assert-count 32 t:CCU2C +select -assert-count 253 t:L6MUX21 +select -assert-count 1150 t:LUT4 +select -assert-count 423 t:PFUMX +select -assert-count 32 t:TRELLIS_FF +select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D diff --git a/tests/ecp5/counter.ys b/tests/ecp5/counter.ys index c65c21622..8ef70778f 100644 --- a/tests/ecp5/counter.ys +++ b/tests/ecp5/counter.ys @@ -2,10 +2,9 @@ read_verilog counter.v hierarchy -top top proc flatten -equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check +equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 6 t:SB_CARRY -select -assert-count 8 t:SB_DFFR -select -assert-count 8 t:SB_LUT4 -select -assert-none t:SB_CARRY t:SB_DFFR t:SB_LUT4 %% t:* %D +select -assert-count 4 t:CCU2C +select -assert-count 8 t:TRELLIS_FF +select -assert-none t:CCU2C t:TRELLIS_FF %% t:* %D diff --git a/tests/ecp5/dpram.ys b/tests/ecp5/dpram.ys index b88eb80dd..786dee134 100644 --- a/tests/ecp5/dpram.ys +++ b/tests/ecp5/dpram.ys @@ -15,4 +15,3 @@ design -load postopt cd top select -assert-count 1 t:DP16KD select -assert-none t:DP16KD %% t:* %D -write_verilog dpram_synth.v diff --git a/tests/ecp5/dpram_synth.v b/tests/ecp5/dpram_synth.v deleted file mode 100644 index 7ae20bbba..000000000 --- a/tests/ecp5/dpram_synth.v +++ /dev/null @@ -1,165 +0,0 @@ -/* Generated by Yosys 0.9+36 (git sha1 7e8f7f4c, gcc 8.3.0-6ubuntu1 -Og -fPIC) */ - -(* dynports = 1 *) -(* top = 1 *) -(* src = "dpram.v:4" *) -module top(din, write_en, waddr, wclk, raddr, rclk, dout); - (* unused_bits = "8" *) - wire [8:0] _0_; - (* src = "dpram.v:8" *) - input [7:0] din; - (* src = "dpram.v:10" *) - output [7:0] dout; - (* src = "dpram.v:7" *) - input [7:0] raddr; - (* src = "dpram.v:9" *) - input rclk; - (* src = "dpram.v:7" *) - input [7:0] waddr; - (* src = "dpram.v:9" *) - input wclk; - (* src = "dpram.v:9" *) - input write_en; - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/brams_map.v:79" *) - DP16KD #( - .CLKAMUX("CLKA"), - .CLKBMUX("CLKB"), - .DATA_WIDTH_A(32'sd9), - .DATA_WIDTH_B(32'sd9), - .GSR("DISABLED"), - .INITVAL_00(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_01(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_02(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_03(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_04(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_05(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_06(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_07(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_08(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_09(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_0A(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_0B(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_0C(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_0D(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_0E(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_0F(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_10(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_11(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_12(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_13(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_14(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_15(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_16(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_17(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_18(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_19(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_1A(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_1B(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_1C(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_1D(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_1E(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_1F(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_20(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_21(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_22(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_23(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_24(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_25(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_26(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_27(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_28(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_29(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_2A(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_2B(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_2C(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_2D(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_2E(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_2F(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_30(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_31(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_32(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_33(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_34(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_35(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_36(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_37(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_38(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_39(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_3A(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_3B(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_3C(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_3D(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_3E(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_3F(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .WRITEMODE_A("READBEFOREWRITE"), - .WRITEMODE_B("READBEFOREWRITE") - ) \mem.0.0.0 ( - .ADA0(1'h0), - .ADA1(1'h0), - .ADA10(waddr[7]), - .ADA11(1'h0), - .ADA12(1'h0), - .ADA13(1'h0), - .ADA2(1'h0), - .ADA3(waddr[0]), - .ADA4(waddr[1]), - .ADA5(waddr[2]), - .ADA6(waddr[3]), - .ADA7(waddr[4]), - .ADA8(waddr[5]), - .ADA9(waddr[6]), - .ADB0(1'h0), - .ADB1(1'h0), - .ADB10(raddr[7]), - .ADB11(1'h0), - .ADB12(1'h0), - .ADB13(1'h0), - .ADB2(1'h0), - .ADB3(raddr[0]), - .ADB4(raddr[1]), - .ADB5(raddr[2]), - .ADB6(raddr[3]), - .ADB7(raddr[4]), - .ADB8(raddr[5]), - .ADB9(raddr[6]), - .CEA(1'h1), - .CEB(1'h1), - .CLKA(wclk), - .CLKB(rclk), - .DIA0(din[0]), - .DIA1(din[1]), - .DIA10(1'h0), - .DIA11(1'h0), - .DIA12(1'h0), - .DIA13(1'h0), - .DIA14(1'h0), - .DIA15(1'h0), - .DIA16(1'h0), - .DIA17(1'h0), - .DIA2(din[2]), - .DIA3(din[3]), - .DIA4(din[4]), - .DIA5(din[5]), - .DIA6(din[6]), - .DIA7(din[7]), - .DIA8(1'h0), - .DIA9(1'h0), - .DOB0(dout[0]), - .DOB1(dout[1]), - .DOB2(dout[2]), - .DOB3(dout[3]), - .DOB4(dout[4]), - .DOB5(dout[5]), - .DOB6(dout[6]), - .DOB7(dout[7]), - .DOB8(_0_[8]), - .OCEA(1'h1), - .OCEB(1'h1), - .RSTA(1'h0), - .RSTB(1'h0), - .WEA(write_en), - .WEB(1'h0) - ); - assign _0_[7:0] = dout; -endmodule diff --git a/tests/ecp5/fsm.ys b/tests/ecp5/fsm.ys index 4cc8629d6..bdd910163 100644 --- a/tests/ecp5/fsm.ys +++ b/tests/ecp5/fsm.ys @@ -2,12 +2,13 @@ read_verilog fsm.v hierarchy -top top proc flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'. +#equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module - -select -assert-count 2 t:SB_DFFESR -select -assert-count 2 t:SB_DFFSR -select -assert-count 1 t:SB_DFFSS -select -assert-count 13 t:SB_LUT4 -select -assert-none t:SB_DFFESR t:SB_DFFSR t:SB_DFFSS t:SB_LUT4 %% t:* %D +select -assert-count 1 t:L6MUX21 +select -assert-count 15 t:LUT4 +select -assert-count 6 t:PFUMX +select -assert-count 6 t:TRELLIS_FF +select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D diff --git a/tests/ecp5/latches.ys b/tests/ecp5/latches.ys index 6eaf77cfd..b9d8faf87 100644 --- a/tests/ecp5/latches.ys +++ b/tests/ecp5/latches.ys @@ -14,4 +14,3 @@ cd top select -assert-count 4 t:LUT4 select -assert-count 1 t:PFUMX select -assert-none t:LUT4 t:PFUMX %% t:* %D -write_verilog latches_synth.v diff --git a/tests/ecp5/latches_synth.v b/tests/ecp5/latches_synth.v deleted file mode 100644 index 816e10d4d..000000000 --- a/tests/ecp5/latches_synth.v +++ /dev/null @@ -1,109 +0,0 @@ -/* Generated by Yosys 0.9+36 (git sha1 7e8f7f4c, gcc 8.3.0-6ubuntu1 -Og -fPIC) */ - -(* top = 1 *) -(* src = "latches.v:27" *) -module top(clk, clr, pre, a, b, b1, b2); - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:105" *) - wire _0_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:105" *) - wire _1_; - (* src = "latches.v:31" *) - input a; - (* src = "latches.v:32" *) - output b; - (* src = "latches.v:32" *) - output b1; - (* src = "latches.v:32" *) - output b2; - (* src = "latches.v:28" *) - input clk; - (* src = "latches.v:29" *) - input clr; - (* src = "latches.v:30" *) - input pre; - (* src = "latches.v:43|latches.v:9" *) - wire \u_latchn.d ; - (* src = "latches.v:43|latches.v:9" *) - wire \u_latchn.en ; - (* src = "latches.v:43|latches.v:9" *) - wire \u_latchn.q ; - (* src = "latches.v:36|latches.v:2" *) - wire \u_latchp.d ; - (* src = "latches.v:36|latches.v:2" *) - wire \u_latchp.en ; - (* src = "latches.v:36|latches.v:2" *) - wire \u_latchp.q ; - (* src = "latches.v:50|latches.v:16" *) - wire \u_latchsr.clr ; - (* src = "latches.v:50|latches.v:16" *) - wire \u_latchsr.d ; - (* src = "latches.v:50|latches.v:16" *) - wire \u_latchsr.en ; - (* src = "latches.v:50|latches.v:16" *) - wire \u_latchsr.pre ; - (* src = "latches.v:50|latches.v:16" *) - wire \u_latchsr.q ; - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:106" *) - LUT4 #( - .INIT(16'h5150) - ) _2_ ( - .A(clr), - .B(clk), - .C(pre), - .D(b2), - .Z(_0_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:108" *) - LUT4 #( - .INIT(16'h5554) - ) _3_ ( - .A(clr), - .B(clk), - .C(pre), - .D(b2), - .Z(_1_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:110" *) - PFUMX _4_ ( - .ALUT(_1_), - .BLUT(_0_), - .C0(a), - .Z(b2) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *) - LUT4 #( - .INIT(16'bx1x1x1x0x0x1x0x0) - ) _5_ ( - .A(1'h0), - .B(clk), - .C(b), - .D(a), - .Z(b) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *) - LUT4 #( - .INIT(16'bx1x1x0x1x1x0x0x0) - ) _6_ ( - .A(1'h0), - .B(clk), - .C(b1), - .D(a), - .Z(b1) - ); - assign \u_latchn.d = a; - assign \u_latchn.en = clk; - assign \u_latchn.q = b1; - assign \u_latchp.d = a; - assign \u_latchp.en = clk; - assign \u_latchp.q = b; - assign \u_latchsr.clr = clr; - assign \u_latchsr.d = a; - assign \u_latchsr.en = clk; - assign \u_latchsr.pre = pre; - assign \u_latchsr.q = b2; -endmodule diff --git a/tests/ecp5/logic.ys b/tests/ecp5/logic.ys index fc5e5b1d8..34125fea9 100644 --- a/tests/ecp5/logic.ys +++ b/tests/ecp5/logic.ys @@ -1,7 +1,7 @@ read_verilog logic.v hierarchy -top top -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 9 t:SB_LUT4 -select -assert-none t:SB_LUT4 %% t:* %D +select -assert-count 9 t:LUT4 +select -assert-none t:LUT4 %% t:* %D diff --git a/tests/ecp5/memory.ys b/tests/ecp5/memory.ys index 9cc6bb5be..9b475f122 100644 --- a/tests/ecp5/memory.ys +++ b/tests/ecp5/memory.ys @@ -17,4 +17,3 @@ select -assert-count 32 t:PFUMX select -assert-count 8 t:TRELLIS_DPR16X4 select -assert-count 35 t:TRELLIS_FF select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D -write_verilog memory_synth.v diff --git a/tests/ecp5/memory_synth.v b/tests/ecp5/memory_synth.v deleted file mode 100644 index a6172de61..000000000 --- a/tests/ecp5/memory_synth.v +++ /dev/null @@ -1,2121 +0,0 @@ -/* Generated by Yosys 0.9+36 (git sha1 7e8f7f4c, gcc 8.3.0-6ubuntu1 -Og -fPIC) */ - -(* top = 1 *) -(* src = "memory.v:1" *) -module top(data_a, addr_a, we_a, clk, q_a); - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _000_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _001_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _002_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _003_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _004_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _005_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _006_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _007_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _008_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _009_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _010_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _011_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _012_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _013_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _014_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _015_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _016_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _017_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _018_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _019_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _020_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _021_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _022_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _023_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _024_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _025_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _026_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _027_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _028_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _029_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _030_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _031_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _032_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _033_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _034_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _035_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _036_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _037_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _038_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _039_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _040_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _041_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _042_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _043_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _044_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _045_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _046_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _047_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _048_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _049_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _050_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _051_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _052_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _053_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _054_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _055_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _056_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _057_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _058_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _059_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _060_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _061_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _062_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _063_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _064_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _065_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _066_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _067_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _068_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _069_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _070_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _071_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _072_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _073_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _074_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _075_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _076_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _077_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _078_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _079_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _080_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _081_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _082_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _083_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _084_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _085_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _086_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _087_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _088_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _089_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _090_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _091_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _092_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _093_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _094_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _095_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _096_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _097_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _098_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _099_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _100_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _101_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _102_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _103_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _104_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _105_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _106_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _107_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _108_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _109_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _110_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _111_; - wire _112_; - wire _113_; - wire _114_; - wire _115_; - wire _116_; - wire _117_; - wire _118_; - wire _119_; - wire _120_; - wire _121_; - wire _122_; - wire _123_; - wire _124_; - wire _125_; - wire _126_; - wire _127_; - wire _128_; - wire _129_; - wire _130_; - wire _131_; - wire _132_; - wire _133_; - wire _134_; - wire _135_; - wire _136_; - wire _137_; - wire _138_; - wire _139_; - wire _140_; - wire _141_; - wire _142_; - wire _143_; - wire _144_; - wire _145_; - wire _146_; - wire _147_; - wire _148_; - wire _149_; - wire _150_; - wire _151_; - wire _152_; - wire _153_; - wire [3:0] _154_; - wire [3:0] _155_; - wire [3:0] _156_; - wire [3:0] _157_; - wire [3:0] _158_; - wire [3:0] _159_; - wire [3:0] _160_; - wire [3:0] _161_; - (* src = "memory.v:4" *) - input [6:1] addr_a; - (* src = "memory.v:5" *) - input clk; - (* src = "memory.v:3" *) - input [7:0] data_a; - (* src = "memory.v:6" *) - output [7:0] q_a; - (* src = "memory.v:5" *) - input we_a; - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:92" *) - LUT4 #( - .INIT(16'bxxx0xxx0xxx0xxx1) - ) _162_ ( - .A(1'h0), - .B(1'h0), - .C(addr_a[5]), - .D(addr_a[6]), - .Z(_147_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:92" *) - LUT4 #( - .INIT(16'bxxx0xxx0xxx1xxx0) - ) _163_ ( - .A(1'h0), - .B(1'h0), - .C(addr_a[5]), - .D(addr_a[6]), - .Z(_148_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:92" *) - LUT4 #( - .INIT(16'bxxx0xxx0xxx1xxx0) - ) _164_ ( - .A(1'h0), - .B(1'h0), - .C(addr_a[6]), - .D(addr_a[5]), - .Z(_149_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *) - LUT4 #( - .INIT(16'bx1x0x0x0x0x0x0x0) - ) _165_ ( - .A(1'h0), - .B(we_a), - .C(addr_a[5]), - .D(addr_a[6]), - .Z(_153_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *) - LUT4 #( - .INIT(16'bx0x0x0x0x0x0x1x0) - ) _166_ ( - .A(1'h0), - .B(we_a), - .C(addr_a[5]), - .D(addr_a[6]), - .Z(_150_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *) - LUT4 #( - .INIT(16'bx0x0x0x0x1x0x0x0) - ) _167_ ( - .A(1'h0), - .B(we_a), - .C(addr_a[5]), - .D(addr_a[6]), - .Z(_151_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *) - LUT4 #( - .INIT(16'bx0x0x0x0x1x0x0x0) - ) _168_ ( - .A(1'h0), - .B(we_a), - .C(addr_a[6]), - .D(addr_a[5]), - .Z(_152_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) - LUT4 #( - .INIT(16'hf000) - ) _169_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_136_), - .Z(_000_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) - LUT4 #( - .INIT(16'hfccc) - ) _170_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_136_), - .Z(_001_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) - LUT4 #( - .INIT(16'hfaaa) - ) _171_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_136_), - .Z(_002_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) - LUT4 #( - .INIT(16'hfeee) - ) _172_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_136_), - .Z(_003_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) - LUT4 #( - .INIT(16'hf101) - ) _173_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_136_), - .Z(_004_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) - LUT4 #( - .INIT(16'hfdcd) - ) _174_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_136_), - .Z(_005_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) - LUT4 #( - .INIT(16'hfbab) - ) _175_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_136_), - .Z(_006_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) - LUT4 #( - .INIT(16'hffef) - ) _176_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_136_), - .Z(_007_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) - PFUMX _177_ ( - .ALUT(_001_), - .BLUT(_000_), - .C0(_132_), - .Z(_008_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) - PFUMX _178_ ( - .ALUT(_003_), - .BLUT(_002_), - .C0(_132_), - .Z(_009_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) - PFUMX _179_ ( - .ALUT(_005_), - .BLUT(_004_), - .C0(_132_), - .Z(_010_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) - PFUMX _180_ ( - .ALUT(_007_), - .BLUT(_006_), - .C0(_132_), - .Z(_011_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) - L6MUX21 _181_ ( - .D0(_008_), - .D1(_009_), - .SD(_128_), - .Z(_012_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) - L6MUX21 _182_ ( - .D0(_010_), - .D1(_011_), - .SD(_128_), - .Z(_013_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) - L6MUX21 _183_ ( - .D0(_012_), - .D1(_013_), - .SD(_140_), - .Z(q_a[4]) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) - LUT4 #( - .INIT(16'hf000) - ) _184_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_137_), - .Z(_014_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) - LUT4 #( - .INIT(16'hfccc) - ) _185_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_137_), - .Z(_015_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) - LUT4 #( - .INIT(16'hfaaa) - ) _186_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_137_), - .Z(_016_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) - LUT4 #( - .INIT(16'hfeee) - ) _187_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_137_), - .Z(_017_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) - LUT4 #( - .INIT(16'hf101) - ) _188_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_137_), - .Z(_018_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) - LUT4 #( - .INIT(16'hfdcd) - ) _189_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_137_), - .Z(_019_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) - LUT4 #( - .INIT(16'hfbab) - ) _190_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_137_), - .Z(_020_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) - LUT4 #( - .INIT(16'hffef) - ) _191_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_137_), - .Z(_021_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) - PFUMX _192_ ( - .ALUT(_015_), - .BLUT(_014_), - .C0(_133_), - .Z(_022_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) - PFUMX _193_ ( - .ALUT(_017_), - .BLUT(_016_), - .C0(_133_), - .Z(_023_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) - PFUMX _194_ ( - .ALUT(_019_), - .BLUT(_018_), - .C0(_133_), - .Z(_024_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) - PFUMX _195_ ( - .ALUT(_021_), - .BLUT(_020_), - .C0(_133_), - .Z(_025_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) - L6MUX21 _196_ ( - .D0(_022_), - .D1(_023_), - .SD(_129_), - .Z(_026_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) - L6MUX21 _197_ ( - .D0(_024_), - .D1(_025_), - .SD(_129_), - .Z(_027_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) - L6MUX21 _198_ ( - .D0(_026_), - .D1(_027_), - .SD(_141_), - .Z(q_a[5]) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) - LUT4 #( - .INIT(16'hf000) - ) _199_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_138_), - .Z(_028_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) - LUT4 #( - .INIT(16'hfccc) - ) _200_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_138_), - .Z(_029_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) - LUT4 #( - .INIT(16'hfaaa) - ) _201_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_138_), - .Z(_030_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) - LUT4 #( - .INIT(16'hfeee) - ) _202_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_138_), - .Z(_031_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) - LUT4 #( - .INIT(16'hf101) - ) _203_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_138_), - .Z(_032_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) - LUT4 #( - .INIT(16'hfdcd) - ) _204_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_138_), - .Z(_033_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) - LUT4 #( - .INIT(16'hfbab) - ) _205_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_138_), - .Z(_034_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) - LUT4 #( - .INIT(16'hffef) - ) _206_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_138_), - .Z(_035_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) - PFUMX _207_ ( - .ALUT(_029_), - .BLUT(_028_), - .C0(_134_), - .Z(_036_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) - PFUMX _208_ ( - .ALUT(_031_), - .BLUT(_030_), - .C0(_134_), - .Z(_037_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) - PFUMX _209_ ( - .ALUT(_033_), - .BLUT(_032_), - .C0(_134_), - .Z(_038_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) - PFUMX _210_ ( - .ALUT(_035_), - .BLUT(_034_), - .C0(_134_), - .Z(_039_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) - L6MUX21 _211_ ( - .D0(_036_), - .D1(_037_), - .SD(_130_), - .Z(_040_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) - L6MUX21 _212_ ( - .D0(_038_), - .D1(_039_), - .SD(_130_), - .Z(_041_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) - L6MUX21 _213_ ( - .D0(_040_), - .D1(_041_), - .SD(_142_), - .Z(q_a[6]) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) - LUT4 #( - .INIT(16'hf000) - ) _214_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_139_), - .Z(_042_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) - LUT4 #( - .INIT(16'hfccc) - ) _215_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_139_), - .Z(_043_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) - LUT4 #( - .INIT(16'hfaaa) - ) _216_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_139_), - .Z(_044_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) - LUT4 #( - .INIT(16'hfeee) - ) _217_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_139_), - .Z(_045_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) - LUT4 #( - .INIT(16'hf101) - ) _218_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_139_), - .Z(_046_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) - LUT4 #( - .INIT(16'hfdcd) - ) _219_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_139_), - .Z(_047_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) - LUT4 #( - .INIT(16'hfbab) - ) _220_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_139_), - .Z(_048_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) - LUT4 #( - .INIT(16'hffef) - ) _221_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_139_), - .Z(_049_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) - PFUMX _222_ ( - .ALUT(_043_), - .BLUT(_042_), - .C0(_135_), - .Z(_050_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) - PFUMX _223_ ( - .ALUT(_045_), - .BLUT(_044_), - .C0(_135_), - .Z(_051_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) - PFUMX _224_ ( - .ALUT(_047_), - .BLUT(_046_), - .C0(_135_), - .Z(_052_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) - PFUMX _225_ ( - .ALUT(_049_), - .BLUT(_048_), - .C0(_135_), - .Z(_053_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) - L6MUX21 _226_ ( - .D0(_050_), - .D1(_051_), - .SD(_131_), - .Z(_054_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) - L6MUX21 _227_ ( - .D0(_052_), - .D1(_053_), - .SD(_131_), - .Z(_055_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) - L6MUX21 _228_ ( - .D0(_054_), - .D1(_055_), - .SD(_143_), - .Z(q_a[7]) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) - LUT4 #( - .INIT(16'hf000) - ) _229_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_120_), - .Z(_056_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) - LUT4 #( - .INIT(16'hfccc) - ) _230_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_120_), - .Z(_057_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) - LUT4 #( - .INIT(16'hfaaa) - ) _231_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_120_), - .Z(_058_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) - LUT4 #( - .INIT(16'hfeee) - ) _232_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_120_), - .Z(_059_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) - LUT4 #( - .INIT(16'hf101) - ) _233_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_120_), - .Z(_060_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) - LUT4 #( - .INIT(16'hfdcd) - ) _234_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_120_), - .Z(_061_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) - LUT4 #( - .INIT(16'hfbab) - ) _235_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_120_), - .Z(_062_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) - LUT4 #( - .INIT(16'hffef) - ) _236_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_120_), - .Z(_063_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) - PFUMX _237_ ( - .ALUT(_057_), - .BLUT(_056_), - .C0(_116_), - .Z(_064_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) - PFUMX _238_ ( - .ALUT(_059_), - .BLUT(_058_), - .C0(_116_), - .Z(_065_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) - PFUMX _239_ ( - .ALUT(_061_), - .BLUT(_060_), - .C0(_116_), - .Z(_066_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) - PFUMX _240_ ( - .ALUT(_063_), - .BLUT(_062_), - .C0(_116_), - .Z(_067_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) - L6MUX21 _241_ ( - .D0(_064_), - .D1(_065_), - .SD(_112_), - .Z(_068_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) - L6MUX21 _242_ ( - .D0(_066_), - .D1(_067_), - .SD(_112_), - .Z(_069_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) - L6MUX21 _243_ ( - .D0(_068_), - .D1(_069_), - .SD(_124_), - .Z(q_a[0]) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) - LUT4 #( - .INIT(16'hf000) - ) _244_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_121_), - .Z(_070_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) - LUT4 #( - .INIT(16'hfccc) - ) _245_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_121_), - .Z(_071_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) - LUT4 #( - .INIT(16'hfaaa) - ) _246_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_121_), - .Z(_072_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) - LUT4 #( - .INIT(16'hfeee) - ) _247_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_121_), - .Z(_073_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) - LUT4 #( - .INIT(16'hf101) - ) _248_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_121_), - .Z(_074_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) - LUT4 #( - .INIT(16'hfdcd) - ) _249_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_121_), - .Z(_075_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) - LUT4 #( - .INIT(16'hfbab) - ) _250_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_121_), - .Z(_076_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) - LUT4 #( - .INIT(16'hffef) - ) _251_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_121_), - .Z(_077_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) - PFUMX _252_ ( - .ALUT(_071_), - .BLUT(_070_), - .C0(_117_), - .Z(_078_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) - PFUMX _253_ ( - .ALUT(_073_), - .BLUT(_072_), - .C0(_117_), - .Z(_079_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) - PFUMX _254_ ( - .ALUT(_075_), - .BLUT(_074_), - .C0(_117_), - .Z(_080_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) - PFUMX _255_ ( - .ALUT(_077_), - .BLUT(_076_), - .C0(_117_), - .Z(_081_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) - L6MUX21 _256_ ( - .D0(_078_), - .D1(_079_), - .SD(_113_), - .Z(_082_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) - L6MUX21 _257_ ( - .D0(_080_), - .D1(_081_), - .SD(_113_), - .Z(_083_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) - L6MUX21 _258_ ( - .D0(_082_), - .D1(_083_), - .SD(_125_), - .Z(q_a[1]) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) - LUT4 #( - .INIT(16'hf000) - ) _259_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_122_), - .Z(_084_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) - LUT4 #( - .INIT(16'hfccc) - ) _260_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_122_), - .Z(_085_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) - LUT4 #( - .INIT(16'hfaaa) - ) _261_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_122_), - .Z(_086_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) - LUT4 #( - .INIT(16'hfeee) - ) _262_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_122_), - .Z(_087_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) - LUT4 #( - .INIT(16'hf101) - ) _263_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_122_), - .Z(_088_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) - LUT4 #( - .INIT(16'hfdcd) - ) _264_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_122_), - .Z(_089_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) - LUT4 #( - .INIT(16'hfbab) - ) _265_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_122_), - .Z(_090_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) - LUT4 #( - .INIT(16'hffef) - ) _266_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_122_), - .Z(_091_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) - PFUMX _267_ ( - .ALUT(_085_), - .BLUT(_084_), - .C0(_118_), - .Z(_092_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) - PFUMX _268_ ( - .ALUT(_087_), - .BLUT(_086_), - .C0(_118_), - .Z(_093_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) - PFUMX _269_ ( - .ALUT(_089_), - .BLUT(_088_), - .C0(_118_), - .Z(_094_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) - PFUMX _270_ ( - .ALUT(_091_), - .BLUT(_090_), - .C0(_118_), - .Z(_095_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) - L6MUX21 _271_ ( - .D0(_092_), - .D1(_093_), - .SD(_114_), - .Z(_096_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) - L6MUX21 _272_ ( - .D0(_094_), - .D1(_095_), - .SD(_114_), - .Z(_097_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) - L6MUX21 _273_ ( - .D0(_096_), - .D1(_097_), - .SD(_126_), - .Z(q_a[2]) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) - LUT4 #( - .INIT(16'hf000) - ) _274_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_123_), - .Z(_098_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) - LUT4 #( - .INIT(16'hfccc) - ) _275_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_123_), - .Z(_099_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) - LUT4 #( - .INIT(16'hfaaa) - ) _276_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_123_), - .Z(_100_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) - LUT4 #( - .INIT(16'hfeee) - ) _277_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_123_), - .Z(_101_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) - LUT4 #( - .INIT(16'hf101) - ) _278_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_123_), - .Z(_102_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) - LUT4 #( - .INIT(16'hfdcd) - ) _279_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_123_), - .Z(_103_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) - LUT4 #( - .INIT(16'hfbab) - ) _280_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_123_), - .Z(_104_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) - LUT4 #( - .INIT(16'hffef) - ) _281_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_123_), - .Z(_105_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) - PFUMX _282_ ( - .ALUT(_099_), - .BLUT(_098_), - .C0(_119_), - .Z(_106_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) - PFUMX _283_ ( - .ALUT(_101_), - .BLUT(_100_), - .C0(_119_), - .Z(_107_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) - PFUMX _284_ ( - .ALUT(_103_), - .BLUT(_102_), - .C0(_119_), - .Z(_108_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) - PFUMX _285_ ( - .ALUT(_105_), - .BLUT(_104_), - .C0(_119_), - .Z(_109_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) - L6MUX21 _286_ ( - .D0(_106_), - .D1(_107_), - .SD(_115_), - .Z(_110_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) - L6MUX21 _287_ ( - .D0(_108_), - .D1(_109_), - .SD(_115_), - .Z(_111_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) - L6MUX21 _288_ ( - .D0(_110_), - .D1(_111_), - .SD(_127_), - .Z(q_a[3]) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _289_ ( - .CLK(clk), - .DI(_147_), - .LSR(1'h0), - .Q(_144_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _290_ ( - .CLK(clk), - .DI(_154_[0]), - .LSR(1'h0), - .Q(_112_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _291_ ( - .CLK(clk), - .DI(_154_[1]), - .LSR(1'h0), - .Q(_113_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _292_ ( - .CLK(clk), - .DI(_154_[2]), - .LSR(1'h0), - .Q(_114_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _293_ ( - .CLK(clk), - .DI(_154_[3]), - .LSR(1'h0), - .Q(_115_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _294_ ( - .CLK(clk), - .DI(_155_[0]), - .LSR(1'h0), - .Q(_116_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _295_ ( - .CLK(clk), - .DI(_155_[1]), - .LSR(1'h0), - .Q(_117_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _296_ ( - .CLK(clk), - .DI(_155_[2]), - .LSR(1'h0), - .Q(_118_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _297_ ( - .CLK(clk), - .DI(_155_[3]), - .LSR(1'h0), - .Q(_119_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _298_ ( - .CLK(clk), - .DI(_156_[0]), - .LSR(1'h0), - .Q(_120_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _299_ ( - .CLK(clk), - .DI(_156_[1]), - .LSR(1'h0), - .Q(_121_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _300_ ( - .CLK(clk), - .DI(_156_[2]), - .LSR(1'h0), - .Q(_122_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _301_ ( - .CLK(clk), - .DI(_156_[3]), - .LSR(1'h0), - .Q(_123_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _302_ ( - .CLK(clk), - .DI(_149_), - .LSR(1'h0), - .Q(_146_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _303_ ( - .CLK(clk), - .DI(_157_[0]), - .LSR(1'h0), - .Q(_124_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _304_ ( - .CLK(clk), - .DI(_157_[1]), - .LSR(1'h0), - .Q(_125_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _305_ ( - .CLK(clk), - .DI(_157_[2]), - .LSR(1'h0), - .Q(_126_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _306_ ( - .CLK(clk), - .DI(_157_[3]), - .LSR(1'h0), - .Q(_127_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _307_ ( - .CLK(clk), - .DI(_158_[0]), - .LSR(1'h0), - .Q(_128_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _308_ ( - .CLK(clk), - .DI(_158_[1]), - .LSR(1'h0), - .Q(_129_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _309_ ( - .CLK(clk), - .DI(_158_[2]), - .LSR(1'h0), - .Q(_130_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _310_ ( - .CLK(clk), - .DI(_158_[3]), - .LSR(1'h0), - .Q(_131_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _311_ ( - .CLK(clk), - .DI(_159_[0]), - .LSR(1'h0), - .Q(_132_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _312_ ( - .CLK(clk), - .DI(_159_[1]), - .LSR(1'h0), - .Q(_133_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _313_ ( - .CLK(clk), - .DI(_159_[2]), - .LSR(1'h0), - .Q(_134_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _314_ ( - .CLK(clk), - .DI(_159_[3]), - .LSR(1'h0), - .Q(_135_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _315_ ( - .CLK(clk), - .DI(_148_), - .LSR(1'h0), - .Q(_145_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _316_ ( - .CLK(clk), - .DI(_160_[0]), - .LSR(1'h0), - .Q(_136_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _317_ ( - .CLK(clk), - .DI(_160_[1]), - .LSR(1'h0), - .Q(_137_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _318_ ( - .CLK(clk), - .DI(_160_[2]), - .LSR(1'h0), - .Q(_138_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _319_ ( - .CLK(clk), - .DI(_160_[3]), - .LSR(1'h0), - .Q(_139_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _320_ ( - .CLK(clk), - .DI(_161_[0]), - .LSR(1'h0), - .Q(_140_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _321_ ( - .CLK(clk), - .DI(_161_[1]), - .LSR(1'h0), - .Q(_141_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _322_ ( - .CLK(clk), - .DI(_161_[2]), - .LSR(1'h0), - .Q(_142_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _323_ ( - .CLK(clk), - .DI(_161_[3]), - .LSR(1'h0), - .Q(_143_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) - TRELLIS_DPR16X4 #( - .INITVAL(64'hxxxxxxxxxxxxxxxx), - .WCKMUX("WCK"), - .WREMUX("WRE") - ) \ram.0.0.0 ( - .DI(data_a[3:0]), - .DO(_154_), - .RAD(addr_a[4:1]), - .WAD(addr_a[4:1]), - .WCK(clk), - .WRE(_150_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) - TRELLIS_DPR16X4 #( - .INITVAL(64'hxxxxxxxxxxxxxxxx), - .WCKMUX("WCK"), - .WREMUX("WRE") - ) \ram.0.1.0 ( - .DI(data_a[3:0]), - .DO(_155_), - .RAD(addr_a[4:1]), - .WAD(addr_a[4:1]), - .WCK(clk), - .WRE(_151_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) - TRELLIS_DPR16X4 #( - .INITVAL(64'hxxxxxxxxxxxxxxxx), - .WCKMUX("WCK"), - .WREMUX("WRE") - ) \ram.0.2.0 ( - .DI(data_a[3:0]), - .DO(_156_), - .RAD(addr_a[4:1]), - .WAD(addr_a[4:1]), - .WCK(clk), - .WRE(_152_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) - TRELLIS_DPR16X4 #( - .INITVAL(64'hxxxxxxxxxxxxxxxx), - .WCKMUX("WCK"), - .WREMUX("WRE") - ) \ram.0.3.0 ( - .DI(data_a[3:0]), - .DO(_157_), - .RAD(addr_a[4:1]), - .WAD(addr_a[4:1]), - .WCK(clk), - .WRE(_153_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) - TRELLIS_DPR16X4 #( - .INITVAL(64'hxxxxxxxxxxxxxxxx), - .WCKMUX("WCK"), - .WREMUX("WRE") - ) \ram.1.0.0 ( - .DI(data_a[7:4]), - .DO(_158_), - .RAD(addr_a[4:1]), - .WAD(addr_a[4:1]), - .WCK(clk), - .WRE(_150_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) - TRELLIS_DPR16X4 #( - .INITVAL(64'hxxxxxxxxxxxxxxxx), - .WCKMUX("WCK"), - .WREMUX("WRE") - ) \ram.1.1.0 ( - .DI(data_a[7:4]), - .DO(_159_), - .RAD(addr_a[4:1]), - .WAD(addr_a[4:1]), - .WCK(clk), - .WRE(_151_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) - TRELLIS_DPR16X4 #( - .INITVAL(64'hxxxxxxxxxxxxxxxx), - .WCKMUX("WCK"), - .WREMUX("WRE") - ) \ram.1.2.0 ( - .DI(data_a[7:4]), - .DO(_160_), - .RAD(addr_a[4:1]), - .WAD(addr_a[4:1]), - .WCK(clk), - .WRE(_152_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) - TRELLIS_DPR16X4 #( - .INITVAL(64'hxxxxxxxxxxxxxxxx), - .WCKMUX("WCK"), - .WREMUX("WRE") - ) \ram.1.3.0 ( - .DI(data_a[7:4]), - .DO(_161_), - .RAD(addr_a[4:1]), - .WAD(addr_a[4:1]), - .WCK(clk), - .WRE(_153_) - ); -endmodule diff --git a/tests/ecp5/shifter.ys b/tests/ecp5/shifter.ys index 47d95d298..70fe6c45c 100644 --- a/tests/ecp5/shifter.ys +++ b/tests/ecp5/shifter.ys @@ -2,8 +2,9 @@ read_verilog shifter.v hierarchy -top top proc flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 8 t:SB_DFF -select -assert-none t:SB_DFF %% t:* %D +stat +select -assert-count 8 t:TRELLIS_FF +select -assert-none t:TRELLIS_FF %% t:* %D -- cgit v1.2.3 From 93f305b1c53ce49338bf276a7fb9c3aa4d578c9e Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Wed, 4 Sep 2019 14:57:45 +0300 Subject: Remove stat command form shifter.ys test --- tests/ecp5/shifter.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/ecp5/shifter.ys b/tests/ecp5/shifter.ys index 70fe6c45c..e1901e1a8 100644 --- a/tests/ecp5/shifter.ys +++ b/tests/ecp5/shifter.ys @@ -5,6 +5,6 @@ flatten equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -stat + select -assert-count 8 t:TRELLIS_FF select -assert-none t:TRELLIS_FF %% t:* %D -- cgit v1.2.3 From c597c2f2ae10111b2dc28e9738ea336d8ad22b31 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Tue, 17 Sep 2019 12:19:31 +0300 Subject: adffs test update (equiv_opt -multiclock). div_mod test fix --- tests/ecp5/adffs.v | 18 +++++++----------- tests/ecp5/adffs.ys | 5 ++--- tests/ecp5/div_mod.ys | 6 +++--- 3 files changed, 12 insertions(+), 17 deletions(-) (limited to 'tests') diff --git a/tests/ecp5/adffs.v b/tests/ecp5/adffs.v index 93c8bf52c..05e68caf7 100644 --- a/tests/ecp5/adffs.v +++ b/tests/ecp5/adffs.v @@ -22,30 +22,26 @@ module adffn q <= d; endmodule -module dffsr +module dffs ( input d, clk, pre, clr, output reg q ); initial begin q = 0; end - always @( posedge clk, posedge pre, posedge clr ) - if ( clr ) - q <= 1'b0; - else if ( pre ) + always @( posedge clk ) + if ( pre ) q <= 1'b1; else q <= d; endmodule -module ndffnsnr +module ndffnr ( input d, clk, pre, clr, output reg q ); initial begin q = 0; end - always @( negedge clk, negedge pre, negedge clr ) + always @( negedge clk ) if ( !clr ) q <= 1'b0; - else if ( !pre ) - q <= 1'b1; else q <= d; endmodule @@ -58,7 +54,7 @@ input a, output b,b1,b2,b3 ); -dffsr u_dffsr ( +dffs u_dffs ( .clk (clk ), .clr (clr), .pre (pre), @@ -66,7 +62,7 @@ dffsr u_dffsr ( .q (b ) ); -ndffnsnr u_ndffnsnr ( +ndffnr u_ndffnr ( .clk (clk ), .clr (clr), .pre (pre), diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys index 7ec2b0114..fc1363a32 100644 --- a/tests/ecp5/adffs.ys +++ b/tests/ecp5/adffs.ys @@ -1,10 +1,9 @@ read_verilog adffs.v proc -async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +equiv_opt -multiclock -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 4 t:TRELLIS_FF -select -assert-count 7 t:LUT4 +select -assert-count 3 t:LUT4 select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D diff --git a/tests/ecp5/div_mod.ys b/tests/ecp5/div_mod.ys index fb13be5d5..9efb00701 100644 --- a/tests/ecp5/div_mod.ys +++ b/tests/ecp5/div_mod.ys @@ -6,7 +6,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd top # Constrain all select calls below inside the top module select -assert-count 28 t:CCU2C -select -assert-count 48 t:L6MUX21 -select -assert-count 194 t:LUT4 -select -assert-count 84 t:PFUMX +select -assert-count 26 t:L6MUX21 +select -assert-count 138 t:LUT4 +select -assert-count 60 t:PFUMX select -assert-none t:LUT4 t:CCU2C t:L6MUX21 t:PFUMX %% t:* %D -- cgit v1.2.3 From 5eb91fa69fc62482d09c1927b3a6f8164dee9408 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Wed, 18 Sep 2019 12:16:04 +0300 Subject: Add comment to dpram test about related issue. --- tests/ecp5/dpram.ys | 1 + 1 file changed, 1 insertion(+) (limited to 'tests') diff --git a/tests/ecp5/dpram.ys b/tests/ecp5/dpram.ys index 786dee134..3bc6bc1d0 100644 --- a/tests/ecp5/dpram.ys +++ b/tests/ecp5/dpram.ys @@ -8,6 +8,7 @@ opt -full miter -equiv -flatten -make_assert -make_outputs gold gate miter +#Blocked by issue #1358 (Missing ECP5 simulation models) #ERROR: Failed to import cell gate.mem.0.0.0 (type DP16KD) to SAT database. #sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter -- cgit v1.2.3 From 27377c46634263beb5f8c28cb34b0c87ed6e9525 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Mon, 23 Sep 2019 12:12:02 +0300 Subject: Add new tests for Anlogic architecture Problems/questions: - memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM? - Internal cell type $_TBUF_ is present. --- tests/anlogic/.gitignore | 4 ++ tests/anlogic/add_sub.v | 13 ++++++ tests/anlogic/add_sub.ys | 9 +++++ tests/anlogic/alu.v | 19 +++++++++ tests/anlogic/alu.ys | 17 ++++++++ tests/anlogic/counter.v | 17 ++++++++ tests/anlogic/counter.ys | 11 +++++ tests/anlogic/dffs.v | 37 +++++++++++++++++ tests/anlogic/dffs.ys | 10 +++++ tests/anlogic/fsm.v | 73 +++++++++++++++++++++++++++++++++ tests/anlogic/fsm.ys | 14 +++++++ tests/anlogic/latches.v | 58 +++++++++++++++++++++++++++ tests/anlogic/latches.ys | 16 ++++++++ tests/anlogic/memory.v | 21 ++++++++++ tests/anlogic/memory.ys | 21 ++++++++++ tests/anlogic/mux.v | 100 ++++++++++++++++++++++++++++++++++++++++++++++ tests/anlogic/mux.ys | 12 ++++++ tests/anlogic/run-test.sh | 20 ++++++++++ tests/anlogic/shifter.v | 22 ++++++++++ tests/anlogic/shifter.ys | 9 +++++ tests/anlogic/tribuf.v | 23 +++++++++++ tests/anlogic/tribuf.ys | 9 +++++ 22 files changed, 535 insertions(+) create mode 100644 tests/anlogic/.gitignore create mode 100644 tests/anlogic/add_sub.v create mode 100644 tests/anlogic/add_sub.ys create mode 100644 tests/anlogic/alu.v create mode 100644 tests/anlogic/alu.ys create mode 100644 tests/anlogic/counter.v create mode 100644 tests/anlogic/counter.ys create mode 100644 tests/anlogic/dffs.v create mode 100644 tests/anlogic/dffs.ys create mode 100644 tests/anlogic/fsm.v create mode 100644 tests/anlogic/fsm.ys create mode 100644 tests/anlogic/latches.v create mode 100644 tests/anlogic/latches.ys create mode 100644 tests/anlogic/memory.v create mode 100644 tests/anlogic/memory.ys create mode 100644 tests/anlogic/mux.v create mode 100644 tests/anlogic/mux.ys create mode 100755 tests/anlogic/run-test.sh create mode 100644 tests/anlogic/shifter.v create mode 100644 tests/anlogic/shifter.ys create mode 100644 tests/anlogic/tribuf.v create mode 100644 tests/anlogic/tribuf.ys (limited to 'tests') diff --git a/tests/anlogic/.gitignore b/tests/anlogic/.gitignore new file mode 100644 index 000000000..9a71dca69 --- /dev/null +++ b/tests/anlogic/.gitignore @@ -0,0 +1,4 @@ +*.log +/run-test.mk ++*_synth.v ++*_testbench diff --git a/tests/anlogic/add_sub.v b/tests/anlogic/add_sub.v new file mode 100644 index 000000000..177c32e30 --- /dev/null +++ b/tests/anlogic/add_sub.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x + y; +assign B = x - y; + +endmodule diff --git a/tests/anlogic/add_sub.ys b/tests/anlogic/add_sub.ys new file mode 100644 index 000000000..55c090506 --- /dev/null +++ b/tests/anlogic/add_sub.ys @@ -0,0 +1,9 @@ +read_verilog add_sub.v +hierarchy -top top +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 10 t:AL_MAP_ADDER +select -assert-count 4 t:AL_MAP_LUT1 +select -assert-none t:AL_MAP_LUT1 t:AL_MAP_ADDER %% t:* %D + diff --git a/tests/anlogic/alu.v b/tests/anlogic/alu.v new file mode 100644 index 000000000..f82cc2e21 --- /dev/null +++ b/tests/anlogic/alu.v @@ -0,0 +1,19 @@ +module top ( + input clock, + input [31:0] dinA, dinB, + input [2:0] opcode, + output reg [31:0] dout +); + always @(posedge clock) begin + case (opcode) + 0: dout <= dinA + dinB; + 1: dout <= dinA - dinB; + 2: dout <= dinA >> dinB; + 3: dout <= $signed(dinA) >>> dinB; + 4: dout <= dinA << dinB; + 5: dout <= dinA & dinB; + 6: dout <= dinA | dinB; + 7: dout <= dinA ^ dinB; + endcase + end +endmodule diff --git a/tests/anlogic/alu.ys b/tests/anlogic/alu.ys new file mode 100644 index 000000000..532ce82d5 --- /dev/null +++ b/tests/anlogic/alu.ys @@ -0,0 +1,17 @@ +read_verilog alu.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 66 t:AL_MAP_ADDER +select -assert-count 32 t:AL_MAP_LUT1 +select -assert-count 23 t:AL_MAP_LUT2 +select -assert-count 61 t:AL_MAP_LUT3 +select -assert-count 209 t:AL_MAP_LUT4 +select -assert-count 100 t:AL_MAP_LUT5 +select -assert-count 79 t:AL_MAP_LUT6 +select -assert-count 32 t:AL_MAP_SEQ +select -assert-none t:AL_MAP_ADDER t:AL_MAP_LUT1 t:AL_MAP_LUT2 t:AL_MAP_LUT3 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D diff --git a/tests/anlogic/counter.v b/tests/anlogic/counter.v new file mode 100644 index 000000000..52852f8ac --- /dev/null +++ b/tests/anlogic/counter.v @@ -0,0 +1,17 @@ +module top ( +out, +clk, +reset +); + output [7:0] out; + input clk, reset; + reg [7:0] out; + + always @(posedge clk, posedge reset) + if (reset) begin + out <= 8'b0 ; + end else + out <= out + 1; + + +endmodule diff --git a/tests/anlogic/counter.ys b/tests/anlogic/counter.ys new file mode 100644 index 000000000..5210221e3 --- /dev/null +++ b/tests/anlogic/counter.ys @@ -0,0 +1,11 @@ +read_verilog counter.v +hierarchy -top top +proc +flatten +equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 9 t:AL_MAP_ADDER +select -assert-count 8 t:AL_MAP_SEQ +select -assert-none t:SB_CARRY t:AL_MAP_SEQ t:AL_MAP_ADDER %% t:* %D diff --git a/tests/anlogic/dffs.v b/tests/anlogic/dffs.v new file mode 100644 index 000000000..d97840c43 --- /dev/null +++ b/tests/anlogic/dffs.v @@ -0,0 +1,37 @@ +module dff + ( input d, clk, output reg q ); + always @( posedge clk ) + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule + +module top ( +input clk, +input en, +input a, +output b,b1, +); + +dff u_dff ( + .clk (clk ), + .d (a ), + .q (b ) + ); + +dffe u_ndffe ( + .clk (clk ), + .en (en), + .d (a ), + .q (b1 ) + ); + +endmodule diff --git a/tests/anlogic/dffs.ys b/tests/anlogic/dffs.ys new file mode 100644 index 000000000..a15c6f24e --- /dev/null +++ b/tests/anlogic/dffs.ys @@ -0,0 +1,10 @@ +read_verilog dffs.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT3 +select -assert-count 2 t:AL_MAP_SEQ +select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D diff --git a/tests/anlogic/fsm.v b/tests/anlogic/fsm.v new file mode 100644 index 000000000..0605bd102 --- /dev/null +++ b/tests/anlogic/fsm.v @@ -0,0 +1,73 @@ + module fsm ( + clock, + reset, + req_0, + req_1, + gnt_0, + gnt_1 + ); + input clock,reset,req_0,req_1; + output gnt_0,gnt_1; + wire clock,reset,req_0,req_1; + reg gnt_0,gnt_1; + + parameter SIZE = 3 ; + parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; + + reg [SIZE-1:0] state; + reg [SIZE-1:0] next_state; + + always @ (posedge clock) + begin : FSM + if (reset == 1'b1) begin + state <= #1 IDLE; + gnt_0 <= 0; + gnt_1 <= 0; + end else + case(state) + IDLE : if (req_0 == 1'b1) begin + state <= #1 GNT0; + gnt_0 <= 1; + end else if (req_1 == 1'b1) begin + gnt_1 <= 1; + state <= #1 GNT0; + end else begin + state <= #1 IDLE; + end + GNT0 : if (req_0 == 1'b1) begin + state <= #1 GNT0; + end else begin + gnt_0 <= 0; + state <= #1 IDLE; + end + GNT1 : if (req_1 == 1'b1) begin + state <= #1 GNT2; + gnt_1 <= req_0; + end + GNT2 : if (req_0 == 1'b1) begin + state <= #1 GNT1; + gnt_1 <= req_1; + end + default : state <= #1 IDLE; + endcase + end + + endmodule + + module top ( +input clk, +input rst, +input a, +input b, +output g0, +output g1 +); + +fsm u_fsm ( .clock(clk), + .reset(rst), + .req_0(a), + .req_1(b), + .gnt_0(g0), + .gnt_1(g1)); + +endmodule diff --git a/tests/anlogic/fsm.ys b/tests/anlogic/fsm.ys new file mode 100644 index 000000000..6eb7b9a71 --- /dev/null +++ b/tests/anlogic/fsm.ys @@ -0,0 +1,14 @@ +read_verilog fsm.v +hierarchy -top top +proc +flatten +#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'. +#equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT2 +select -assert-count 5 t:AL_MAP_LUT5 +select -assert-count 1 t:AL_MAP_LUT6 +select -assert-count 6 t:AL_MAP_SEQ +select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D diff --git a/tests/anlogic/latches.v b/tests/anlogic/latches.v new file mode 100644 index 000000000..9dc43e4c2 --- /dev/null +++ b/tests/anlogic/latches.v @@ -0,0 +1,58 @@ +module latchp + ( input d, clk, en, output reg q ); + always @* + if ( en ) + q <= d; +endmodule + +module latchn + ( input d, clk, en, output reg q ); + always @* + if ( !en ) + q <= d; +endmodule + +module latchsr + ( input d, clk, en, clr, pre, output reg q ); + always @* + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else if ( en ) + q <= d; +endmodule + + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2 +); + + +latchp u_latchp ( + .en (clk ), + .d (a ), + .q (b ) + ); + + +latchn u_latchn ( + .en (clk ), + .d (a ), + .q (b1 ) + ); + + +latchsr u_latchsr ( + .en (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b2 ) + ); + +endmodule diff --git a/tests/anlogic/latches.ys b/tests/anlogic/latches.ys new file mode 100644 index 000000000..b5e52cf16 --- /dev/null +++ b/tests/anlogic/latches.ys @@ -0,0 +1,16 @@ +read_verilog latches.v +design -save read + +proc +async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock +flatten +synth_anlogic +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) + +design -load read +synth_anlogic +cd top +select -assert-count 2 t:AL_MAP_LUT3 +select -assert-count 1 t:AL_MAP_LUT5 +select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT5 %% t:* %D diff --git a/tests/anlogic/memory.v b/tests/anlogic/memory.v new file mode 100644 index 000000000..cb7753f7b --- /dev/null +++ b/tests/anlogic/memory.v @@ -0,0 +1,21 @@ +module top +( + input [7:0] data_a, + input [6:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end +endmodule diff --git a/tests/anlogic/memory.ys b/tests/anlogic/memory.ys new file mode 100644 index 000000000..8c0ce844e --- /dev/null +++ b/tests/anlogic/memory.ys @@ -0,0 +1,21 @@ +read_verilog memory.v +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. +#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd top + +select -assert-count 8 t:AL_MAP_LUT2 +select -assert-count 8 t:AL_MAP_LUT4 +select -assert-count 8 t:AL_MAP_LUT5 +select -assert-count 36 t:AL_MAP_SEQ +select -assert-count 8 t:EG_LOGIC_DRAM16X4 #Why not AL_LOGIC_BRAM? +select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_SEQ t:EG_LOGIC_DRAM16X4 %% t:* %D diff --git a/tests/anlogic/mux.v b/tests/anlogic/mux.v new file mode 100644 index 000000000..0814b733e --- /dev/null +++ b/tests/anlogic/mux.v @@ -0,0 +1,100 @@ +module mux2 (S,A,B,Y); + input S; + input A,B; + output reg Y; + + always @(*) + Y = (S)? B : A; +endmodule + +module mux4 ( S, D, Y ); + +input[1:0] S; +input[3:0] D; +output Y; + +reg Y; +wire[1:0] S; +wire[3:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + endcase +end + +endmodule + +module mux8 ( S, D, Y ); + +input[2:0] S; +input[7:0] D; +output Y; + +reg Y; +wire[2:0] S; +wire[7:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + 4 : Y = D[4]; + 5 : Y = D[5]; + 6 : Y = D[6]; + 7 : Y = D[7]; + endcase +end + +endmodule + +module mux16 (D, S, Y); + input [15:0] D; + input [3:0] S; + output Y; + +assign Y = D[S]; + +endmodule + + +module top ( +input [3:0] S, +input [15:0] D, +output M2,M4,M8,M16 +); + +mux2 u_mux2 ( + .S (S[0]), + .A (D[0]), + .B (D[1]), + .Y (M2) + ); + + +mux4 u_mux4 ( + .S (S[1:0]), + .D (D[3:0]), + .Y (M4) + ); + +mux8 u_mux8 ( + .S (S[2:0]), + .D (D[7:0]), + .Y (M8) + ); + +mux16 u_mux16 ( + .S (S[3:0]), + .D (D[15:0]), + .Y (M16) + ); + +endmodule diff --git a/tests/anlogic/mux.ys b/tests/anlogic/mux.ys new file mode 100644 index 000000000..84a8bcccf --- /dev/null +++ b/tests/anlogic/mux.ys @@ -0,0 +1,12 @@ +read_verilog mux.v +proc +flatten +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:AL_MAP_LUT3 +select -assert-count 4 t:AL_MAP_LUT4 +select -assert-count 4 t:AL_MAP_LUT5 +select -assert-count 1 t:AL_MAP_LUT6 +select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_LUT6 %% t:* %D diff --git a/tests/anlogic/run-test.sh b/tests/anlogic/run-test.sh new file mode 100755 index 000000000..2c72ca3a9 --- /dev/null +++ b/tests/anlogic/run-test.sh @@ -0,0 +1,20 @@ +#!/usr/bin/env bash +set -e +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" +done +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s" + fi +done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/anlogic/shifter.v b/tests/anlogic/shifter.v new file mode 100644 index 000000000..c55632552 --- /dev/null +++ b/tests/anlogic/shifter.v @@ -0,0 +1,22 @@ +module top ( +out, +clk, +in +); + output [7:0] out; + input signed clk, in; + reg signed [7:0] out = 0; + + always @(posedge clk) + begin +`ifndef BUG + out <= out >> 1; + out[7] <= in; +`else + + out <= out << 1; + out[7] <= in; +`endif + end + +endmodule diff --git a/tests/anlogic/shifter.ys b/tests/anlogic/shifter.ys new file mode 100644 index 000000000..edd89b344 --- /dev/null +++ b/tests/anlogic/shifter.ys @@ -0,0 +1,9 @@ +read_verilog shifter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 8 t:AL_MAP_SEQ +select -assert-none t:AL_MAP_SEQ %% t:* %D diff --git a/tests/anlogic/tribuf.v b/tests/anlogic/tribuf.v new file mode 100644 index 000000000..870a02584 --- /dev/null +++ b/tests/anlogic/tribuf.v @@ -0,0 +1,23 @@ +module tristate (en, i, o); + input en; + input i; + output o; + + assign o = en ? i : 1'bz; + +endmodule + + +module top ( +input en, +input a, +output b +); + +tristate u_tri ( + .en (en ), + .i (a ), + .o (b ) + ); + +endmodule diff --git a/tests/anlogic/tribuf.ys b/tests/anlogic/tribuf.ys new file mode 100644 index 000000000..663e93fb2 --- /dev/null +++ b/tests/anlogic/tribuf.ys @@ -0,0 +1,9 @@ +read_verilog tribuf.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/anlogic/cells_sim.v -map +/simcells.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D -- cgit v1.2.3 From eeb86247c59f7ea7f98c05eaa456d0ebe041d149 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 15:14:41 -0700 Subject: Update fsm.ys resource count --- tests/ecp5/fsm.ys | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'tests') diff --git a/tests/ecp5/fsm.ys b/tests/ecp5/fsm.ys index bdd910163..36b10c0ce 100644 --- a/tests/ecp5/fsm.ys +++ b/tests/ecp5/fsm.ys @@ -8,7 +8,7 @@ equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:L6MUX21 -select -assert-count 15 t:LUT4 -select -assert-count 6 t:PFUMX -select -assert-count 6 t:TRELLIS_FF +select -assert-count 13 t:LUT4 +select -assert-count 5 t:PFUMX +select -assert-count 5 t:TRELLIS_FF select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D -- cgit v1.2.3 From d992858318c9fae869a7d0d4ed046ed8c5ea5811 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 15:15:14 -0700 Subject: Move $x to end as per 7f0eec8 --- tests/ecp5/run-test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/ecp5/run-test.sh b/tests/ecp5/run-test.sh index 2c72ca3a9..46716f9a0 100755 --- a/tests/ecp5/run-test.sh +++ b/tests/ecp5/run-test.sh @@ -6,7 +6,7 @@ for x in *.ys; do echo "all:: run-$x" echo "run-$x:" echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" + echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then -- cgit v1.2.3 From f8d5e11aa7285fc92832b87063d530afe27eca28 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 19:54:04 -0700 Subject: Update resource count for alu.ys --- tests/ecp5/alu.ys | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'tests') diff --git a/tests/ecp5/alu.ys b/tests/ecp5/alu.ys index d10cd63b2..c2950b164 100644 --- a/tests/ecp5/alu.ys +++ b/tests/ecp5/alu.ys @@ -6,8 +6,8 @@ equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 32 t:CCU2C -select -assert-count 253 t:L6MUX21 -select -assert-count 1150 t:LUT4 -select -assert-count 423 t:PFUMX +select -assert-count 242 t:L6MUX21 +select -assert-count 1127 t:LUT4 +select -assert-count 417 t:PFUMX select -assert-count 32 t:TRELLIS_FF select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D -- cgit v1.2.3 From 1caaf5149258ff84ac2a6532c26e9ffb076183a9 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 19:54:59 -0700 Subject: equiv_opt with -assert --- tests/ecp5/fsm.ys | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'tests') diff --git a/tests/ecp5/fsm.ys b/tests/ecp5/fsm.ys index 36b10c0ce..6368edc57 100644 --- a/tests/ecp5/fsm.ys +++ b/tests/ecp5/fsm.ys @@ -2,9 +2,7 @@ read_verilog fsm.v hierarchy -top top proc flatten -#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'. -#equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:L6MUX21 -- cgit v1.2.3 From fc56459746fec7751735749e3328378e1089b914 Mon Sep 17 00:00:00 2001 From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com> Date: Tue, 1 Oct 2019 10:55:34 +0300 Subject: run-test.sh Move $x at end of line. --- tests/anlogic/run-test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/anlogic/run-test.sh b/tests/anlogic/run-test.sh index 2c72ca3a9..46716f9a0 100755 --- a/tests/anlogic/run-test.sh +++ b/tests/anlogic/run-test.sh @@ -6,7 +6,7 @@ for x in *.ys; do echo "all:: run-$x" echo "run-$x:" echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" + echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then -- cgit v1.2.3 From c28d4b804720c2cf0086e921748219150e9631b5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 2 Oct 2019 14:52:40 -0700 Subject: Add test that is expecting to fail --- tests/sat/initval.ys | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'tests') diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys index 2079d2f34..1627a37e3 100644 --- a/tests/sat/initval.ys +++ b/tests/sat/initval.ys @@ -2,3 +2,23 @@ read_verilog -sv initval.v proc;; sat -seq 10 -prove-asserts + +read_verilog < Date: Wed, 2 Oct 2019 17:48:55 -0700 Subject: Add test --- tests/various/peepopt.ys | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'tests') diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index 6bca62e2b..dc0acf3ca 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -173,3 +173,34 @@ select -assert-count 1 t:$dff r:WIDTH=2 %i select -assert-count 2 t:$mux select -assert-count 2 t:$mux r:WIDTH=2 %i select -assert-count 0 t:$logic_not t:$dff t:$mux %% t:* %D + +#################### + +design -reset +read_verilog < Date: Wed, 2 Oct 2019 18:03:45 -0700 Subject: Update test --- tests/various/peepopt.ys | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) (limited to 'tests') diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index dc0acf3ca..734a22408 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -188,19 +188,9 @@ endmodule EOT proc -#equiv_opt -assert peepopt - -design -save gold -peepopt -design -stash gate -design -import gold -as gold -design -import gate -as gate -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -seq 1 -verify -prove-asserts -show-ports miter - +equiv_opt -assert peepopt design -load postopt -wreduce -select -assert-count 1 t:$dff r:WIDTH=2 %i +select -assert-count 1 t:$dff r:WIDTH=4 %i select -assert-count 2 t:$mux -select -assert-count 2 t:$mux r:WIDTH=2 %i +select -assert-count 2 t:$mux r:WIDTH=4 %i select -assert-count 0 t:$logic_not t:$dff t:$mux %% t:* %D -- cgit v1.2.3 From e4bd5aaebf7e329236b10c93eac9ad113231f00e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 2 Oct 2019 18:12:25 -0700 Subject: Fix test --- tests/various/peepopt.ys | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index 734a22408..1f18f1c74 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -188,8 +188,18 @@ endmodule EOT proc -equiv_opt -assert peepopt -design -load postopt +#equiv_opt -assert peepopt + +design -save gold +peepopt +wreduce +design -stash gate +design -import gold -as gold +design -import gate -as gate +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -seq 1 -verify -prove-asserts -show-ports miter + +design -load gate select -assert-count 1 t:$dff r:WIDTH=4 %i select -assert-count 2 t:$mux select -assert-count 2 t:$mux r:WIDTH=4 %i -- cgit v1.2.3 From e9645c7fa7fc349afad103ff8736699bb4dc0412 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 2 Oct 2019 21:26:26 -0700 Subject: Fix broken CI, check reset even for constants, trim rstmux --- tests/various/peepopt.ys | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index 1f18f1c74..4b130578b 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -131,8 +131,8 @@ EOT proc equiv_opt -assert peepopt design -load postopt -select -assert-count 1 t:$dff r:WIDTH=5 %i -select -assert-count 1 t:$mux r:WIDTH=5 %i +select -assert-count 1 t:$dff r:WIDTH=4 %i +select -assert-count 1 t:$mux r:WIDTH=4 %i select -assert-count 0 t:$dff t:$mux %% t:* %D #################### -- cgit v1.2.3 From f6b5e47e40b4a2bda6e5d928480ea218a6a911c2 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 19 Sep 2019 20:43:13 +0100 Subject: sv: Switch parser to glr, prep for typedef Signed-off-by: David Shah --- tests/svtypes/typedef1.sv | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 tests/svtypes/typedef1.sv (limited to 'tests') diff --git a/tests/svtypes/typedef1.sv b/tests/svtypes/typedef1.sv new file mode 100644 index 000000000..9e5d02364 --- /dev/null +++ b/tests/svtypes/typedef1.sv @@ -0,0 +1,22 @@ +`define STRINGIFY(x) `"x`" +`define STATIC_ASSERT(x) if(!(x)) $error({"assert failed: ", `STRINGIFY(x)}) + +module top; + + typedef logic [1:0] uint2_t; + typedef logic signed [3:0] int4_t; + typedef logic signed [7:0] int8_t; + typedef int8_t char_t; + + (* keep *) uint2_t int2 = 2'b10; + (* keep *) int4_t int4 = -1; + (* keep *) int8_t int8 = int4; + (* keep *) char_t ch = int8; + + + always @* assert(int2 == 2'b10); + always @* assert(int4 == 4'b1111); + always @* assert(int8 == 8'b11111111); + always @* assert(ch == 8'b11111111); + +endmodule \ No newline at end of file -- cgit v1.2.3 From c9629516120930aedaf52d72fec5d7fabe51d496 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 19 Sep 2019 21:07:20 +0100 Subject: sv: Fix typedef parameters Signed-off-by: David Shah --- tests/svtypes/typedef1.sv | 22 ---------------------- tests/svtypes/typedef_param.sv | 22 ++++++++++++++++++++++ tests/svtypes/typedef_simple.sv | 19 +++++++++++++++++++ 3 files changed, 41 insertions(+), 22 deletions(-) delete mode 100644 tests/svtypes/typedef1.sv create mode 100644 tests/svtypes/typedef_param.sv create mode 100644 tests/svtypes/typedef_simple.sv (limited to 'tests') diff --git a/tests/svtypes/typedef1.sv b/tests/svtypes/typedef1.sv deleted file mode 100644 index 9e5d02364..000000000 --- a/tests/svtypes/typedef1.sv +++ /dev/null @@ -1,22 +0,0 @@ -`define STRINGIFY(x) `"x`" -`define STATIC_ASSERT(x) if(!(x)) $error({"assert failed: ", `STRINGIFY(x)}) - -module top; - - typedef logic [1:0] uint2_t; - typedef logic signed [3:0] int4_t; - typedef logic signed [7:0] int8_t; - typedef int8_t char_t; - - (* keep *) uint2_t int2 = 2'b10; - (* keep *) int4_t int4 = -1; - (* keep *) int8_t int8 = int4; - (* keep *) char_t ch = int8; - - - always @* assert(int2 == 2'b10); - always @* assert(int4 == 4'b1111); - always @* assert(int8 == 8'b11111111); - always @* assert(ch == 8'b11111111); - -endmodule \ No newline at end of file diff --git a/tests/svtypes/typedef_param.sv b/tests/svtypes/typedef_param.sv new file mode 100644 index 000000000..13a522f19 --- /dev/null +++ b/tests/svtypes/typedef_param.sv @@ -0,0 +1,22 @@ +`define STRINGIFY(x) `"x`" +`define STATIC_ASSERT(x) if(!(x)) $error({"assert failed: ", `STRINGIFY(x)}) + +module top; + + typedef logic [1:0] uint2_t; + typedef logic signed [3:0] int4_t; + typedef logic signed [7:0] int8_t; + typedef int8_t char_t; + + parameter uint2_t int2 = 2'b10; + localparam int4_t int4 = -1; + localparam int8_t int8 = int4; + localparam char_t ch = int8; + + + `STATIC_ASSERT(int2 == 2'b10); + `STATIC_ASSERT(int4 == 4'b1111); + `STATIC_ASSERT(int8 == 8'b11111111); + `STATIC_ASSERT(ch == 8'b11111111); + +endmodule \ No newline at end of file diff --git a/tests/svtypes/typedef_simple.sv b/tests/svtypes/typedef_simple.sv new file mode 100644 index 000000000..0cf2c072c --- /dev/null +++ b/tests/svtypes/typedef_simple.sv @@ -0,0 +1,19 @@ +module top; + + typedef logic [1:0] uint2_t; + typedef logic signed [3:0] int4_t; + typedef logic signed [7:0] int8_t; + typedef int8_t char_t; + + (* keep *) uint2_t int2 = 2'b10; + (* keep *) int4_t int4 = -1; + (* keep *) int8_t int8 = int4; + (* keep *) char_t ch = int8; + + + always @* assert(int2 == 2'b10); + always @* assert(int4 == 4'b1111); + always @* assert(int8 == 8'b11111111); + always @* assert(ch == 8'b11111111); + +endmodule \ No newline at end of file -- cgit v1.2.3 From e70e4afb60a41da6d9f6200b20f36f61c6b993b2 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 19 Sep 2019 21:21:21 +0100 Subject: sv: Fix typedefs in packages Signed-off-by: David Shah --- tests/svtypes/typedef_package.sv | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 tests/svtypes/typedef_package.sv (limited to 'tests') diff --git a/tests/svtypes/typedef_package.sv b/tests/svtypes/typedef_package.sv new file mode 100644 index 000000000..4aa22b6af --- /dev/null +++ b/tests/svtypes/typedef_package.sv @@ -0,0 +1,11 @@ +package pkg; + typedef logic [7:0] uint8_t; +endpackage + +module top; + + (* keep *) pkg::uint8_t a = 8'hAA; + + always @* assert(a == 8'hAA); + +endmodule \ No newline at end of file -- cgit v1.2.3 From 30d23260309ef392a0e69fe5294c38b71ad0692e Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 20 Sep 2019 11:39:15 +0100 Subject: sv: Add support for memory typedefs Signed-off-by: David Shah --- tests/svtypes/typedef_memory.sv | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 tests/svtypes/typedef_memory.sv (limited to 'tests') diff --git a/tests/svtypes/typedef_memory.sv b/tests/svtypes/typedef_memory.sv new file mode 100644 index 000000000..c848c3287 --- /dev/null +++ b/tests/svtypes/typedef_memory.sv @@ -0,0 +1,10 @@ +module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata); + typedef logic [3:0] ram16x4_t[0:15]; + + ram16x4_t mem; + + always @(posedge clk) begin + if (wen) mem[addr] <= wdata; + rdata <= mem[addr]; + end +endmodule \ No newline at end of file -- cgit v1.2.3 From af25585170f87506bcc7dbe5afe0fec868290d5b Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 20 Sep 2019 11:46:37 +0100 Subject: sv: Add support for memories of a typedef Signed-off-by: David Shah --- tests/svtypes/typedef_memory_2.sv | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 tests/svtypes/typedef_memory_2.sv (limited to 'tests') diff --git a/tests/svtypes/typedef_memory_2.sv b/tests/svtypes/typedef_memory_2.sv new file mode 100644 index 000000000..1e8abb155 --- /dev/null +++ b/tests/svtypes/typedef_memory_2.sv @@ -0,0 +1,10 @@ +module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata); + typedef logic [3:0] nibble; + + nibble mem[0:15]; + + always @(posedge clk) begin + if (wen) mem[addr] <= wdata; + rdata <= mem[addr]; + end +endmodule \ No newline at end of file -- cgit v1.2.3 From abc155715dbe8db5ee95707f7c243f23954ca139 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 20 Sep 2019 13:00:26 +0100 Subject: sv: Add test scripts for typedefs Signed-off-by: David Shah --- tests/svtypes/.gitignore | 3 +++ tests/svtypes/run-test.sh | 20 ++++++++++++++++++++ tests/svtypes/typedef_memory.ys | 3 +++ tests/svtypes/typedef_memory_2.ys | 4 ++++ 4 files changed, 30 insertions(+) create mode 100644 tests/svtypes/.gitignore create mode 100755 tests/svtypes/run-test.sh create mode 100644 tests/svtypes/typedef_memory.ys create mode 100644 tests/svtypes/typedef_memory_2.ys (limited to 'tests') diff --git a/tests/svtypes/.gitignore b/tests/svtypes/.gitignore new file mode 100644 index 000000000..b48f808a1 --- /dev/null +++ b/tests/svtypes/.gitignore @@ -0,0 +1,3 @@ +/*.log +/*.out +/run-test.mk diff --git a/tests/svtypes/run-test.sh b/tests/svtypes/run-test.sh new file mode 100755 index 000000000..09a30eed1 --- /dev/null +++ b/tests/svtypes/run-test.sh @@ -0,0 +1,20 @@ +#!/usr/bin/env bash +set -e +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log $x" +done +for x in *.sv; do + if [ ! -f "${x%.sv}.ys" ]; then + echo "all:: check-$x" + echo "check-$x:" + echo " @echo 'Checking $x..'" + echo " @../../yosys -ql ${x%.sv}.log -p \"prep -top top; sat -verify -prove-asserts\" $x" + fi +done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/svtypes/typedef_memory.ys b/tests/svtypes/typedef_memory.ys new file mode 100644 index 000000000..bc1127dc5 --- /dev/null +++ b/tests/svtypes/typedef_memory.ys @@ -0,0 +1,3 @@ +read -sv typedef_memory.sv +prep -top top +select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i \ No newline at end of file diff --git a/tests/svtypes/typedef_memory_2.ys b/tests/svtypes/typedef_memory_2.ys new file mode 100644 index 000000000..571e28914 --- /dev/null +++ b/tests/svtypes/typedef_memory_2.ys @@ -0,0 +1,4 @@ +read -sv typedef_memory_2.sv +prep -top top +dump +select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i \ No newline at end of file -- cgit v1.2.3 From 9b9d24f15b1b91b64b97e12bd05693f4539762d9 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 20 Sep 2019 18:40:35 +0100 Subject: sv: Improve tests Signed-off-by: David Shah --- tests/svtypes/typedef_memory.sv | 2 +- tests/svtypes/typedef_memory.ys | 2 +- tests/svtypes/typedef_memory_2.sv | 2 +- tests/svtypes/typedef_memory_2.ys | 2 +- tests/svtypes/typedef_package.sv | 2 +- tests/svtypes/typedef_param.sv | 2 +- tests/svtypes/typedef_scopes.sv | 23 +++++++++++++++++++++++ tests/svtypes/typedef_simple.sv | 2 +- 8 files changed, 30 insertions(+), 7 deletions(-) create mode 100644 tests/svtypes/typedef_scopes.sv (limited to 'tests') diff --git a/tests/svtypes/typedef_memory.sv b/tests/svtypes/typedef_memory.sv index c848c3287..37e63c1d0 100644 --- a/tests/svtypes/typedef_memory.sv +++ b/tests/svtypes/typedef_memory.sv @@ -7,4 +7,4 @@ module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata); if (wen) mem[addr] <= wdata; rdata <= mem[addr]; end -endmodule \ No newline at end of file +endmodule diff --git a/tests/svtypes/typedef_memory.ys b/tests/svtypes/typedef_memory.ys index bc1127dc5..d0b8cf5bf 100644 --- a/tests/svtypes/typedef_memory.ys +++ b/tests/svtypes/typedef_memory.ys @@ -1,3 +1,3 @@ read -sv typedef_memory.sv prep -top top -select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i \ No newline at end of file +select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i diff --git a/tests/svtypes/typedef_memory_2.sv b/tests/svtypes/typedef_memory_2.sv index 1e8abb155..6d65131db 100644 --- a/tests/svtypes/typedef_memory_2.sv +++ b/tests/svtypes/typedef_memory_2.sv @@ -7,4 +7,4 @@ module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata); if (wen) mem[addr] <= wdata; rdata <= mem[addr]; end -endmodule \ No newline at end of file +endmodule diff --git a/tests/svtypes/typedef_memory_2.ys b/tests/svtypes/typedef_memory_2.ys index 571e28914..0997beeea 100644 --- a/tests/svtypes/typedef_memory_2.ys +++ b/tests/svtypes/typedef_memory_2.ys @@ -1,4 +1,4 @@ read -sv typedef_memory_2.sv prep -top top dump -select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i \ No newline at end of file +select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i diff --git a/tests/svtypes/typedef_package.sv b/tests/svtypes/typedef_package.sv index 4aa22b6af..bee88b7ae 100644 --- a/tests/svtypes/typedef_package.sv +++ b/tests/svtypes/typedef_package.sv @@ -8,4 +8,4 @@ module top; always @* assert(a == 8'hAA); -endmodule \ No newline at end of file +endmodule diff --git a/tests/svtypes/typedef_param.sv b/tests/svtypes/typedef_param.sv index 13a522f19..d838dd828 100644 --- a/tests/svtypes/typedef_param.sv +++ b/tests/svtypes/typedef_param.sv @@ -19,4 +19,4 @@ module top; `STATIC_ASSERT(int8 == 8'b11111111); `STATIC_ASSERT(ch == 8'b11111111); -endmodule \ No newline at end of file +endmodule diff --git a/tests/svtypes/typedef_scopes.sv b/tests/svtypes/typedef_scopes.sv new file mode 100644 index 000000000..340defbbb --- /dev/null +++ b/tests/svtypes/typedef_scopes.sv @@ -0,0 +1,23 @@ + +typedef logic [3:0] outer_uint4_t; + +module top; + + outer_uint4_t u4_i = 8'hA5; + always @(*) assert(u4_i == 4'h5); + + typedef logic [3:0] inner_type; + inner_type inner_i1 = 8'h5A; + always @(*) assert(inner_i1 == 4'hA); + + if (1) begin: genblock + typedef logic [7:0] inner_type; + inner_type inner_gb_i = 8'hA5; + always @(*) assert(inner_gb_i == 8'hA5); + end + + inner_type inner_i2 = 8'h42; + always @(*) assert(inner_i2 == 4'h2); + + +endmodule diff --git a/tests/svtypes/typedef_simple.sv b/tests/svtypes/typedef_simple.sv index 0cf2c072c..8f89910e5 100644 --- a/tests/svtypes/typedef_simple.sv +++ b/tests/svtypes/typedef_simple.sv @@ -16,4 +16,4 @@ module top; always @* assert(int8 == 8'b11111111); always @* assert(ch == 8'b11111111); -endmodule \ No newline at end of file +endmodule -- cgit v1.2.3 From 5d680590d6bccd929ed3909248dbb73fb3876e65 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 3 Oct 2019 10:30:33 -0700 Subject: Use equiv_opt -async2sync for xilinx --- tests/xilinx/latches.ys | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'tests') diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys index ac1102896..bd1dffd21 100644 --- a/tests/xilinx/latches.ys +++ b/tests/xilinx/latches.ys @@ -2,9 +2,7 @@ read_verilog latches.v proc flatten -equiv_opt -assert -run :prove -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -async2sync -equiv_opt -assert -run prove: -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load preopt synth_xilinx -- cgit v1.2.3 From bd5889640bbcbb11c80360893fcf17d9399cef8a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 3 Oct 2019 10:45:53 -0700 Subject: Disable equiv check for ice40 latches --- tests/ice40/latches.ys | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'tests') diff --git a/tests/ice40/latches.ys b/tests/ice40/latches.ys index f3562559e..708734e44 100644 --- a/tests/ice40/latches.ys +++ b/tests/ice40/latches.ys @@ -1,14 +1,11 @@ read_verilog latches.v -design -save read proc -async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock flatten -synth_ice40 -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +# Can't run any sort of equivalence check because latches are blown to LUTs +#equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load read +#design -load preopt synth_ice40 cd top select -assert-count 4 t:SB_LUT4 -- cgit v1.2.3 From 045f34403889b69f3ac3ac08d96e5cf1fae787d1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 3 Oct 2019 11:11:50 -0700 Subject: Use `sat -tempinduct` and comments for why equiv_opt not sufficient --- tests/various/peepopt.ys | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys index 4b130578b..ee5ad8a1a 100644 --- a/tests/various/peepopt.ys +++ b/tests/various/peepopt.ys @@ -188,6 +188,13 @@ endmodule EOT proc +# NB: equiv_opt uses equiv_induct which covers +# only the induction half of temporal induction +# --- missing the base-case half +# This makes it akin to `sat -tempinduct-inductonly` +# instead of `sat -tempinduct-baseonly` or +# `sat -tempinduct` which is necessary for this +# testcase #equiv_opt -assert peepopt design -save gold @@ -197,7 +204,7 @@ design -stash gate design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -seq 1 -verify -prove-asserts -show-ports miter +sat -tempinduct -verify -prove-asserts -show-ports miter design -load gate select -assert-count 1 t:$dff r:WIDTH=4 %i -- cgit v1.2.3 From d19f765a581ac465a7f7cea22f1d96c9da9cbe01 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 08:41:53 +0200 Subject: Removed alu and div_mod tests as agreed --- tests/ecp5/alu.v | 19 ------------------- tests/ecp5/alu.ys | 13 ------------- tests/ecp5/div_mod.v | 13 ------------- tests/ecp5/div_mod.ys | 12 ------------ 4 files changed, 57 deletions(-) delete mode 100644 tests/ecp5/alu.v delete mode 100644 tests/ecp5/alu.ys delete mode 100644 tests/ecp5/div_mod.v delete mode 100644 tests/ecp5/div_mod.ys (limited to 'tests') diff --git a/tests/ecp5/alu.v b/tests/ecp5/alu.v deleted file mode 100644 index f82cc2e21..000000000 --- a/tests/ecp5/alu.v +++ /dev/null @@ -1,19 +0,0 @@ -module top ( - input clock, - input [31:0] dinA, dinB, - input [2:0] opcode, - output reg [31:0] dout -); - always @(posedge clock) begin - case (opcode) - 0: dout <= dinA + dinB; - 1: dout <= dinA - dinB; - 2: dout <= dinA >> dinB; - 3: dout <= $signed(dinA) >>> dinB; - 4: dout <= dinA << dinB; - 5: dout <= dinA & dinB; - 6: dout <= dinA | dinB; - 7: dout <= dinA ^ dinB; - endcase - end -endmodule diff --git a/tests/ecp5/alu.ys b/tests/ecp5/alu.ys deleted file mode 100644 index c2950b164..000000000 --- a/tests/ecp5/alu.ys +++ /dev/null @@ -1,13 +0,0 @@ -read_verilog alu.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 32 t:CCU2C -select -assert-count 242 t:L6MUX21 -select -assert-count 1127 t:LUT4 -select -assert-count 417 t:PFUMX -select -assert-count 32 t:TRELLIS_FF -select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D diff --git a/tests/ecp5/div_mod.v b/tests/ecp5/div_mod.v deleted file mode 100644 index 64a36707d..000000000 --- a/tests/ecp5/div_mod.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x % y; -assign B = x / y; - -endmodule diff --git a/tests/ecp5/div_mod.ys b/tests/ecp5/div_mod.ys deleted file mode 100644 index 9efb00701..000000000 --- a/tests/ecp5/div_mod.ys +++ /dev/null @@ -1,12 +0,0 @@ -read_verilog div_mod.v -hierarchy -top top -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 28 t:CCU2C -select -assert-count 26 t:L6MUX21 -select -assert-count 138 t:LUT4 -select -assert-count 60 t:PFUMX -select -assert-none t:LUT4 t:CCU2C t:L6MUX21 t:PFUMX %% t:* %D -- cgit v1.2.3 From 9e8175fc759478a7a496ac0d492cb4b6d0f13799 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 08:42:29 +0200 Subject: Check flops one by one --- tests/ecp5/adffs.v | 40 ---------------------------------------- tests/ecp5/adffs.ys | 41 ++++++++++++++++++++++++++++++++++++----- tests/ecp5/dffs.v | 22 ---------------------- tests/ecp5/dffs.ys | 18 ++++++++++++++---- 4 files changed, 50 insertions(+), 71 deletions(-) (limited to 'tests') diff --git a/tests/ecp5/adffs.v b/tests/ecp5/adffs.v index 05e68caf7..223b52d21 100644 --- a/tests/ecp5/adffs.v +++ b/tests/ecp5/adffs.v @@ -45,43 +45,3 @@ module ndffnr else q <= d; endmodule - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2,b3 -); - -dffs u_dffs ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b ) - ); - -ndffnr u_ndffnr ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b1 ) - ); - -adff u_adff ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b2 ) - ); - -adffn u_adffn ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b3 ) - ); - -endmodule diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys index fc1363a32..658f302d0 100644 --- a/tests/ecp5/adffs.ys +++ b/tests/ecp5/adffs.ys @@ -1,9 +1,40 @@ read_verilog adffs.v +design -save read + proc -flatten -equiv_opt -multiclock -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +hierarchy -top adff +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 4 t:TRELLIS_FF -select -assert-count 3 t:LUT4 +cd adff # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-none t:TRELLIS_FF %% t:* %D + +design -load read +proc +hierarchy -top adffn +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adffn # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-count 1 t:LUT4 +select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D + +design -load read +proc +hierarchy -top dffs +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffs # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-count 1 t:LUT4 +select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D + +design -load read +proc +hierarchy -top ndffnr +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd ndffnr # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-count 1 t:LUT4 select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D diff --git a/tests/ecp5/dffs.v b/tests/ecp5/dffs.v index d97840c43..3418787c9 100644 --- a/tests/ecp5/dffs.v +++ b/tests/ecp5/dffs.v @@ -13,25 +13,3 @@ module dffe if ( en ) q <= d; endmodule - -module top ( -input clk, -input en, -input a, -output b,b1, -); - -dff u_dff ( - .clk (clk ), - .d (a ), - .q (b ) - ); - -dffe u_ndffe ( - .clk (clk ), - .en (en), - .d (a ), - .q (b1 ) - ); - -endmodule diff --git a/tests/ecp5/dffs.ys b/tests/ecp5/dffs.ys index 5510bb440..93b8595ad 100644 --- a/tests/ecp5/dffs.ys +++ b/tests/ecp5/dffs.ys @@ -1,9 +1,19 @@ read_verilog dffs.v -hierarchy -top top +design -save read + proc -flatten +hierarchy -top dff equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 2 t:TRELLIS_FF +cd dff # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF select -assert-none t:TRELLIS_FF %% t:* %D + +design -load read +proc +hierarchy -top dffe +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-none t:TRELLIS_FF %% t:* %D \ No newline at end of file -- cgit v1.2.3 From abb5a3a44df18a6ca18b6998f4c35aafc4284df8 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 08:44:10 +0200 Subject: Check for MULT18X18D, since that is working now --- tests/ecp5/macc.ys | 12 +++++------- tests/ecp5/mul.ys | 13 ++++++------- 2 files changed, 11 insertions(+), 14 deletions(-) (limited to 'tests') diff --git a/tests/ecp5/macc.ys b/tests/ecp5/macc.ys index bc6340509..f60281a54 100644 --- a/tests/ecp5/macc.ys +++ b/tests/ecp5/macc.ys @@ -1,15 +1,13 @@ read_verilog macc.v proc hierarchy -top top -#Failed because of 14 unproven cells. -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -#equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +# Blocked by issue #1358 (Missing ECP5 simulation models) +#equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:MULT18X18D select -assert-count 4 t:CCU2C -select -assert-count 6 t:L6MUX21 -select -assert-count 49 t:LUT4 -select -assert-count 19 t:PFUMX select -assert-count 7 t:TRELLIS_FF -select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D +select -assert-none t:CCU2C t:MULT18X18D t:TRELLIS_FF %% t:* %D diff --git a/tests/ecp5/mul.ys b/tests/ecp5/mul.ys index 0e8d6908f..132340664 100644 --- a/tests/ecp5/mul.ys +++ b/tests/ecp5/mul.ys @@ -1,11 +1,10 @@ read_verilog mul.v hierarchy -top top -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +# Blocked by issue #1358 (Missing ECP5 simulation models) +#equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check + design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 6 t:CCU2C -select -assert-count 46 t:L6MUX21 -select -assert-count 169 t:LUT4 -select -assert-count 72 t:PFUMX - -select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX %% t:* %D +select -assert-count 1 t:MULT18X18D +select -assert-none t:MULT18X18D %% t:* %D -- cgit v1.2.3 From d6ef9b1a6b47e740dba948e5f2fcf456d7ee79cf Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 08:45:58 +0200 Subject: Cleaned verilog code from not used defines --- tests/ecp5/shifter.v | 6 ------ 1 file changed, 6 deletions(-) (limited to 'tests') diff --git a/tests/ecp5/shifter.v b/tests/ecp5/shifter.v index c55632552..04ae49d83 100644 --- a/tests/ecp5/shifter.v +++ b/tests/ecp5/shifter.v @@ -9,14 +9,8 @@ in always @(posedge clk) begin -`ifndef BUG out <= out >> 1; out[7] <= in; -`else - - out <= out << 1; - out[7] <= in; -`endif end endmodule -- cgit v1.2.3 From 3c40c810307c2bed62527f4f067790edc4ac8823 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 08:52:54 +0200 Subject: Test muxes synth one by one --- tests/ecp5/mux.v | 34 ---------------------------------- tests/ecp5/mux.ys | 43 +++++++++++++++++++++++++++++++++++++++---- 2 files changed, 39 insertions(+), 38 deletions(-) (limited to 'tests') diff --git a/tests/ecp5/mux.v b/tests/ecp5/mux.v index 0814b733e..782424a9b 100644 --- a/tests/ecp5/mux.v +++ b/tests/ecp5/mux.v @@ -64,37 +64,3 @@ assign Y = D[S]; endmodule - -module top ( -input [3:0] S, -input [15:0] D, -output M2,M4,M8,M16 -); - -mux2 u_mux2 ( - .S (S[0]), - .A (D[0]), - .B (D[1]), - .Y (M2) - ); - - -mux4 u_mux4 ( - .S (S[1:0]), - .D (D[3:0]), - .Y (M4) - ); - -mux8 u_mux8 ( - .S (S[2:0]), - .D (D[7:0]), - .Y (M8) - ); - -mux16 u_mux16 ( - .S (S[3:0]), - .D (D[15:0]), - .Y (M16) - ); - -endmodule diff --git a/tests/ecp5/mux.ys b/tests/ecp5/mux.ys index 7d40c9cf1..eada276ba 100644 --- a/tests/ecp5/mux.ys +++ b/tests/ecp5/mux.ys @@ -1,11 +1,46 @@ read_verilog mux.v +design -save read + +proc +hierarchy -top mux2 +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux2 # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT4 +select -assert-none t:LUT4 %% t:* %D + +design -load read +proc +hierarchy -top mux4 +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 1 t:L6MUX21 +select -assert-count 4 t:LUT4 +select -assert-count 2 t:PFUMX + +select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D + +design -load read +proc +hierarchy -top mux8 +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 1 t:L6MUX21 +select -assert-count 7 t:LUT4 +select -assert-count 2 t:PFUMX + +select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D + +design -load read proc -flatten +hierarchy -top mux16 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 32 t:LUT4 +cd mux16 # Constrain all select calls below inside the top module select -assert-count 8 t:L6MUX21 -select -assert-count 14 t:PFUMX +select -assert-count 26 t:LUT4 +select -assert-count 12 t:PFUMX select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D -- cgit v1.2.3 From 3358b2f18597c59ee3cac5f123f954ca79e0baad Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 09:53:54 +0200 Subject: Removed top module where not needed --- tests/ecp5/fsm.v | 18 ------------------ tests/ecp5/fsm.ys | 4 ++-- tests/ecp5/tribuf.v | 15 --------------- tests/ecp5/tribuf.ys | 4 ++-- 4 files changed, 4 insertions(+), 37 deletions(-) (limited to 'tests') diff --git a/tests/ecp5/fsm.v b/tests/ecp5/fsm.v index 0605bd102..368fbaace 100644 --- a/tests/ecp5/fsm.v +++ b/tests/ecp5/fsm.v @@ -52,22 +52,4 @@ endcase end - endmodule - - module top ( -input clk, -input rst, -input a, -input b, -output g0, -output g1 -); - -fsm u_fsm ( .clock(clk), - .reset(rst), - .req_0(a), - .req_1(b), - .gnt_0(g0), - .gnt_1(g1)); - endmodule diff --git a/tests/ecp5/fsm.ys b/tests/ecp5/fsm.ys index 6368edc57..ded91e5f7 100644 --- a/tests/ecp5/fsm.ys +++ b/tests/ecp5/fsm.ys @@ -1,10 +1,10 @@ read_verilog fsm.v -hierarchy -top top +hierarchy -top fsm proc flatten equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd fsm # Constrain all select calls below inside the top module select -assert-count 1 t:L6MUX21 select -assert-count 13 t:LUT4 select -assert-count 5 t:PFUMX diff --git a/tests/ecp5/tribuf.v b/tests/ecp5/tribuf.v index 870a02584..90dd314e4 100644 --- a/tests/ecp5/tribuf.v +++ b/tests/ecp5/tribuf.v @@ -6,18 +6,3 @@ module tristate (en, i, o); assign o = en ? i : 1'bz; endmodule - - -module top ( -input en, -input a, -output b -); - -tristate u_tri ( - .en (en ), - .i (a ), - .o (b ) - ); - -endmodule diff --git a/tests/ecp5/tribuf.ys b/tests/ecp5/tribuf.ys index f454a0c02..a6e9c9598 100644 --- a/tests/ecp5/tribuf.ys +++ b/tests/ecp5/tribuf.ys @@ -1,9 +1,9 @@ read_verilog tribuf.v -hierarchy -top top +hierarchy -top tristate proc flatten equiv_opt -assert -map +/ecp5/cells_sim.v -map +/simcells.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd tristate # Constrain all select calls below inside the top module select -assert-count 1 t:$_TBUF_ select -assert-none t:$_TBUF_ %% t:* %D -- cgit v1.2.3 From 7785f23719cdbcae6816415cf2dc124aba312c66 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 10:31:51 +0200 Subject: Check latches type one by one --- tests/ecp5/latches.v | 34 ---------------------------------- tests/ecp5/latches.ys | 31 +++++++++++++++++++++++++------ 2 files changed, 25 insertions(+), 40 deletions(-) (limited to 'tests') diff --git a/tests/ecp5/latches.v b/tests/ecp5/latches.v index 9dc43e4c2..adb5d5319 100644 --- a/tests/ecp5/latches.v +++ b/tests/ecp5/latches.v @@ -22,37 +22,3 @@ module latchsr else if ( en ) q <= d; endmodule - - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2 -); - - -latchp u_latchp ( - .en (clk ), - .d (a ), - .q (b ) - ); - - -latchn u_latchn ( - .en (clk ), - .d (a ), - .q (b1 ) - ); - - -latchsr u_latchsr ( - .en (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b2 ) - ); - -endmodule diff --git a/tests/ecp5/latches.ys b/tests/ecp5/latches.ys index b9d8faf87..f32998232 100644 --- a/tests/ecp5/latches.ys +++ b/tests/ecp5/latches.ys @@ -1,16 +1,35 @@ + read_verilog latches.v design -save read proc -async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock -flatten +hierarchy -top latchp +# Can't run any sort of equivalence check because latches are blown to LUTs synth_ecp5 -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd latchp # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT4 + +select -assert-none t:LUT4 %% t:* %D + design -load read +proc +hierarchy -top latchn +# Can't run any sort of equivalence check because latches are blown to LUTs synth_ecp5 -cd top -select -assert-count 4 t:LUT4 +cd latchn # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT4 + +select -assert-none t:LUT4 %% t:* %D + + +design -load read +proc +hierarchy -top latchsr +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_ecp5 +cd latchsr # Constrain all select calls below inside the top module +select -assert-count 2 t:LUT4 select -assert-count 1 t:PFUMX + select -assert-none t:LUT4 t:PFUMX %% t:* %D -- cgit v1.2.3 From 1435b9bf97bc5c4e625bd3ef5db19065a0af2632 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 10:55:13 +0200 Subject: remove alu test --- tests/anlogic/alu.v | 19 ------------------- tests/anlogic/alu.ys | 17 ----------------- 2 files changed, 36 deletions(-) delete mode 100644 tests/anlogic/alu.v delete mode 100644 tests/anlogic/alu.ys (limited to 'tests') diff --git a/tests/anlogic/alu.v b/tests/anlogic/alu.v deleted file mode 100644 index f82cc2e21..000000000 --- a/tests/anlogic/alu.v +++ /dev/null @@ -1,19 +0,0 @@ -module top ( - input clock, - input [31:0] dinA, dinB, - input [2:0] opcode, - output reg [31:0] dout -); - always @(posedge clock) begin - case (opcode) - 0: dout <= dinA + dinB; - 1: dout <= dinA - dinB; - 2: dout <= dinA >> dinB; - 3: dout <= $signed(dinA) >>> dinB; - 4: dout <= dinA << dinB; - 5: dout <= dinA & dinB; - 6: dout <= dinA | dinB; - 7: dout <= dinA ^ dinB; - endcase - end -endmodule diff --git a/tests/anlogic/alu.ys b/tests/anlogic/alu.ys deleted file mode 100644 index 532ce82d5..000000000 --- a/tests/anlogic/alu.ys +++ /dev/null @@ -1,17 +0,0 @@ -read_verilog alu.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 66 t:AL_MAP_ADDER -select -assert-count 32 t:AL_MAP_LUT1 -select -assert-count 23 t:AL_MAP_LUT2 -select -assert-count 61 t:AL_MAP_LUT3 -select -assert-count 209 t:AL_MAP_LUT4 -select -assert-count 100 t:AL_MAP_LUT5 -select -assert-count 79 t:AL_MAP_LUT6 -select -assert-count 32 t:AL_MAP_SEQ -select -assert-none t:AL_MAP_ADDER t:AL_MAP_LUT1 t:AL_MAP_LUT2 t:AL_MAP_LUT3 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D -- cgit v1.2.3 From 3d3479b0af0d2d59708a0828cfa785257c52d6fd Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 10:57:47 +0200 Subject: Cleanup top modules and not used defines --- tests/anlogic/fsm.v | 18 ------------------ tests/anlogic/fsm.ys | 6 +++--- tests/anlogic/shifter.v | 6 ------ tests/anlogic/tribuf.v | 15 --------------- tests/anlogic/tribuf.ys | 4 ++-- 5 files changed, 5 insertions(+), 44 deletions(-) (limited to 'tests') diff --git a/tests/anlogic/fsm.v b/tests/anlogic/fsm.v index 0605bd102..368fbaace 100644 --- a/tests/anlogic/fsm.v +++ b/tests/anlogic/fsm.v @@ -52,22 +52,4 @@ endcase end - endmodule - - module top ( -input clk, -input rst, -input a, -input b, -output g0, -output g1 -); - -fsm u_fsm ( .clock(clk), - .reset(rst), - .req_0(a), - .req_1(b), - .gnt_0(g0), - .gnt_1(g1)); - endmodule diff --git a/tests/anlogic/fsm.ys b/tests/anlogic/fsm.ys index 6eb7b9a71..76a5d3e43 100644 --- a/tests/anlogic/fsm.ys +++ b/tests/anlogic/fsm.ys @@ -1,12 +1,12 @@ read_verilog fsm.v -hierarchy -top top +hierarchy -top fsm proc -flatten +#flatten #ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'. #equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd fsm # Constrain all select calls below inside the top module select -assert-count 1 t:AL_MAP_LUT2 select -assert-count 5 t:AL_MAP_LUT5 select -assert-count 1 t:AL_MAP_LUT6 diff --git a/tests/anlogic/shifter.v b/tests/anlogic/shifter.v index c55632552..04ae49d83 100644 --- a/tests/anlogic/shifter.v +++ b/tests/anlogic/shifter.v @@ -9,14 +9,8 @@ in always @(posedge clk) begin -`ifndef BUG out <= out >> 1; out[7] <= in; -`else - - out <= out << 1; - out[7] <= in; -`endif end endmodule diff --git a/tests/anlogic/tribuf.v b/tests/anlogic/tribuf.v index 870a02584..90dd314e4 100644 --- a/tests/anlogic/tribuf.v +++ b/tests/anlogic/tribuf.v @@ -6,18 +6,3 @@ module tristate (en, i, o); assign o = en ? i : 1'bz; endmodule - - -module top ( -input en, -input a, -output b -); - -tristate u_tri ( - .en (en ), - .i (a ), - .o (b ) - ); - -endmodule diff --git a/tests/anlogic/tribuf.ys b/tests/anlogic/tribuf.ys index 663e93fb2..0eb1338ac 100644 --- a/tests/anlogic/tribuf.ys +++ b/tests/anlogic/tribuf.ys @@ -1,9 +1,9 @@ read_verilog tribuf.v -hierarchy -top top +hierarchy -top tristate proc flatten equiv_opt -assert -map +/anlogic/cells_sim.v -map +/simcells.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd tristate # Constrain all select calls below inside the top module select -assert-count 1 t:$_TBUF_ select -assert-none t:$_TBUF_ %% t:* %D -- cgit v1.2.3 From 91ad3ab717159da311b72531f4b9c77a7522702a Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 11:00:49 +0200 Subject: check ff's separately --- tests/anlogic/dffs.v | 22 ---------------------- tests/anlogic/dffs.ys | 18 ++++++++++++++---- 2 files changed, 14 insertions(+), 26 deletions(-) (limited to 'tests') diff --git a/tests/anlogic/dffs.v b/tests/anlogic/dffs.v index d97840c43..3418787c9 100644 --- a/tests/anlogic/dffs.v +++ b/tests/anlogic/dffs.v @@ -13,25 +13,3 @@ module dffe if ( en ) q <= d; endmodule - -module top ( -input clk, -input en, -input a, -output b,b1, -); - -dff u_dff ( - .clk (clk ), - .d (a ), - .q (b ) - ); - -dffe u_ndffe ( - .clk (clk ), - .en (en), - .d (a ), - .q (b1 ) - ); - -endmodule diff --git a/tests/anlogic/dffs.ys b/tests/anlogic/dffs.ys index a15c6f24e..38dffa326 100644 --- a/tests/anlogic/dffs.ys +++ b/tests/anlogic/dffs.ys @@ -1,10 +1,20 @@ read_verilog dffs.v -hierarchy -top top +design -save read + proc -flatten +hierarchy -top dff equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd dff # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_SEQ +select -assert-none t:AL_MAP_SEQ %% t:* %D + +design -load read +proc +hierarchy -top dffe +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module select -assert-count 1 t:AL_MAP_LUT3 -select -assert-count 2 t:AL_MAP_SEQ +select -assert-count 1 t:AL_MAP_SEQ select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D -- cgit v1.2.3 From 3238ee7d354aed51eb61ce5a8c2799f56f2cb4b2 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 11:04:18 +0200 Subject: check muxes per type --- tests/anlogic/mux.v | 35 ----------------------------------- tests/anlogic/mux.ys | 44 +++++++++++++++++++++++++++++++++++++------- 2 files changed, 37 insertions(+), 42 deletions(-) (limited to 'tests') diff --git a/tests/anlogic/mux.v b/tests/anlogic/mux.v index 0814b733e..27bc0bf0b 100644 --- a/tests/anlogic/mux.v +++ b/tests/anlogic/mux.v @@ -63,38 +63,3 @@ module mux16 (D, S, Y); assign Y = D[S]; endmodule - - -module top ( -input [3:0] S, -input [15:0] D, -output M2,M4,M8,M16 -); - -mux2 u_mux2 ( - .S (S[0]), - .A (D[0]), - .B (D[1]), - .Y (M2) - ); - - -mux4 u_mux4 ( - .S (S[1:0]), - .D (D[3:0]), - .Y (M4) - ); - -mux8 u_mux8 ( - .S (S[2:0]), - .D (D[7:0]), - .Y (M8) - ); - -mux16 u_mux16 ( - .S (S[3:0]), - .D (D[15:0]), - .Y (M16) - ); - -endmodule diff --git a/tests/anlogic/mux.ys b/tests/anlogic/mux.ys index 84a8bcccf..354fc836c 100644 --- a/tests/anlogic/mux.ys +++ b/tests/anlogic/mux.ys @@ -1,12 +1,42 @@ read_verilog mux.v +design -save read + +proc +hierarchy -top mux2 +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux2 # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT3 + +select -assert-none t:AL_MAP_LUT3 %% t:* %D + +design -load read +proc +hierarchy -top mux4 +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT6 + +select -assert-none t:AL_MAP_LUT6 %% t:* %D + +design -load read +proc +hierarchy -top mux8 +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 3 t:AL_MAP_LUT4 +select -assert-count 1 t:AL_MAP_LUT6 + +select -assert-none t:AL_MAP_LUT4 t:AL_MAP_LUT6 %% t:* %D + +design -load read proc -flatten +hierarchy -top mux16 equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd mux16 # Constrain all select calls below inside the top module +select -assert-count 5 t:AL_MAP_LUT6 -select -assert-count 1 t:AL_MAP_LUT3 -select -assert-count 4 t:AL_MAP_LUT4 -select -assert-count 4 t:AL_MAP_LUT5 -select -assert-count 1 t:AL_MAP_LUT6 -select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_LUT6 %% t:* %D +select -assert-none t:AL_MAP_LUT6 %% t:* %D -- cgit v1.2.3 From a5844e3ceb76152d1e87ad8fdf1c71553238ef64 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 11:08:42 +0200 Subject: split latches into separate checks --- tests/anlogic/latches.v | 34 ---------------------------------- tests/anlogic/latches.ys | 31 ++++++++++++++++++++++++------- 2 files changed, 24 insertions(+), 41 deletions(-) (limited to 'tests') diff --git a/tests/anlogic/latches.v b/tests/anlogic/latches.v index 9dc43e4c2..adb5d5319 100644 --- a/tests/anlogic/latches.v +++ b/tests/anlogic/latches.v @@ -22,37 +22,3 @@ module latchsr else if ( en ) q <= d; endmodule - - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2 -); - - -latchp u_latchp ( - .en (clk ), - .d (a ), - .q (b ) - ); - - -latchn u_latchn ( - .en (clk ), - .d (a ), - .q (b1 ) - ); - - -latchsr u_latchsr ( - .en (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b2 ) - ); - -endmodule diff --git a/tests/anlogic/latches.ys b/tests/anlogic/latches.ys index b5e52cf16..ae9e15ff8 100644 --- a/tests/anlogic/latches.ys +++ b/tests/anlogic/latches.ys @@ -2,15 +2,32 @@ read_verilog latches.v design -save read proc -async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock -flatten +hierarchy -top latchp +# Can't run any sort of equivalence check because latches are blown to LUTs synth_anlogic -equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd latchp # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT3 + +select -assert-none t:AL_MAP_LUT3 %% t:* %D + + +design -load read +proc +hierarchy -top latchn +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_anlogic +cd latchn # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT3 + +select -assert-none t:AL_MAP_LUT3 %% t:* %D + design -load read +proc +hierarchy -top latchsr +# Can't run any sort of equivalence check because latches are blown to LUTs synth_anlogic -cd top -select -assert-count 2 t:AL_MAP_LUT3 +cd latchsr # Constrain all select calls below inside the top module select -assert-count 1 t:AL_MAP_LUT5 -select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT5 %% t:* %D + +select -assert-none t:AL_MAP_LUT5 %% t:* %D -- cgit v1.2.3 From 03a3deec43ef4e92b251ea4bceaadc77c8044df0 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 11:09:59 +0200 Subject: Cleanup and formating --- tests/anlogic/add_sub.ys | 2 +- tests/anlogic/counter.ys | 2 +- tests/anlogic/fsm.ys | 1 + tests/anlogic/shifter.ys | 1 + 4 files changed, 4 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/anlogic/add_sub.ys b/tests/anlogic/add_sub.ys index 55c090506..994cd0d03 100644 --- a/tests/anlogic/add_sub.ys +++ b/tests/anlogic/add_sub.ys @@ -5,5 +5,5 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd top # Constrain all select calls below inside the top module select -assert-count 10 t:AL_MAP_ADDER select -assert-count 4 t:AL_MAP_LUT1 -select -assert-none t:AL_MAP_LUT1 t:AL_MAP_ADDER %% t:* %D +select -assert-none t:AL_MAP_LUT1 t:AL_MAP_ADDER %% t:* %D diff --git a/tests/anlogic/counter.ys b/tests/anlogic/counter.ys index 5210221e3..036fdba46 100644 --- a/tests/anlogic/counter.ys +++ b/tests/anlogic/counter.ys @@ -8,4 +8,4 @@ cd top # Constrain all select calls below inside the top module select -assert-count 9 t:AL_MAP_ADDER select -assert-count 8 t:AL_MAP_SEQ -select -assert-none t:SB_CARRY t:AL_MAP_SEQ t:AL_MAP_ADDER %% t:* %D +select -assert-none t:AL_MAP_SEQ t:AL_MAP_ADDER %% t:* %D diff --git a/tests/anlogic/fsm.ys b/tests/anlogic/fsm.ys index 76a5d3e43..452ef9251 100644 --- a/tests/anlogic/fsm.ys +++ b/tests/anlogic/fsm.ys @@ -11,4 +11,5 @@ select -assert-count 1 t:AL_MAP_LUT2 select -assert-count 5 t:AL_MAP_LUT5 select -assert-count 1 t:AL_MAP_LUT6 select -assert-count 6 t:AL_MAP_SEQ + select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D diff --git a/tests/anlogic/shifter.ys b/tests/anlogic/shifter.ys index edd89b344..5eaed30a3 100644 --- a/tests/anlogic/shifter.ys +++ b/tests/anlogic/shifter.ys @@ -6,4 +6,5 @@ equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 8 t:AL_MAP_SEQ + select -assert-none t:AL_MAP_SEQ %% t:* %D -- cgit v1.2.3 From 5c68da4150f8e5367138f2c7187f707b20cc19db Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sat, 5 Oct 2019 09:27:12 -0700 Subject: Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf --- tests/ice40/wrapcarry.ys | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 tests/ice40/wrapcarry.ys (limited to 'tests') diff --git a/tests/ice40/wrapcarry.ys b/tests/ice40/wrapcarry.ys new file mode 100644 index 000000000..10c029e68 --- /dev/null +++ b/tests/ice40/wrapcarry.ys @@ -0,0 +1,22 @@ +read_verilog < Date: Tue, 8 Oct 2019 12:41:26 -0700 Subject: Revert "Add test that is expecting to fail" This reverts commit c28d4b804720c2cf0086e921748219150e9631b5. --- tests/sat/initval.ys | 20 -------------------- 1 file changed, 20 deletions(-) (limited to 'tests') diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys index 1627a37e3..2079d2f34 100644 --- a/tests/sat/initval.ys +++ b/tests/sat/initval.ys @@ -2,23 +2,3 @@ read_verilog -sv initval.v proc;; sat -seq 10 -prove-asserts - -read_verilog < Date: Mon, 9 Sep 2019 08:33:26 +0300 Subject: Add tests for Xilinx UG901 examples --- tests/xilinx_ug901/asym_ram_sdp_read_wider.v | 74 +++++++++++++ tests/xilinx_ug901/asym_ram_sdp_read_wider.ys | 22 ++++ tests/xilinx_ug901/asym_ram_sdp_write_wider.v | 75 +++++++++++++ tests/xilinx_ug901/asym_ram_sdp_write_wider.ys | 31 ++++++ tests/xilinx_ug901/asym_ram_tdp_read_first.v | 85 ++++++++++++++ tests/xilinx_ug901/asym_ram_tdp_read_first.ys | 21 ++++ tests/xilinx_ug901/asym_ram_tdp_write_first.v | 92 ++++++++++++++++ tests/xilinx_ug901/asym_ram_tdp_write_first.ys | 29 +++++ tests/xilinx_ug901/black_box_1.v | 19 ++++ tests/xilinx_ug901/black_box_1.ys | 15 +++ tests/xilinx_ug901/bytewrite_ram_1b.v | 42 +++++++ tests/xilinx_ug901/bytewrite_ram_1b.ys | 22 ++++ tests/xilinx_ug901/bytewrite_tdp_ram_nc.v | 78 +++++++++++++ tests/xilinx_ug901/bytewrite_tdp_ram_nc.ys | 22 ++++ tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.v | 71 ++++++++++++ tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.ys | 21 ++++ tests/xilinx_ug901/bytewrite_tdp_ram_rf.v | 61 +++++++++++ tests/xilinx_ug901/bytewrite_tdp_ram_rf.ys | 21 ++++ tests/xilinx_ug901/bytewrite_tdp_ram_wf.v | 68 ++++++++++++ tests/xilinx_ug901/bytewrite_tdp_ram_wf.ys | 23 ++++ tests/xilinx_ug901/cmacc.v | 122 +++++++++++++++++++++ tests/xilinx_ug901/cmacc.ys | 25 +++++ tests/xilinx_ug901/cmult.v | 71 ++++++++++++ tests/xilinx_ug901/cmult.ys | 31 ++++++ tests/xilinx_ug901/dynamic_shift_registers_1.v | 21 ++++ tests/xilinx_ug901/dynamic_shift_registers_1.ys | 15 +++ tests/xilinx_ug901/dynpreaddmultadd.v | 47 ++++++++ tests/xilinx_ug901/dynpreaddmultadd.ys | 31 ++++++ tests/xilinx_ug901/fsm_1.v | 42 +++++++ tests/xilinx_ug901/fsm_1.ys | 16 +++ tests/xilinx_ug901/latches.v | 17 +++ tests/xilinx_ug901/latches.ys | 10 ++ tests/xilinx_ug901/macc.v | 47 ++++++++ tests/xilinx_ug901/macc.ys | 23 ++++ tests/xilinx_ug901/mult_unsigned.v | 33 ++++++ tests/xilinx_ug901/mult_unsigned.ys | 29 +++++ tests/xilinx_ug901/presubmult.v | 43 ++++++++ tests/xilinx_ug901/presubmult.ys | 23 ++++ tests/xilinx_ug901/ram_simple_dual_one_clock.v | 25 +++++ tests/xilinx_ug901/ram_simple_dual_one_clock.ys | 20 ++++ tests/xilinx_ug901/ram_simple_dual_two_clocks.v | 30 +++++ tests/xilinx_ug901/ram_simple_dual_two_clocks.ys | 20 ++++ tests/xilinx_ug901/rams_dist.v | 24 ++++ tests/xilinx_ug901/rams_dist.ys | 21 ++++ tests/xilinx_ug901/rams_init_file.data | 64 +++++++++++ tests/xilinx_ug901/rams_init_file.v | 24 ++++ tests/xilinx_ug901/rams_init_file.ys | 22 ++++ tests/xilinx_ug901/rams_pipeline.v | 42 +++++++ tests/xilinx_ug901/rams_pipeline.ys | 22 ++++ tests/xilinx_ug901/rams_sp_nc.v | 26 +++++ tests/xilinx_ug901/rams_sp_nc.ys | 22 ++++ tests/xilinx_ug901/rams_sp_rf.v | 26 +++++ tests/xilinx_ug901/rams_sp_rf.ys | 22 ++++ tests/xilinx_ug901/rams_sp_rf_rst.v | 29 +++++ tests/xilinx_ug901/rams_sp_rf_rst.ys | 28 +++++ tests/xilinx_ug901/rams_sp_rom.v | 46 ++++++++ tests/xilinx_ug901/rams_sp_rom.ys | 22 ++++ tests/xilinx_ug901/rams_sp_rom_1.v | 53 +++++++++ tests/xilinx_ug901/rams_sp_rom_1.ys | 22 ++++ tests/xilinx_ug901/rams_sp_wf.v | 26 +++++ tests/xilinx_ug901/rams_sp_wf.ys | 26 +++++ tests/xilinx_ug901/rams_tdp_rf_rf.v | 33 ++++++ tests/xilinx_ug901/rams_tdp_rf_rf.ys | 21 ++++ tests/xilinx_ug901/registers_1.v | 25 +++++ tests/xilinx_ug901/registers_1.ys | 12 ++ tests/xilinx_ug901/run-test.sh | 20 ++++ tests/xilinx_ug901/sfir_shifter.v | 19 ++++ tests/xilinx_ug901/sfir_shifter.ys | 16 +++ tests/xilinx_ug901/shift_registers_0.v | 22 ++++ tests/xilinx_ug901/shift_registers_0.ys | 13 +++ tests/xilinx_ug901/shift_registers_1.v | 24 ++++ tests/xilinx_ug901/shift_registers_1.ys | 14 +++ tests/xilinx_ug901/squarediffmacc.v | 52 +++++++++ tests/xilinx_ug901/squarediffmacc.ys | 23 ++++ tests/xilinx_ug901/squarediffmult.v | 42 +++++++ tests/xilinx_ug901/squarediffmult.ys | 30 +++++ tests/xilinx_ug901/top_mux.v | 18 +++ tests/xilinx_ug901/top_mux.ys | 13 +++ tests/xilinx_ug901/tristates_1.v | 17 +++ tests/xilinx_ug901/tristates_1.ys | 13 +++ tests/xilinx_ug901/tristates_2.v | 10 ++ tests/xilinx_ug901/tristates_2.ys | 13 +++ .../xilinx_ultraram_single_port_no_change.v | 78 +++++++++++++ .../xilinx_ultraram_single_port_no_change.ys | 25 +++++ .../xilinx_ultraram_single_port_read_first.v | 78 +++++++++++++ .../xilinx_ultraram_single_port_read_first.ys | 24 ++++ .../xilinx_ultraram_single_port_write_first.v | 82 ++++++++++++++ .../xilinx_ultraram_single_port_write_first.ys | 24 ++++ 88 files changed, 2961 insertions(+) create mode 100644 tests/xilinx_ug901/asym_ram_sdp_read_wider.v create mode 100644 tests/xilinx_ug901/asym_ram_sdp_read_wider.ys create mode 100644 tests/xilinx_ug901/asym_ram_sdp_write_wider.v create mode 100644 tests/xilinx_ug901/asym_ram_sdp_write_wider.ys create mode 100644 tests/xilinx_ug901/asym_ram_tdp_read_first.v create mode 100644 tests/xilinx_ug901/asym_ram_tdp_read_first.ys create mode 100644 tests/xilinx_ug901/asym_ram_tdp_write_first.v create mode 100644 tests/xilinx_ug901/asym_ram_tdp_write_first.ys create mode 100644 tests/xilinx_ug901/black_box_1.v create mode 100644 tests/xilinx_ug901/black_box_1.ys create mode 100644 tests/xilinx_ug901/bytewrite_ram_1b.v create mode 100644 tests/xilinx_ug901/bytewrite_ram_1b.ys create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_nc.v create mode 100644 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tests/xilinx_ug901/xilinx_ultraram_single_port_read_first.v create mode 100644 tests/xilinx_ug901/xilinx_ultraram_single_port_read_first.ys create mode 100644 tests/xilinx_ug901/xilinx_ultraram_single_port_write_first.v create mode 100644 tests/xilinx_ug901/xilinx_ultraram_single_port_write_first.ys (limited to 'tests') diff --git a/tests/xilinx_ug901/asym_ram_sdp_read_wider.v b/tests/xilinx_ug901/asym_ram_sdp_read_wider.v new file mode 100644 index 000000000..0716dffdc --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_sdp_read_wider.v @@ -0,0 +1,74 @@ +// Asymmetric port RAM +// Read Wider than Write. Read Statement in loop +//asym_ram_sdp_read_wider.v + +module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA, doB); +parameter WIDTHA = 4; +parameter SIZEA = 1024; +parameter ADDRWIDTHA = 10; + +parameter WIDTHB = 16; +parameter SIZEB = 256; +parameter ADDRWIDTHB = 8; +input clkA; +input clkB; +input weA; +input enaA, enaB; +input [ADDRWIDTHA-1:0] addrA; +input [ADDRWIDTHB-1:0] addrB; +input [WIDTHA-1:0] diA; +output [WIDTHB-1:0] doB; +`define max(a,b) {(a) > (b) ? (a) : (b)} +`define min(a,b) {(a) < (b) ? (a) : (b)} + +function integer log2; +input integer value; +reg [31:0] shifted; +integer res; +begin + if (value < 2) + log2 = value; + else + begin + shifted = value-1; + for (res=0; shifted>0; res=res+1) + shifted = shifted>>1; + log2 = res; + end +end +endfunction + +localparam maxSIZE = `max(SIZEA, SIZEB); +localparam maxWIDTH = `max(WIDTHA, WIDTHB); +localparam minWIDTH = `min(WIDTHA, WIDTHB); + +localparam RATIO = maxWIDTH / minWIDTH; +localparam log2RATIO = log2(RATIO); + +reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; +reg [WIDTHB-1:0] readB; + +always @(posedge clkA) +begin + if (enaA) begin + if (weA) + RAM[addrA] <= diA; + end +end + + +always @(posedge clkB) +begin : ramread + integer i; + reg [log2RATIO-1:0] lsbaddr; + if (enaB) begin + for (i = 0; i < RATIO; i = i+1) begin + lsbaddr = i; + readB[(i+1)*minWIDTH-1 -: minWIDTH] <= RAM[{addrB, lsbaddr}]; + end + end +end +assign doB = readB; + +endmodule + diff --git a/tests/xilinx_ug901/asym_ram_sdp_read_wider.ys b/tests/xilinx_ug901/asym_ram_sdp_read_wider.ys new file mode 100644 index 000000000..c63157cdf --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_sdp_read_wider.ys @@ -0,0 +1,22 @@ +read_verilog asym_ram_sdp_read_wider.v +hierarchy -top asym_ram_sdp_read_wider +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd asym_ram_sdp_read_wider +stat +#Vivado synthesizes 1 RAMB18E1. +select -assert-count 2 t:BUFG +select -assert-count 1 t:LUT2 +select -assert-count 4 t:RAMB18E1 + +select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D diff --git a/tests/xilinx_ug901/asym_ram_sdp_write_wider.v b/tests/xilinx_ug901/asym_ram_sdp_write_wider.v new file mode 100644 index 000000000..22d12d2ce --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_sdp_write_wider.v @@ -0,0 +1,75 @@ +// Asymmetric port RAM +// Write wider than Read. Write Statement in a loop. +// asym_ram_sdp_write_wider.v + +module asym_ram_sdp_write_wider (clkA, clkB, weA, enaA, enaB, addrA, addrB, diA, doB); +parameter WIDTHB = 4; +//Default parameters were changed because of slow test +//parameter SIZEB = 1024; +//parameter ADDRWIDTHB = 10; +parameter SIZEB = 256; +parameter ADDRWIDTHB = 8; + +//parameter WIDTHA = 16; +parameter WIDTHA = 8; +parameter SIZEA = 256; +parameter ADDRWIDTHA = 8; +input clkA; +input clkB; +input weA; +input enaA, enaB; +input [ADDRWIDTHA-1:0] addrA; +input [ADDRWIDTHB-1:0] addrB; +input [WIDTHA-1:0] diA; +output [WIDTHB-1:0] doB; +`define max(a,b) {(a) > (b) ? (a) : (b)} +`define min(a,b) {(a) < (b) ? (a) : (b)} + +function integer log2; +input integer value; +reg [31:0] shifted; +integer res; +begin + if (value < 2) + log2 = value; + else + begin + shifted = value-1; + for (res=0; shifted>0; res=res+1) + shifted = shifted>>1; + log2 = res; + end +end +endfunction + +localparam maxSIZE = `max(SIZEA, SIZEB); +localparam maxWIDTH = `max(WIDTHA, WIDTHB); +localparam minWIDTH = `min(WIDTHA, WIDTHB); + +localparam RATIO = maxWIDTH / minWIDTH; +localparam log2RATIO = log2(RATIO); + +reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; +reg [WIDTHB-1:0] readB; + +always @(posedge clkB) begin + if (enaB) begin + readB <= RAM[addrB]; + end +end +assign doB = readB; + +always @(posedge clkA) +begin : ramwrite + integer i; + reg [log2RATIO-1:0] lsbaddr; + for (i=0; i< RATIO; i= i+ 1) begin : write1 + lsbaddr = i; + if (enaA) begin + if (weA) + RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH]; + end + end +end + +endmodule diff --git a/tests/xilinx_ug901/asym_ram_sdp_write_wider.ys b/tests/xilinx_ug901/asym_ram_sdp_write_wider.ys new file mode 100644 index 000000000..229d98df6 --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_sdp_write_wider.ys @@ -0,0 +1,31 @@ +read_verilog asym_ram_sdp_write_wider.v +hierarchy -top asym_ram_sdp_write_wider +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd asym_ram_sdp_write_wider +stat +#Vivado synthesizes 1 RAMB18E1. +select -assert-count 2 t:BUFG +select -assert-count 1028 t:FDRE +select -assert-count 170 t:LUT2 +select -assert-count 6 t:LUT3 +select -assert-count 518 t:LUT4 +select -assert-count 10 t:LUT5 +select -assert-count 484 t:LUT6 +select -assert-count 157 t:MUXF7 +select -assert-count 3 t:MUXF8 + +#RRAM128X1D will be synthesized in case when the parameter WIDTHA=4 +#select -assert-count 8 t:RAM128X1D + +select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D diff --git a/tests/xilinx_ug901/asym_ram_tdp_read_first.v b/tests/xilinx_ug901/asym_ram_tdp_read_first.v new file mode 100644 index 000000000..2b807a382 --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_tdp_read_first.v @@ -0,0 +1,85 @@ +// Asymetric RAM - TDP +// READ_FIRST MODE. +// asym_ram_tdp_read_first.v + + +module asym_ram_tdp_read_first (clkA, clkB, enaA, weA, enaB, weB, addrA, addrB, diA, doA, diB, doB); +parameter WIDTHB = 4; +parameter SIZEB = 1024; +parameter ADDRWIDTHB = 10; +parameter WIDTHA = 16; +parameter SIZEA = 256; +parameter ADDRWIDTHA = 8; +input clkA; +input clkB; +input weA, weB; +input enaA, enaB; + +input [ADDRWIDTHA-1:0] addrA; +input [ADDRWIDTHB-1:0] addrB; +input [WIDTHA-1:0] diA; +input [WIDTHB-1:0] diB; + +output [WIDTHA-1:0] doA; +output [WIDTHB-1:0] doB; + +`define max(a,b) {(a) > (b) ? (a) : (b)} +`define min(a,b) {(a) < (b) ? (a) : (b)} + +function integer log2; +input integer value; +reg [31:0] shifted; +integer res; +begin + if (value < 2) + log2 = value; + else + begin + shifted = value-1; + for (res=0; shifted>0; res=res+1) + shifted = shifted>>1; + log2 = res; + end +end +endfunction + +localparam maxSIZE = `max(SIZEA, SIZEB); +localparam maxWIDTH = `max(WIDTHA, WIDTHB); +localparam minWIDTH = `min(WIDTHA, WIDTHB); + +localparam RATIO = maxWIDTH / minWIDTH; +localparam log2RATIO = log2(RATIO); + +reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; +reg [WIDTHA-1:0] readA; +reg [WIDTHB-1:0] readB; + +always @(posedge clkB) +begin + if (enaB) begin + readB <= RAM[addrB] ; + if (weB) + RAM[addrB] <= diB; + end +end + + +always @(posedge clkA) +begin : portA + integer i; + reg [log2RATIO-1:0] lsbaddr ; + for (i=0; i< RATIO; i= i+ 1) begin + lsbaddr = i; + if (enaA) begin + readA[(i+1)*minWIDTH -1 -: minWIDTH] <= RAM[{addrA, lsbaddr}]; + + if (weA) + RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH]; + end + end +end + +assign doA = readA; +assign doB = readB; + +endmodule diff --git a/tests/xilinx_ug901/asym_ram_tdp_read_first.ys b/tests/xilinx_ug901/asym_ram_tdp_read_first.ys new file mode 100644 index 000000000..5f96b800c --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_tdp_read_first.ys @@ -0,0 +1,21 @@ +read_verilog asym_ram_tdp_read_first.v +hierarchy -top asym_ram_tdp_read_first +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd asym_ram_tdp_read_first +stat +#Vivado synthesizes 1 RAMB18E1. +select -assert-count 1 t:$mem +select -assert-count 2 t:LUT2 + +select -assert-none t:$mem t:LUT2 %% t:* %D diff --git a/tests/xilinx_ug901/asym_ram_tdp_write_first.v b/tests/xilinx_ug901/asym_ram_tdp_write_first.v new file mode 100644 index 000000000..90187ea26 --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_tdp_write_first.v @@ -0,0 +1,92 @@ +// Asymmetric port RAM - TDP +// WRITE_FIRST MODE. +// asym_ram_tdp_write_first.v + + +module asym_ram_tdp_write_first (clkA, clkB, enaA, weA, enaB, weB, addrA, addrB, diA, doA, diB, doB); +parameter WIDTHB = 4; +//Default parameters were changed because of slow test +//parameter SIZEB = 1024; +//parameter ADDRWIDTHB = 10; +parameter SIZEB = 32; +parameter ADDRWIDTHB = 8; + +//parameter WIDTHA = 16; +parameter WIDTHA = 4; +//parameter SIZEA = 256; +parameter SIZEA = 32; +parameter ADDRWIDTHA = 8; +input clkA; +input clkB; +input weA, weB; +input enaA, enaB; + +input [ADDRWIDTHA-1:0] addrA; +input [ADDRWIDTHB-1:0] addrB; +input [WIDTHA-1:0] diA; +input [WIDTHB-1:0] diB; + +output [WIDTHA-1:0] doA; +output [WIDTHB-1:0] doB; + +`define max(a,b) {(a) > (b) ? (a) : (b)} +`define min(a,b) {(a) < (b) ? (a) : (b)} + +function integer log2; +input integer value; +reg [31:0] shifted; +integer res; +begin + if (value < 2) + log2 = value; + else + begin + shifted = value-1; + for (res=0; shifted>0; res=res+1) + shifted = shifted>>1; + log2 = res; + end +end +endfunction + +localparam maxSIZE = `max(SIZEA, SIZEB); +localparam maxWIDTH = `max(WIDTHA, WIDTHB); +localparam minWIDTH = `min(WIDTHA, WIDTHB); + +localparam RATIO = maxWIDTH / minWIDTH; +localparam log2RATIO = log2(RATIO); + +reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; +reg [WIDTHA-1:0] readA; +reg [WIDTHB-1:0] readB; + +always @(posedge clkB) +begin + if (enaB) begin + if (weB) + RAM[addrB] = diB; + readB = RAM[addrB] ; + end +end + + +always @(posedge clkA) +begin : portA + integer i; + reg [log2RATIO-1:0] lsbaddr ; + for (i=0; i< RATIO; i= i+ 1) begin + lsbaddr = i; + if (enaA) begin + + if (weA) + RAM[{addrA, lsbaddr}] = diA[(i+1)*minWIDTH-1 -: minWIDTH]; + + readA[(i+1)*minWIDTH -1 -: minWIDTH] = RAM[{addrA, lsbaddr}]; + end + end +end + +assign doA = readA; +assign doB = readB; + +endmodule diff --git a/tests/xilinx_ug901/asym_ram_tdp_write_first.ys b/tests/xilinx_ug901/asym_ram_tdp_write_first.ys new file mode 100644 index 000000000..bbe3cc849 --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_tdp_write_first.ys @@ -0,0 +1,29 @@ +read_verilog asym_ram_tdp_write_first.v +hierarchy -top asym_ram_tdp_write_first +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd asym_ram_tdp_write_first +stat +#Vivado synthesizes 1 RAMB18E1. +select -assert-count 2 t:BUFG +select -assert-count 200 t:FDRE +select -assert-count 10 t:LUT2 +select -assert-count 44 t:LUT3 +select -assert-count 81 t:LUT4 +select -assert-count 104 t:LUT5 +select -assert-count 560 t:LUT6 +select -assert-count 261 t:MUXF7 +select -assert-count 127 t:MUXF8 + + +select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D diff --git a/tests/xilinx_ug901/black_box_1.v b/tests/xilinx_ug901/black_box_1.v new file mode 100644 index 000000000..40caa1b10 --- /dev/null +++ b/tests/xilinx_ug901/black_box_1.v @@ -0,0 +1,19 @@ +// Black Box +// black_box_1.v +// +(* black_box *) module black_box1 (in1, in2, dout); +input in1, in2; +output dout; +endmodule + +module black_box_1 (DI_1, DI_2, DOUT); +input DI_1, DI_2; +output DOUT; + +black_box1 U1 ( + .in1(DI_1), + .in2(DI_2), + .dout(DOUT) + ); + +endmodule diff --git a/tests/xilinx_ug901/black_box_1.ys b/tests/xilinx_ug901/black_box_1.ys new file mode 100644 index 000000000..acf0b5761 --- /dev/null +++ b/tests/xilinx_ug901/black_box_1.ys @@ -0,0 +1,15 @@ +read_verilog black_box_1.v +hierarchy -top black_box_1 +proc +tribuf +flatten +synth +#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd black_box_1 # Constrain all select calls below inside the top module +#Vivado synthesizes 1 black box. +#stat +#select -assert-count 0 t:LUT1 +#select -assert-count 1 t:$_TBUF_ +#select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D diff --git a/tests/xilinx_ug901/bytewrite_ram_1b.v b/tests/xilinx_ug901/bytewrite_ram_1b.v new file mode 100644 index 000000000..46d86c297 --- /dev/null +++ b/tests/xilinx_ug901/bytewrite_ram_1b.v @@ -0,0 +1,42 @@ +// Single-Port BRAM with Byte-wide Write Enable +// Read-First mode +// Single-process description +// Compact description of the write with a generate-for +// statement +// Column width and number of columns easily configurable +// +// bytewrite_ram_1b.v +// + +module bytewrite_ram_1b (clk, we, addr, di, do); + +parameter SIZE = 1024; +parameter ADDR_WIDTH = 10; +parameter COL_WIDTH = 8; +parameter NB_COL = 4; + +input clk; +input [NB_COL-1:0] we; +input [ADDR_WIDTH-1:0] addr; +input [NB_COL*COL_WIDTH-1:0] di; +output reg [NB_COL*COL_WIDTH-1:0] do; + +reg [NB_COL*COL_WIDTH-1:0] RAM [SIZE-1:0]; + +always @(posedge clk) +begin + do <= RAM[addr]; +end + +generate genvar i; +for (i = 0; i < NB_COL; i = i+1) +begin +always @(posedge clk) +begin + if (we[i]) + RAM[addr][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= di[(i+1)*COL_WIDTH-1:i*COL_WIDTH]; + end +end +endgenerate + +endmodule diff --git a/tests/xilinx_ug901/bytewrite_ram_1b.ys b/tests/xilinx_ug901/bytewrite_ram_1b.ys new file mode 100644 index 000000000..4f0967801 --- /dev/null +++ b/tests/xilinx_ug901/bytewrite_ram_1b.ys @@ -0,0 +1,22 @@ +read_verilog bytewrite_ram_1b.v +hierarchy -top bytewrite_ram_1b +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd bytewrite_ram_1b +stat +#Vivado synthesizes 1 RAMB36E1. +select -assert-count 1 t:BUFG +select -assert-count 32 t:LUT2 +select -assert-count 8 t:RAMB36E1 + +select -assert-none t:BUFG t:LUT2 t:RAMB36E1 %% t:* %D diff --git a/tests/xilinx_ug901/bytewrite_tdp_ram_nc.v b/tests/xilinx_ug901/bytewrite_tdp_ram_nc.v new file mode 100644 index 000000000..1093b0838 --- /dev/null +++ b/tests/xilinx_ug901/bytewrite_tdp_ram_nc.v @@ -0,0 +1,78 @@ +// +// True-Dual-Port BRAM with Byte-wide Write Enable +// No-Change mode +// +// bytewrite_tdp_ram_nc.v +// +// ByteWide Write Enable, - NO_CHANGE mode template - Vivado recomended +module bytewrite_tdp_ram_nc + #( + //--------------------------------------------------------------- + parameter NUM_COL = 4, + parameter COL_WIDTH = 8, + parameter ADDR_WIDTH = 10, // Addr Width in bits : 2**ADDR_WIDTH = RAM Depth + parameter DATA_WIDTH = NUM_COL*COL_WIDTH // Data Width in bits + //--------------------------------------------------------------- + ) ( + input clkA, + input enaA, + input [NUM_COL-1:0] weA, + input [ADDR_WIDTH-1:0] addrA, + input [DATA_WIDTH-1:0] dinA, + output reg [DATA_WIDTH-1:0] doutA, + + input clkB, + input enaB, + input [NUM_COL-1:0] weB, + input [ADDR_WIDTH-1:0] addrB, + input [DATA_WIDTH-1:0] dinB, + output reg [DATA_WIDTH-1:0] doutB + ); + + + // Core Memory + reg [DATA_WIDTH-1:0] ram_block [(2**ADDR_WIDTH)-1:0]; + + // Port-A Operation + generate + genvar i; + for(i=0;i run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/xilinx_ug901/sfir_shifter.v b/tests/xilinx_ug901/sfir_shifter.v new file mode 100644 index 000000000..a8b144bcd --- /dev/null +++ b/tests/xilinx_ug901/sfir_shifter.v @@ -0,0 +1,19 @@ +//sfir_shifter.v +(* dont_touch = "yes" *) +module sfir_shifter #(parameter dsize = 16, nbtap = 4) + (input clk,input [dsize-1:0] datain, output [dsize-1:0] dataout); + + (* srl_style = "srl_register" *) reg [dsize-1:0] tmp [0:2*nbtap-1]; + integer i; + + always @(posedge clk) + begin + tmp[0] <= datain; + for (i=0; i<=2*nbtap-2; i=i+1) + tmp[i+1] <= tmp[i]; + end + + assign dataout = tmp[2*nbtap-1]; + +endmodule +// sfir_shifter diff --git a/tests/xilinx_ug901/sfir_shifter.ys b/tests/xilinx_ug901/sfir_shifter.ys new file mode 100644 index 000000000..b9fbeb8cb --- /dev/null +++ b/tests/xilinx_ug901/sfir_shifter.ys @@ -0,0 +1,16 @@ +read_verilog sfir_shifter.v +hierarchy -top sfir_shifter +proc +flatten +#ERROR: Found 32 unproven $equiv cells in 'equiv_status -assert'. +#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) + +cd sfir_shifter +#Vivado synthesizes 32 FDRE, 16 SRL16E. +stat +select -assert-count 1 t:BUFG +select -assert-count 16 t:SRL16E + +select -assert-none t:BUFG t:SRL16E %% t:* %D diff --git a/tests/xilinx_ug901/shift_registers_0.v b/tests/xilinx_ug901/shift_registers_0.v new file mode 100644 index 000000000..77a3ec893 --- /dev/null +++ b/tests/xilinx_ug901/shift_registers_0.v @@ -0,0 +1,22 @@ +// 8-bit Shift Register +// Rising edge clock +// Active high clock enable +// Concatenation-based template +// File: shift_registers_0.v + +module shift_registers_0 (clk, clken, SI, SO); +parameter WIDTH = 32; +input clk, clken, SI; +output SO; + +reg [WIDTH-1:0] shreg; + +always @(posedge clk) + begin + if (clken) + shreg = {shreg[WIDTH-2:0], SI}; + end + +assign SO = shreg[WIDTH-1]; + +endmodule diff --git a/tests/xilinx_ug901/shift_registers_0.ys b/tests/xilinx_ug901/shift_registers_0.ys new file mode 100644 index 000000000..ae7d23a7f --- /dev/null +++ b/tests/xilinx_ug901/shift_registers_0.ys @@ -0,0 +1,13 @@ +read_verilog shift_registers_0.v +hierarchy -top shift_registers_0 +proc +flatten +#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check + +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd shift_registers_0 # Constrain all select calls below inside the top module +#Vivado synthesizes 1 BUFG, 2 FDRE, 3 SRLC32E. +select -assert-count 1 t:BUFG +select -assert-count 1 t:SRLC32E +select -assert-none t:BUFG t:SRLC32E %% t:* %D diff --git a/tests/xilinx_ug901/shift_registers_1.v b/tests/xilinx_ug901/shift_registers_1.v new file mode 100644 index 000000000..d50820e7b --- /dev/null +++ b/tests/xilinx_ug901/shift_registers_1.v @@ -0,0 +1,24 @@ +// 32-bit Shift Register +// Rising edge clock +// Active high clock enable +// For-loop based template +// File: shift_registers_1.v + +module shift_registers_1 (clk, clken, SI, SO); +parameter WIDTH = 32; +input clk, clken, SI; +output SO; +reg [WIDTH-1:0] shreg; + +integer i; +always @(posedge clk) +begin + if (clken) + begin + for (i = 0; i < WIDTH-1; i = i+1) + shreg[i+1] <= shreg[i]; + shreg[0] <= SI; + end +end +assign SO = shreg[WIDTH-1]; +endmodule diff --git a/tests/xilinx_ug901/shift_registers_1.ys b/tests/xilinx_ug901/shift_registers_1.ys new file mode 100644 index 000000000..fb935c446 --- /dev/null +++ b/tests/xilinx_ug901/shift_registers_1.ys @@ -0,0 +1,14 @@ +read_verilog shift_registers_1.v +hierarchy -top shift_registers_1 +proc +flatten + +#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check + +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd shift_registers_1 # Constrain all select calls below inside the top module +#Vivado synthesizes 1 BUFG, 2 FDRE, 3 SRLC32E. +select -assert-count 1 t:BUFG +select -assert-count 1 t:SRLC32E +select -assert-none t:BUFG t:SRLC32E %% t:* %D diff --git a/tests/xilinx_ug901/squarediffmacc.v b/tests/xilinx_ug901/squarediffmacc.v new file mode 100644 index 000000000..6535b24c4 --- /dev/null +++ b/tests/xilinx_ug901/squarediffmacc.v @@ -0,0 +1,52 @@ +// This module performs subtraction of two inputs, squaring on the diff +// and then accumulation +// This can be implemented in 1 DSP Block (Ultrascale architecture) +// File : squarediffmacc.v +module squarediffmacc # ( + //Default parameters were changed because of slow test + //parameter SIZEIN = 16, + //SIZEOUT = 40 + parameter SIZEIN = 8, + SIZEOUT = 20 + ) + ( + input clk, + input ce, + input sload, + input signed [SIZEIN-1:0] a, + input signed [SIZEIN-1:0] b, + output signed [SIZEOUT+1:0] accum_out + ); + +// Declare registers for intermediate values +reg signed [SIZEIN-1:0] a_reg, b_reg; +reg signed [SIZEIN:0] diff_reg; +reg sload_reg; +reg signed [2*SIZEIN+1:0] m_reg; +reg signed [SIZEOUT-1:0] adder_out, old_result; + + always @(sload_reg or adder_out) + if (sload_reg) + old_result <= 0; + else + // 'sload' is now and opens the accumulation loop. + // The accumulator takes the next multiplier output + // in the same cycle. + old_result <= adder_out; + + always @(posedge clk) + if (ce) + begin + a_reg <= a; + b_reg <= b; + diff_reg <= a_reg - b_reg; + m_reg <= diff_reg * diff_reg; + sload_reg <= sload; + // Store accumulation result into a register + adder_out <= old_result + m_reg; + end + + // Output accumulation result + assign accum_out = adder_out; + +endmodule // squarediffmacc diff --git a/tests/xilinx_ug901/squarediffmacc.ys b/tests/xilinx_ug901/squarediffmacc.ys new file mode 100644 index 000000000..92474bea3 --- /dev/null +++ b/tests/xilinx_ug901/squarediffmacc.ys @@ -0,0 +1,23 @@ +read_verilog squarediffmacc.v +hierarchy -top squarediffmacc +proc +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) + +cd squarediffmacc +#Vivado synthesizes 1 DSP48E1, 33 FDRE, 16 LUT. +stat +select -assert-count 1 t:BUFG +select -assert-count 64 t:FDRE +select -assert-count 78 t:LUT2 +select -assert-count 7 t:LUT3 +select -assert-count 11 t:LUT4 +select -assert-count 8 t:LUT5 +select -assert-count 125 t:LUT6 +select -assert-count 44 t:MUXCY +select -assert-count 50 t:MUXF7 +select -assert-count 17 t:MUXF8 +select -assert-count 47 t:XORCY + +select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D diff --git a/tests/xilinx_ug901/squarediffmult.v b/tests/xilinx_ug901/squarediffmult.v new file mode 100644 index 000000000..0f41b67bc --- /dev/null +++ b/tests/xilinx_ug901/squarediffmult.v @@ -0,0 +1,42 @@ +// Squarer support for DSP block (DSP48E2) with +// pre-adder configured +// as subtractor +// File: squarediffmult.v + +module squarediffmult # (parameter SIZEIN = 16) + ( + input clk, ce, rst, + input signed [SIZEIN-1:0] a, b, + output signed [2*SIZEIN+1:0] square_out + ); + + // Declare registers for intermediate values +reg signed [SIZEIN-1:0] a_reg, b_reg; +reg signed [SIZEIN:0] diff_reg; +reg signed [2*SIZEIN+1:0] m_reg, p_reg; + +always @(posedge clk) +begin + if (rst) + begin + a_reg <= 0; + b_reg <= 0; + diff_reg <= 0; + m_reg <= 0; + p_reg <= 0; + end + else + if (ce) + begin + a_reg <= a; + b_reg <= b; + diff_reg <= a_reg - b_reg; + m_reg <= diff_reg * diff_reg; + p_reg <= m_reg; + end +end + +// Output result +assign square_out = p_reg; + +endmodule // squarediffmult diff --git a/tests/xilinx_ug901/squarediffmult.ys b/tests/xilinx_ug901/squarediffmult.ys new file mode 100644 index 000000000..3468e5bb4 --- /dev/null +++ b/tests/xilinx_ug901/squarediffmult.ys @@ -0,0 +1,30 @@ +read_verilog squarediffmult.v +hierarchy -top squarediffmult +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd squarediffmult +stat +#Vivado synthesizes 16 FDRE, 1 DSP48E1. +select -assert-count 1 t:BUFG +select -assert-count 117 t:FDRE +select -assert-count 223 t:LUT2 +select -assert-count 50 t:LUT3 +select -assert-count 38 t:LUT4 +select -assert-count 56 t:LUT5 +select -assert-count 372 t:LUT6 +select -assert-count 49 t:MUXCY +select -assert-count 99 t:MUXF7 +select -assert-count 26 t:MUXF8 +select -assert-count 51 t:XORCY + +select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D diff --git a/tests/xilinx_ug901/top_mux.v b/tests/xilinx_ug901/top_mux.v new file mode 100644 index 000000000..c23c7491c --- /dev/null +++ b/tests/xilinx_ug901/top_mux.v @@ -0,0 +1,18 @@ +// Multiplexer using case statement +module mux4 (sel, a, b, c, d, outmux); +input [1:0] sel; +input [1:0] a, b, c, d; +output [1:0] outmux; +reg [1:0] outmux; + +always @ * + begin + case(sel) + 2'b00 : outmux = a; + 2'b01 : outmux = b; + 2'b10 : outmux = c; + 2'b11 : outmux = d; + endcase + end +endmodule + diff --git a/tests/xilinx_ug901/top_mux.ys b/tests/xilinx_ug901/top_mux.ys new file mode 100644 index 000000000..0245f3bbc --- /dev/null +++ b/tests/xilinx_ug901/top_mux.ys @@ -0,0 +1,13 @@ +read_verilog top_mux.v +hierarchy -top mux4 +proc +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) + +cd mux4 +#Vivado synthesizes 2 LUT. +stat +select -assert-count 2 t:LUT6 + +select -assert-none t:LUT6 %% t:* %D diff --git a/tests/xilinx_ug901/tristates_1.v b/tests/xilinx_ug901/tristates_1.v new file mode 100644 index 000000000..0038a9989 --- /dev/null +++ b/tests/xilinx_ug901/tristates_1.v @@ -0,0 +1,17 @@ +// Tristate Description Using Combinatorial Always Block +// File: tristates_1.v +// +module tristates_1 (T, I, O); +input T, I; +output O; +reg O; + +always @(T or I) +begin + if (~T) + O = I; + else + O = 1'bZ; +end + +endmodule diff --git a/tests/xilinx_ug901/tristates_1.ys b/tests/xilinx_ug901/tristates_1.ys new file mode 100644 index 000000000..7c13dc227 --- /dev/null +++ b/tests/xilinx_ug901/tristates_1.ys @@ -0,0 +1,13 @@ +read_verilog tristates_1.v +hierarchy -top tristates_1 +proc +tribuf +flatten +synth +equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd tristates_1 # Constrain all select calls below inside the top module +#Vivado synthesizes 3 IBUF, 1 OBUFT. +select -assert-count 1 t:LUT1 +select -assert-count 1 t:$_TBUF_ +select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D diff --git a/tests/xilinx_ug901/tristates_2.v b/tests/xilinx_ug901/tristates_2.v new file mode 100644 index 000000000..0c70a1257 --- /dev/null +++ b/tests/xilinx_ug901/tristates_2.v @@ -0,0 +1,10 @@ +// Tristate Description Using Concurrent Assignment +// File: tristates_2.v +// +module tristates_2 (T, I, O); +input T, I; +output O; + +assign O = (~T) ? I: 1'bZ; + +endmodule diff --git a/tests/xilinx_ug901/tristates_2.ys b/tests/xilinx_ug901/tristates_2.ys new file mode 100644 index 000000000..ba2e1d855 --- /dev/null +++ b/tests/xilinx_ug901/tristates_2.ys @@ -0,0 +1,13 @@ +read_verilog tristates_2.v +hierarchy -top tristates_2 +proc +tribuf +flatten +synth +equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd tristates_2 # Constrain all select calls below inside the top module +#Vivado synthesizes 3 IBUF, 1 OBUFT. +select -assert-count 1 t:LUT1 +select -assert-count 1 t:$_TBUF_ +select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D diff --git a/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.v b/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.v new file mode 100644 index 000000000..f5e843dc9 --- /dev/null +++ b/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.v @@ -0,0 +1,78 @@ +// Xilinx UltraRAM Single Port No Change Mode. This code implements +// a parameterizable UltraRAM block in No Change mode. The behavior of this RAM is +// when data is written, the output of RAM is unchanged. Only when write is +// inactive data corresponding to the address is presented on the output port. +// +module xilinx_ultraram_single_port_no_change #( +//Default parameters were changed because of slow test + //parameter AWIDTH = 12, // Address Width + //parameter DWIDTH = 72, // Data Width + //parameter NBPIPE = 3 // Number of pipeline Registers + parameter AWIDTH = 8, // Address Width + parameter DWIDTH = 8, // Data Width + parameter NBPIPE = 3 // Number of pipeline Registers + ) ( + input clk, // Clock + input rst, // Reset + input we, // Write Enable + input regce, // Output Register Enable + input mem_en, // Memory Enable + input [DWIDTH-1:0] din, // Data Input + input [AWIDTH-1:0] addr, // Address Input + output reg [DWIDTH-1:0] dout // Data Output + ); + +(* ram_style = "ultra" *) +reg [DWIDTH-1:0] mem[(1< Date: Mon, 9 Sep 2019 08:49:29 +0300 Subject: Add comments for unproven cells. --- tests/xilinx_ug901/dynamic_shift_registers_1.ys | 2 +- tests/xilinx_ug901/shift_registers_0.ys | 1 + tests/xilinx_ug901/shift_registers_1.ys | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/xilinx_ug901/dynamic_shift_registers_1.ys b/tests/xilinx_ug901/dynamic_shift_registers_1.ys index 994e12a3e..f70c84f2f 100644 --- a/tests/xilinx_ug901/dynamic_shift_registers_1.ys +++ b/tests/xilinx_ug901/dynamic_shift_registers_1.ys @@ -2,7 +2,7 @@ read_verilog dynamic_shift_registers_1.v hierarchy -top dynamic_shift_register_1 proc flatten - +#ERROR: Found 1 unproven $equiv cells in 'equiv_status -assert'. #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check diff --git a/tests/xilinx_ug901/shift_registers_0.ys b/tests/xilinx_ug901/shift_registers_0.ys index ae7d23a7f..89da1d7cc 100644 --- a/tests/xilinx_ug901/shift_registers_0.ys +++ b/tests/xilinx_ug901/shift_registers_0.ys @@ -2,6 +2,7 @@ read_verilog shift_registers_0.v hierarchy -top shift_registers_0 proc flatten +#ERROR: Found 2 unproven $equiv cells in 'equiv_status -assert'. #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check diff --git a/tests/xilinx_ug901/shift_registers_1.ys b/tests/xilinx_ug901/shift_registers_1.ys index fb935c446..b53b6cb25 100644 --- a/tests/xilinx_ug901/shift_registers_1.ys +++ b/tests/xilinx_ug901/shift_registers_1.ys @@ -2,7 +2,7 @@ read_verilog shift_registers_1.v hierarchy -top shift_registers_1 proc flatten - +#ERROR: Found 2 unproven $equiv cells in 'equiv_status -assert'. #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -- cgit v1.2.3 From 757c476f625bef871f9a4388d4d19bf8c3bc400b Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Tue, 10 Sep 2019 08:08:03 +0300 Subject: Add smoke tests to tests/xilinx --- tests/xilinx/add_sub.v | 13 ++++++ tests/xilinx/add_sub.ys | 10 +++++ tests/xilinx/adffs.v | 91 ++++++++++++++++++++++++++++++++++++++++++ tests/xilinx/adffs.ys | 14 +++++++ tests/xilinx/alu.v | 19 +++++++++ tests/xilinx/alu.ys | 21 ++++++++++ tests/xilinx/counter.v | 17 ++++++++ tests/xilinx/counter.ys | 14 +++++++ tests/xilinx/dffs.v | 37 ++++++++++++++++++ tests/xilinx/dffs.ys | 10 +++++ tests/xilinx/div_mod.v | 13 ++++++ tests/xilinx/div_mod.ys | 17 ++++++++ tests/xilinx/fsm.v | 73 ++++++++++++++++++++++++++++++++++ tests/xilinx/fsm.ys | 14 +++++++ tests/xilinx/latches.v | 6 +-- tests/xilinx/latches.ys | 17 +++++--- tests/xilinx/logic.v | 18 +++++++++ tests/xilinx/logic.ys | 10 +++++ tests/xilinx/memory.v | 21 ++++++++++ tests/xilinx/memory.ys | 17 ++++++++ tests/xilinx/mul.v | 11 ++++++ tests/xilinx/mul.ys | 15 +++++++ tests/xilinx/mux.v | 100 +++++++++++++++++++++++++++++++++++++++++++++++ tests/xilinx/mux.ys | 10 +++++ tests/xilinx/run-test.sh | 2 +- tests/xilinx/shifter.v | 22 +++++++++++ tests/xilinx/shifter.ys | 11 ++++++ tests/xilinx/tribuf.v | 29 ++++++++++++++ tests/xilinx/tribuf.ys | 11 ++++++ 29 files changed, 654 insertions(+), 9 deletions(-) create mode 100644 tests/xilinx/add_sub.v create mode 100644 tests/xilinx/add_sub.ys create mode 100644 tests/xilinx/adffs.v create mode 100644 tests/xilinx/adffs.ys create mode 100644 tests/xilinx/alu.v create mode 100644 tests/xilinx/alu.ys create mode 100644 tests/xilinx/counter.v create mode 100644 tests/xilinx/counter.ys create mode 100644 tests/xilinx/dffs.v create mode 100644 tests/xilinx/dffs.ys create mode 100644 tests/xilinx/div_mod.v create mode 100644 tests/xilinx/div_mod.ys create mode 100644 tests/xilinx/fsm.v create mode 100644 tests/xilinx/fsm.ys create mode 100644 tests/xilinx/logic.v create mode 100644 tests/xilinx/logic.ys create mode 100644 tests/xilinx/memory.v create mode 100644 tests/xilinx/memory.ys create mode 100644 tests/xilinx/mul.v create mode 100644 tests/xilinx/mul.ys create mode 100644 tests/xilinx/mux.v create mode 100644 tests/xilinx/mux.ys create mode 100644 tests/xilinx/shifter.v create mode 100644 tests/xilinx/shifter.ys create mode 100644 tests/xilinx/tribuf.v create mode 100644 tests/xilinx/tribuf.ys (limited to 'tests') diff --git a/tests/xilinx/add_sub.v b/tests/xilinx/add_sub.v new file mode 100644 index 000000000..177c32e30 --- /dev/null +++ b/tests/xilinx/add_sub.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x + y; +assign B = x - y; + +endmodule diff --git a/tests/xilinx/add_sub.ys b/tests/xilinx/add_sub.ys new file mode 100644 index 000000000..821341f20 --- /dev/null +++ b/tests/xilinx/add_sub.ys @@ -0,0 +1,10 @@ +read_verilog add_sub.v +hierarchy -top top +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 14 t:LUT2 +select -assert-count 6 t:MUXCY +select -assert-count 8 t:XORCY +select -assert-none t:LUT2 t:MUXCY t:XORCY %% t:* %D + diff --git a/tests/xilinx/adffs.v b/tests/xilinx/adffs.v new file mode 100644 index 000000000..93c8bf52c --- /dev/null +++ b/tests/xilinx/adffs.v @@ -0,0 +1,91 @@ +module adff + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge clr ) + if ( clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module adffn + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, negedge clr ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module dffsr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge pre, posedge clr ) + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module ndffnsnr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( negedge clk, negedge pre, negedge clr ) + if ( !clr ) + q <= 1'b0; + else if ( !pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2,b3 +); + +dffsr u_dffsr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b ) + ); + +ndffnsnr u_ndffnsnr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b1 ) + ); + +adff u_adff ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b2 ) + ); + +adffn u_adffn ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b3 ) + ); + +endmodule diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys new file mode 100644 index 000000000..96d8e176f --- /dev/null +++ b/tests/xilinx/adffs.ys @@ -0,0 +1,14 @@ +read_verilog adffs.v +proc +async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:BUFG +select -assert-count 3 t:FDRE +select -assert-count 1 t:FDRE_1 +select -assert-count 4 t:LUT2 +select -assert-count 4 t:LUT3 +select -assert-none t:BUFG t:FDRE t:FDRE_1 t:LUT2 t:LUT3 %% t:* %D diff --git a/tests/xilinx/alu.v b/tests/xilinx/alu.v new file mode 100644 index 000000000..f82cc2e21 --- /dev/null +++ b/tests/xilinx/alu.v @@ -0,0 +1,19 @@ +module top ( + input clock, + input [31:0] dinA, dinB, + input [2:0] opcode, + output reg [31:0] dout +); + always @(posedge clock) begin + case (opcode) + 0: dout <= dinA + dinB; + 1: dout <= dinA - dinB; + 2: dout <= dinA >> dinB; + 3: dout <= $signed(dinA) >>> dinB; + 4: dout <= dinA << dinB; + 5: dout <= dinA & dinB; + 6: dout <= dinA | dinB; + 7: dout <= dinA ^ dinB; + endcase + end +endmodule diff --git a/tests/xilinx/alu.ys b/tests/xilinx/alu.ys new file mode 100644 index 000000000..f85f03928 --- /dev/null +++ b/tests/xilinx/alu.ys @@ -0,0 +1,21 @@ +read_verilog alu.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + + +select -assert-count 1 t:BUFG +select -assert-count 32 t:LUT1 +select -assert-count 142 t:LUT2 +select -assert-count 55 t:LUT3 +select -assert-count 70 t:LUT4 +select -assert-count 46 t:LUT5 +select -assert-count 625 t:LUT6 +select -assert-count 62 t:MUXCY +select -assert-count 265 t:MUXF7 +select -assert-count 79 t:MUXF8 +select -assert-count 64 t:XORCY +select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D diff --git a/tests/xilinx/counter.v b/tests/xilinx/counter.v new file mode 100644 index 000000000..52852f8ac --- /dev/null +++ b/tests/xilinx/counter.v @@ -0,0 +1,17 @@ +module top ( +out, +clk, +reset +); + output [7:0] out; + input clk, reset; + reg [7:0] out; + + always @(posedge clk, posedge reset) + if (reset) begin + out <= 8'b0 ; + end else + out <= out + 1; + + +endmodule diff --git a/tests/xilinx/counter.ys b/tests/xilinx/counter.ys new file mode 100644 index 000000000..b602b74d7 --- /dev/null +++ b/tests/xilinx/counter.ys @@ -0,0 +1,14 @@ +read_verilog counter.v +hierarchy -top top +proc +flatten +equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:BUFG +select -assert-count 8 t:FDCE +select -assert-count 1 t:LUT1 +select -assert-count 7 t:MUXCY +select -assert-count 8 t:XORCY +select -assert-none t:BUFG t:FDCE t:LUT1 t:MUXCY t:XORCY %% t:* %D diff --git a/tests/xilinx/dffs.v b/tests/xilinx/dffs.v new file mode 100644 index 000000000..d97840c43 --- /dev/null +++ b/tests/xilinx/dffs.v @@ -0,0 +1,37 @@ +module dff + ( input d, clk, output reg q ); + always @( posedge clk ) + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule + +module top ( +input clk, +input en, +input a, +output b,b1, +); + +dff u_dff ( + .clk (clk ), + .d (a ), + .q (b ) + ); + +dffe u_ndffe ( + .clk (clk ), + .en (en), + .d (a ), + .q (b1 ) + ); + +endmodule diff --git a/tests/xilinx/dffs.ys b/tests/xilinx/dffs.ys new file mode 100644 index 000000000..6a98994c0 --- /dev/null +++ b/tests/xilinx/dffs.ys @@ -0,0 +1,10 @@ +read_verilog dffs.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 2 t:FDRE +select -assert-none t:BUFG t:FDRE %% t:* %D diff --git a/tests/xilinx/div_mod.v b/tests/xilinx/div_mod.v new file mode 100644 index 000000000..64a36707d --- /dev/null +++ b/tests/xilinx/div_mod.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x % y; +assign B = x / y; + +endmodule diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys new file mode 100644 index 000000000..cc00b1a27 --- /dev/null +++ b/tests/xilinx/div_mod.ys @@ -0,0 +1,17 @@ +read_verilog div_mod.v +hierarchy -top top +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 12 t:LUT1 +select -assert-count 21 t:LUT2 +select -assert-count 13 t:LUT4 +select -assert-count 6 t:LUT5 +select -assert-count 80 t:LUT6 +select -assert-count 65 t:MUXCY +select -assert-count 36 t:MUXF7 +select -assert-count 9 t:MUXF8 +select -assert-count 28 t:XORCY +select -assert-none t:LUT1 t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D diff --git a/tests/xilinx/fsm.v b/tests/xilinx/fsm.v new file mode 100644 index 000000000..0605bd102 --- /dev/null +++ b/tests/xilinx/fsm.v @@ -0,0 +1,73 @@ + module fsm ( + clock, + reset, + req_0, + req_1, + gnt_0, + gnt_1 + ); + input clock,reset,req_0,req_1; + output gnt_0,gnt_1; + wire clock,reset,req_0,req_1; + reg gnt_0,gnt_1; + + parameter SIZE = 3 ; + parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; + + reg [SIZE-1:0] state; + reg [SIZE-1:0] next_state; + + always @ (posedge clock) + begin : FSM + if (reset == 1'b1) begin + state <= #1 IDLE; + gnt_0 <= 0; + gnt_1 <= 0; + end else + case(state) + IDLE : if (req_0 == 1'b1) begin + state <= #1 GNT0; + gnt_0 <= 1; + end else if (req_1 == 1'b1) begin + gnt_1 <= 1; + state <= #1 GNT0; + end else begin + state <= #1 IDLE; + end + GNT0 : if (req_0 == 1'b1) begin + state <= #1 GNT0; + end else begin + gnt_0 <= 0; + state <= #1 IDLE; + end + GNT1 : if (req_1 == 1'b1) begin + state <= #1 GNT2; + gnt_1 <= req_0; + end + GNT2 : if (req_0 == 1'b1) begin + state <= #1 GNT1; + gnt_1 <= req_1; + end + default : state <= #1 IDLE; + endcase + end + + endmodule + + module top ( +input clk, +input rst, +input a, +input b, +output g0, +output g1 +); + +fsm u_fsm ( .clock(clk), + .reset(rst), + .req_0(a), + .req_1(b), + .gnt_0(g0), + .gnt_1(g1)); + +endmodule diff --git a/tests/xilinx/fsm.ys b/tests/xilinx/fsm.ys new file mode 100644 index 000000000..3b73891c2 --- /dev/null +++ b/tests/xilinx/fsm.ys @@ -0,0 +1,14 @@ +read_verilog fsm.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:BUFG +select -assert-count 5 t:FDRE +select -assert-count 1 t:LUT3 +select -assert-count 2 t:LUT4 +select -assert-count 4 t:LUT6 +select -assert-none t:BUFG t:FDRE t:LUT3 t:LUT4 t:LUT6 %% t:* %D diff --git a/tests/xilinx/latches.v b/tests/xilinx/latches.v index 83bad7f35..9dc43e4c2 100644 --- a/tests/xilinx/latches.v +++ b/tests/xilinx/latches.v @@ -1,19 +1,19 @@ module latchp - ( input d, en, output reg q ); + ( input d, clk, en, output reg q ); always @* if ( en ) q <= d; endmodule module latchn - ( input d, en, output reg q ); + ( input d, clk, en, output reg q ); always @* if ( !en ) q <= d; endmodule module latchsr - ( input d, en, clr, pre, output reg q ); + ( input d, clk, en, clr, pre, output reg q ); always @* if ( clr ) q <= 1'b0; diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys index bd1dffd21..9ab562bcf 100644 --- a/tests/xilinx/latches.ys +++ b/tests/xilinx/latches.ys @@ -1,13 +1,20 @@ read_verilog latches.v +design -save read proc +async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock flatten -equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +synth_xilinx +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) + +design -load read -design -load preopt synth_xilinx -cd top +#cd top + select -assert-count 1 t:LUT1 select -assert-count 2 t:LUT3 -select -assert-count 3 t:LDCE -select -assert-none t:LUT1 t:LUT3 t:LDCE %% t:* %D +select -assert-count 3 t:$_DLATCH_P_ +#ERROR: Assertion failed: selection is not empty: t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D +#select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D diff --git a/tests/xilinx/logic.v b/tests/xilinx/logic.v new file mode 100644 index 000000000..e5343cae0 --- /dev/null +++ b/tests/xilinx/logic.v @@ -0,0 +1,18 @@ +module top +( + input [0:7] in, + output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10 + ); + + assign B1 = in[0] & in[1]; + assign B2 = in[0] | in[1]; + assign B3 = in[0] ~& in[1]; + assign B4 = in[0] ~| in[1]; + assign B5 = in[0] ^ in[1]; + assign B6 = in[0] ~^ in[1]; + assign B7 = ~in[0]; + assign B8 = in[0]; + assign B9 = in[0:1] && in [2:3]; + assign B10 = in[0:1] || in [2:3]; + +endmodule diff --git a/tests/xilinx/logic.ys b/tests/xilinx/logic.ys new file mode 100644 index 000000000..e138ae6a3 --- /dev/null +++ b/tests/xilinx/logic.ys @@ -0,0 +1,10 @@ +read_verilog logic.v +hierarchy -top top +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:LUT1 +select -assert-count 6 t:LUT2 +select -assert-count 2 t:LUT4 +select -assert-none t:LUT1 t:LUT2 t:LUT4 %% t:* %D diff --git a/tests/xilinx/memory.v b/tests/xilinx/memory.v new file mode 100644 index 000000000..cb7753f7b --- /dev/null +++ b/tests/xilinx/memory.v @@ -0,0 +1,21 @@ +module top +( + input [7:0] data_a, + input [6:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end +endmodule diff --git a/tests/xilinx/memory.ys b/tests/xilinx/memory.ys new file mode 100644 index 000000000..5402513a2 --- /dev/null +++ b/tests/xilinx/memory.ys @@ -0,0 +1,17 @@ +read_verilog memory.v +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd top +select -assert-count 1 t:BUFG +select -assert-count 8 t:FDRE +select -assert-count 8 t:RAM64X1D +select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D diff --git a/tests/xilinx/mul.v b/tests/xilinx/mul.v new file mode 100644 index 000000000..d5b48b1d7 --- /dev/null +++ b/tests/xilinx/mul.v @@ -0,0 +1,11 @@ +module top +( + input [5:0] x, + input [5:0] y, + + output [11:0] A, + ); + +assign A = x * y; + +endmodule diff --git a/tests/xilinx/mul.ys b/tests/xilinx/mul.ys new file mode 100644 index 000000000..ec30c9c2c --- /dev/null +++ b/tests/xilinx/mul.ys @@ -0,0 +1,15 @@ +read_verilog mul.v +hierarchy -top top +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 12 t:LUT2 +select -assert-count 1 t:LUT3 +select -assert-count 6 t:LUT4 +select -assert-count 1 t:LUT5 +select -assert-count 33 t:LUT6 +select -assert-count 11 t:MUXCY +select -assert-count 1 t:MUXF7 +select -assert-count 12 t:XORCY +select -assert-none t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:XORCY %% t:* %D diff --git a/tests/xilinx/mux.v b/tests/xilinx/mux.v new file mode 100644 index 000000000..0814b733e --- /dev/null +++ b/tests/xilinx/mux.v @@ -0,0 +1,100 @@ +module mux2 (S,A,B,Y); + input S; + input A,B; + output reg Y; + + always @(*) + Y = (S)? B : A; +endmodule + +module mux4 ( S, D, Y ); + +input[1:0] S; +input[3:0] D; +output Y; + +reg Y; +wire[1:0] S; +wire[3:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + endcase +end + +endmodule + +module mux8 ( S, D, Y ); + +input[2:0] S; +input[7:0] D; +output Y; + +reg Y; +wire[2:0] S; +wire[7:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + 4 : Y = D[4]; + 5 : Y = D[5]; + 6 : Y = D[6]; + 7 : Y = D[7]; + endcase +end + +endmodule + +module mux16 (D, S, Y); + input [15:0] D; + input [3:0] S; + output Y; + +assign Y = D[S]; + +endmodule + + +module top ( +input [3:0] S, +input [15:0] D, +output M2,M4,M8,M16 +); + +mux2 u_mux2 ( + .S (S[0]), + .A (D[0]), + .B (D[1]), + .Y (M2) + ); + + +mux4 u_mux4 ( + .S (S[1:0]), + .D (D[3:0]), + .Y (M4) + ); + +mux8 u_mux8 ( + .S (S[2:0]), + .D (D[7:0]), + .Y (M8) + ); + +mux16 u_mux16 ( + .S (S[3:0]), + .D (D[15:0]), + .Y (M16) + ); + +endmodule diff --git a/tests/xilinx/mux.ys b/tests/xilinx/mux.ys new file mode 100644 index 000000000..6ecee58f5 --- /dev/null +++ b/tests/xilinx/mux.ys @@ -0,0 +1,10 @@ +read_verilog mux.v +proc +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 2 t:LUT3 +select -assert-count 5 t:LUT6 +select -assert-none t:LUT3 t:LUT6 %% t:* %D diff --git a/tests/xilinx/run-test.sh b/tests/xilinx/run-test.sh index ea56b70f0..2c72ca3a9 100755 --- a/tests/xilinx/run-test.sh +++ b/tests/xilinx/run-test.sh @@ -6,7 +6,7 @@ for x in *.ys; do echo "all:: run-$x" echo "run-$x:" echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log $x" + echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then diff --git a/tests/xilinx/shifter.v b/tests/xilinx/shifter.v new file mode 100644 index 000000000..c55632552 --- /dev/null +++ b/tests/xilinx/shifter.v @@ -0,0 +1,22 @@ +module top ( +out, +clk, +in +); + output [7:0] out; + input signed clk, in; + reg signed [7:0] out = 0; + + always @(posedge clk) + begin +`ifndef BUG + out <= out >> 1; + out[7] <= in; +`else + + out <= out << 1; + out[7] <= in; +`endif + end + +endmodule diff --git a/tests/xilinx/shifter.ys b/tests/xilinx/shifter.ys new file mode 100644 index 000000000..84e16f41e --- /dev/null +++ b/tests/xilinx/shifter.ys @@ -0,0 +1,11 @@ +read_verilog shifter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:BUFG +select -assert-count 8 t:FDRE +select -assert-none t:BUFG t:FDRE %% t:* %D diff --git a/tests/xilinx/tribuf.v b/tests/xilinx/tribuf.v new file mode 100644 index 000000000..3fa6eb6c6 --- /dev/null +++ b/tests/xilinx/tribuf.v @@ -0,0 +1,29 @@ +module tristate (en, i, o); + input en; + input i; + output reg o; +`ifndef BUG + + always @(en or i) + o <= (en)? i : 1'bZ; +`else + + always @(en or i) + o <= (en)? ~i : 1'bZ; +`endif +endmodule + + +module top ( +input en, +input a, +output b +); + +tristate u_tri ( + .en (en ), + .i (a ), + .o (b ) + ); + +endmodule diff --git a/tests/xilinx/tribuf.ys b/tests/xilinx/tribuf.ys new file mode 100644 index 000000000..fc7ed37ef --- /dev/null +++ b/tests/xilinx/tribuf.ys @@ -0,0 +1,11 @@ +read_verilog tribuf.v +hierarchy -top top +proc +tribuf +flatten +synth +equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D -- cgit v1.2.3 From 6331fa5b022b9e16f9392d9604a545f86dc13385 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Tue, 10 Sep 2019 08:11:56 +0300 Subject: Remove xilinx_ug901 tests (will be moved to yosys-tests) --- tests/xilinx_ug901/asym_ram_sdp_read_wider.v | 74 ------------- tests/xilinx_ug901/asym_ram_sdp_read_wider.ys | 22 ---- tests/xilinx_ug901/asym_ram_sdp_write_wider.v | 75 ------------- tests/xilinx_ug901/asym_ram_sdp_write_wider.ys | 31 ------ tests/xilinx_ug901/asym_ram_tdp_read_first.v | 85 -------------- tests/xilinx_ug901/asym_ram_tdp_read_first.ys | 21 ---- tests/xilinx_ug901/asym_ram_tdp_write_first.v | 92 ---------------- tests/xilinx_ug901/asym_ram_tdp_write_first.ys | 29 ----- tests/xilinx_ug901/black_box_1.v | 19 ---- tests/xilinx_ug901/black_box_1.ys | 15 --- tests/xilinx_ug901/bytewrite_ram_1b.v | 42 ------- tests/xilinx_ug901/bytewrite_ram_1b.ys | 22 ---- tests/xilinx_ug901/bytewrite_tdp_ram_nc.v | 78 ------------- tests/xilinx_ug901/bytewrite_tdp_ram_nc.ys | 22 ---- tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.v | 71 ------------ tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.ys | 21 ---- tests/xilinx_ug901/bytewrite_tdp_ram_rf.v | 61 ----------- tests/xilinx_ug901/bytewrite_tdp_ram_rf.ys | 21 ---- tests/xilinx_ug901/bytewrite_tdp_ram_wf.v | 68 ------------ tests/xilinx_ug901/bytewrite_tdp_ram_wf.ys | 23 ---- tests/xilinx_ug901/cmacc.v | 122 --------------------- tests/xilinx_ug901/cmacc.ys | 25 ----- tests/xilinx_ug901/cmult.v | 71 ------------ tests/xilinx_ug901/cmult.ys | 31 ------ tests/xilinx_ug901/dynamic_shift_registers_1.v | 21 ---- tests/xilinx_ug901/dynamic_shift_registers_1.ys | 15 --- tests/xilinx_ug901/dynpreaddmultadd.v | 47 -------- tests/xilinx_ug901/dynpreaddmultadd.ys | 31 ------ tests/xilinx_ug901/fsm_1.v | 42 ------- tests/xilinx_ug901/fsm_1.ys | 16 --- tests/xilinx_ug901/latches.v | 17 --- tests/xilinx_ug901/latches.ys | 10 -- tests/xilinx_ug901/macc.v | 47 -------- tests/xilinx_ug901/macc.ys | 23 ---- tests/xilinx_ug901/mult_unsigned.v | 33 ------ tests/xilinx_ug901/mult_unsigned.ys | 29 ----- tests/xilinx_ug901/presubmult.v | 43 -------- tests/xilinx_ug901/presubmult.ys | 23 ---- tests/xilinx_ug901/ram_simple_dual_one_clock.v | 25 ----- tests/xilinx_ug901/ram_simple_dual_one_clock.ys | 20 ---- tests/xilinx_ug901/ram_simple_dual_two_clocks.v | 30 ----- tests/xilinx_ug901/ram_simple_dual_two_clocks.ys | 20 ---- tests/xilinx_ug901/rams_dist.v | 24 ---- tests/xilinx_ug901/rams_dist.ys | 21 ---- tests/xilinx_ug901/rams_init_file.data | 64 ----------- tests/xilinx_ug901/rams_init_file.v | 24 ---- tests/xilinx_ug901/rams_init_file.ys | 22 ---- tests/xilinx_ug901/rams_pipeline.v | 42 ------- tests/xilinx_ug901/rams_pipeline.ys | 22 ---- tests/xilinx_ug901/rams_sp_nc.v | 26 ----- tests/xilinx_ug901/rams_sp_nc.ys | 22 ---- tests/xilinx_ug901/rams_sp_rf.v | 26 ----- tests/xilinx_ug901/rams_sp_rf.ys | 22 ---- tests/xilinx_ug901/rams_sp_rf_rst.v | 29 ----- tests/xilinx_ug901/rams_sp_rf_rst.ys | 28 ----- tests/xilinx_ug901/rams_sp_rom.v | 46 -------- tests/xilinx_ug901/rams_sp_rom.ys | 22 ---- tests/xilinx_ug901/rams_sp_rom_1.v | 53 --------- tests/xilinx_ug901/rams_sp_rom_1.ys | 22 ---- tests/xilinx_ug901/rams_sp_wf.v | 26 ----- tests/xilinx_ug901/rams_sp_wf.ys | 26 ----- tests/xilinx_ug901/rams_tdp_rf_rf.v | 33 ------ tests/xilinx_ug901/rams_tdp_rf_rf.ys | 21 ---- tests/xilinx_ug901/registers_1.v | 25 ----- tests/xilinx_ug901/registers_1.ys | 12 -- tests/xilinx_ug901/run-test.sh | 20 ---- tests/xilinx_ug901/sfir_shifter.v | 19 ---- tests/xilinx_ug901/sfir_shifter.ys | 16 --- tests/xilinx_ug901/shift_registers_0.v | 22 ---- tests/xilinx_ug901/shift_registers_0.ys | 14 --- tests/xilinx_ug901/shift_registers_1.v | 24 ---- tests/xilinx_ug901/shift_registers_1.ys | 14 --- tests/xilinx_ug901/squarediffmacc.v | 52 --------- tests/xilinx_ug901/squarediffmacc.ys | 23 ---- tests/xilinx_ug901/squarediffmult.v | 42 ------- tests/xilinx_ug901/squarediffmult.ys | 30 ----- tests/xilinx_ug901/top_mux.v | 18 --- tests/xilinx_ug901/top_mux.ys | 13 --- tests/xilinx_ug901/tristates_1.v | 17 --- tests/xilinx_ug901/tristates_1.ys | 13 --- tests/xilinx_ug901/tristates_2.v | 10 -- tests/xilinx_ug901/tristates_2.ys | 13 --- .../xilinx_ultraram_single_port_no_change.v | 78 ------------- .../xilinx_ultraram_single_port_no_change.ys | 25 ----- .../xilinx_ultraram_single_port_read_first.v | 78 ------------- .../xilinx_ultraram_single_port_read_first.ys | 24 ---- .../xilinx_ultraram_single_port_write_first.v | 82 -------------- .../xilinx_ultraram_single_port_write_first.ys | 24 ---- 88 files changed, 2962 deletions(-) delete mode 100644 tests/xilinx_ug901/asym_ram_sdp_read_wider.v delete mode 100644 tests/xilinx_ug901/asym_ram_sdp_read_wider.ys delete mode 100644 tests/xilinx_ug901/asym_ram_sdp_write_wider.v delete mode 100644 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b/tests/xilinx_ug901/asym_ram_sdp_read_wider.v deleted file mode 100644 index 0716dffdc..000000000 --- a/tests/xilinx_ug901/asym_ram_sdp_read_wider.v +++ /dev/null @@ -1,74 +0,0 @@ -// Asymmetric port RAM -// Read Wider than Write. Read Statement in loop -//asym_ram_sdp_read_wider.v - -module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA, doB); -parameter WIDTHA = 4; -parameter SIZEA = 1024; -parameter ADDRWIDTHA = 10; - -parameter WIDTHB = 16; -parameter SIZEB = 256; -parameter ADDRWIDTHB = 8; -input clkA; -input clkB; -input weA; -input enaA, enaB; -input [ADDRWIDTHA-1:0] addrA; -input [ADDRWIDTHB-1:0] addrB; -input [WIDTHA-1:0] diA; -output [WIDTHB-1:0] doB; -`define max(a,b) {(a) > (b) ? (a) : (b)} -`define min(a,b) {(a) < (b) ? (a) : (b)} - -function integer log2; -input integer value; -reg [31:0] shifted; -integer res; -begin - if (value < 2) - log2 = value; - else - begin - shifted = value-1; - for (res=0; shifted>0; res=res+1) - shifted = shifted>>1; - log2 = res; - end -end -endfunction - -localparam maxSIZE = `max(SIZEA, SIZEB); -localparam maxWIDTH = `max(WIDTHA, WIDTHB); -localparam minWIDTH = `min(WIDTHA, WIDTHB); - -localparam RATIO = maxWIDTH / minWIDTH; -localparam log2RATIO = log2(RATIO); - -reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; -reg [WIDTHB-1:0] readB; - -always @(posedge clkA) -begin - if (enaA) begin - if (weA) - RAM[addrA] <= diA; - end -end - - -always @(posedge clkB) -begin : ramread - integer i; - reg [log2RATIO-1:0] lsbaddr; - if (enaB) begin - for (i = 0; i < RATIO; i = i+1) begin - lsbaddr = i; - readB[(i+1)*minWIDTH-1 -: minWIDTH] <= RAM[{addrB, lsbaddr}]; - end - end -end -assign doB = readB; - -endmodule - diff --git a/tests/xilinx_ug901/asym_ram_sdp_read_wider.ys b/tests/xilinx_ug901/asym_ram_sdp_read_wider.ys deleted file mode 100644 index c63157cdf..000000000 --- a/tests/xilinx_ug901/asym_ram_sdp_read_wider.ys +++ /dev/null @@ -1,22 +0,0 @@ -read_verilog asym_ram_sdp_read_wider.v -hierarchy -top asym_ram_sdp_read_wider -proc -memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -memory -opt -full - -# TODO -#equiv_opt -run prove: -assert null -miter -equiv -flatten -make_assert -make_outputs gold gate miter -#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter - -design -load postopt -cd asym_ram_sdp_read_wider -stat -#Vivado synthesizes 1 RAMB18E1. -select -assert-count 2 t:BUFG -select -assert-count 1 t:LUT2 -select -assert-count 4 t:RAMB18E1 - -select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D diff --git a/tests/xilinx_ug901/asym_ram_sdp_write_wider.v b/tests/xilinx_ug901/asym_ram_sdp_write_wider.v deleted file mode 100644 index 22d12d2ce..000000000 --- a/tests/xilinx_ug901/asym_ram_sdp_write_wider.v +++ /dev/null @@ -1,75 +0,0 @@ -// Asymmetric port RAM -// Write wider than Read. Write Statement in a loop. -// asym_ram_sdp_write_wider.v - -module asym_ram_sdp_write_wider (clkA, clkB, weA, enaA, enaB, addrA, addrB, diA, doB); -parameter WIDTHB = 4; -//Default parameters were changed because of slow test -//parameter SIZEB = 1024; -//parameter ADDRWIDTHB = 10; -parameter SIZEB = 256; -parameter ADDRWIDTHB = 8; - -//parameter WIDTHA = 16; -parameter WIDTHA = 8; -parameter SIZEA = 256; -parameter ADDRWIDTHA = 8; -input clkA; -input clkB; -input weA; -input enaA, enaB; -input [ADDRWIDTHA-1:0] addrA; -input [ADDRWIDTHB-1:0] addrB; -input [WIDTHA-1:0] diA; -output [WIDTHB-1:0] doB; -`define max(a,b) {(a) > (b) ? (a) : (b)} -`define min(a,b) {(a) < (b) ? (a) : (b)} - -function integer log2; -input integer value; -reg [31:0] shifted; -integer res; -begin - if (value < 2) - log2 = value; - else - begin - shifted = value-1; - for (res=0; shifted>0; res=res+1) - shifted = shifted>>1; - log2 = res; - end -end -endfunction - -localparam maxSIZE = `max(SIZEA, SIZEB); -localparam maxWIDTH = `max(WIDTHA, WIDTHB); -localparam minWIDTH = `min(WIDTHA, WIDTHB); - -localparam RATIO = maxWIDTH / minWIDTH; -localparam log2RATIO = log2(RATIO); - -reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; -reg [WIDTHB-1:0] readB; - -always @(posedge clkB) begin - if (enaB) begin - readB <= RAM[addrB]; - end -end -assign doB = readB; - -always @(posedge clkA) -begin : ramwrite - integer i; - reg [log2RATIO-1:0] lsbaddr; - for (i=0; i< RATIO; i= i+ 1) begin : write1 - lsbaddr = i; - if (enaA) begin - if (weA) - RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH]; - end - end -end - -endmodule diff --git a/tests/xilinx_ug901/asym_ram_sdp_write_wider.ys b/tests/xilinx_ug901/asym_ram_sdp_write_wider.ys deleted file mode 100644 index 229d98df6..000000000 --- a/tests/xilinx_ug901/asym_ram_sdp_write_wider.ys +++ /dev/null @@ -1,31 +0,0 @@ -read_verilog asym_ram_sdp_write_wider.v -hierarchy -top asym_ram_sdp_write_wider -proc -memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -memory -opt -full - -# TODO -#equiv_opt -run prove: -assert null -miter -equiv -flatten -make_assert -make_outputs gold gate miter -#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter - -design -load postopt -cd asym_ram_sdp_write_wider -stat -#Vivado synthesizes 1 RAMB18E1. -select -assert-count 2 t:BUFG -select -assert-count 1028 t:FDRE -select -assert-count 170 t:LUT2 -select -assert-count 6 t:LUT3 -select -assert-count 518 t:LUT4 -select -assert-count 10 t:LUT5 -select -assert-count 484 t:LUT6 -select -assert-count 157 t:MUXF7 -select -assert-count 3 t:MUXF8 - -#RRAM128X1D will be synthesized in case when the parameter WIDTHA=4 -#select -assert-count 8 t:RAM128X1D - -select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D diff --git a/tests/xilinx_ug901/asym_ram_tdp_read_first.v b/tests/xilinx_ug901/asym_ram_tdp_read_first.v deleted file mode 100644 index 2b807a382..000000000 --- a/tests/xilinx_ug901/asym_ram_tdp_read_first.v +++ /dev/null @@ -1,85 +0,0 @@ -// Asymetric RAM - TDP -// READ_FIRST MODE. -// asym_ram_tdp_read_first.v - - -module asym_ram_tdp_read_first (clkA, clkB, enaA, weA, enaB, weB, addrA, addrB, diA, doA, diB, doB); -parameter WIDTHB = 4; -parameter SIZEB = 1024; -parameter ADDRWIDTHB = 10; -parameter WIDTHA = 16; -parameter SIZEA = 256; -parameter ADDRWIDTHA = 8; -input clkA; -input clkB; -input weA, weB; -input enaA, enaB; - -input [ADDRWIDTHA-1:0] addrA; -input [ADDRWIDTHB-1:0] addrB; -input [WIDTHA-1:0] diA; -input [WIDTHB-1:0] diB; - -output [WIDTHA-1:0] doA; -output [WIDTHB-1:0] doB; - -`define max(a,b) {(a) > (b) ? (a) : (b)} -`define min(a,b) {(a) < (b) ? (a) : (b)} - -function integer log2; -input integer value; -reg [31:0] shifted; -integer res; -begin - if (value < 2) - log2 = value; - else - begin - shifted = value-1; - for (res=0; shifted>0; res=res+1) - shifted = shifted>>1; - log2 = res; - end -end -endfunction - -localparam maxSIZE = `max(SIZEA, SIZEB); -localparam maxWIDTH = `max(WIDTHA, WIDTHB); -localparam minWIDTH = `min(WIDTHA, WIDTHB); - -localparam RATIO = maxWIDTH / minWIDTH; -localparam log2RATIO = log2(RATIO); - -reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; -reg [WIDTHA-1:0] readA; -reg [WIDTHB-1:0] readB; - -always @(posedge clkB) -begin - if (enaB) begin - readB <= RAM[addrB] ; - if (weB) - RAM[addrB] <= diB; - end -end - - -always @(posedge clkA) -begin : portA - integer i; - reg [log2RATIO-1:0] lsbaddr ; - for (i=0; i< RATIO; i= i+ 1) begin - lsbaddr = i; - if (enaA) begin - readA[(i+1)*minWIDTH -1 -: minWIDTH] <= RAM[{addrA, lsbaddr}]; - - if (weA) - RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH]; - end - end -end - -assign doA = readA; -assign doB = readB; - -endmodule diff --git a/tests/xilinx_ug901/asym_ram_tdp_read_first.ys b/tests/xilinx_ug901/asym_ram_tdp_read_first.ys deleted file mode 100644 index 5f96b800c..000000000 --- a/tests/xilinx_ug901/asym_ram_tdp_read_first.ys +++ /dev/null @@ -1,21 +0,0 @@ -read_verilog asym_ram_tdp_read_first.v -hierarchy -top asym_ram_tdp_read_first -proc -memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -memory -opt -full - -# TODO -#equiv_opt -run prove: -assert null -miter -equiv -flatten -make_assert -make_outputs gold gate miter -#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter - -design -load postopt -cd asym_ram_tdp_read_first -stat -#Vivado synthesizes 1 RAMB18E1. -select -assert-count 1 t:$mem -select -assert-count 2 t:LUT2 - -select -assert-none t:$mem t:LUT2 %% t:* %D diff --git a/tests/xilinx_ug901/asym_ram_tdp_write_first.v b/tests/xilinx_ug901/asym_ram_tdp_write_first.v deleted file mode 100644 index 90187ea26..000000000 --- a/tests/xilinx_ug901/asym_ram_tdp_write_first.v +++ /dev/null @@ -1,92 +0,0 @@ -// Asymmetric port RAM - TDP -// WRITE_FIRST MODE. -// asym_ram_tdp_write_first.v - - -module asym_ram_tdp_write_first (clkA, clkB, enaA, weA, enaB, weB, addrA, addrB, diA, doA, diB, doB); -parameter WIDTHB = 4; -//Default parameters were changed because of slow test -//parameter SIZEB = 1024; -//parameter ADDRWIDTHB = 10; -parameter SIZEB = 32; -parameter ADDRWIDTHB = 8; - -//parameter WIDTHA = 16; -parameter WIDTHA = 4; -//parameter SIZEA = 256; -parameter SIZEA = 32; -parameter ADDRWIDTHA = 8; -input clkA; -input clkB; -input weA, weB; -input enaA, enaB; - -input [ADDRWIDTHA-1:0] addrA; -input [ADDRWIDTHB-1:0] addrB; -input [WIDTHA-1:0] diA; -input [WIDTHB-1:0] diB; - -output [WIDTHA-1:0] doA; -output [WIDTHB-1:0] doB; - -`define max(a,b) {(a) > (b) ? (a) : (b)} -`define min(a,b) {(a) < (b) ? (a) : (b)} - -function integer log2; -input integer value; -reg [31:0] shifted; -integer res; -begin - if (value < 2) - log2 = value; - else - begin - shifted = value-1; - for (res=0; shifted>0; res=res+1) - shifted = shifted>>1; - log2 = res; - end -end -endfunction - -localparam maxSIZE = `max(SIZEA, SIZEB); -localparam maxWIDTH = `max(WIDTHA, WIDTHB); -localparam minWIDTH = `min(WIDTHA, WIDTHB); - -localparam RATIO = maxWIDTH / minWIDTH; -localparam log2RATIO = log2(RATIO); - -reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; -reg [WIDTHA-1:0] readA; -reg [WIDTHB-1:0] readB; - -always @(posedge clkB) -begin - if (enaB) begin - if (weB) - RAM[addrB] = diB; - readB = RAM[addrB] ; - end -end - - -always @(posedge clkA) -begin : portA - integer i; - reg [log2RATIO-1:0] lsbaddr ; - for (i=0; i< RATIO; i= i+ 1) begin - lsbaddr = i; - if (enaA) begin - - if (weA) - RAM[{addrA, lsbaddr}] = diA[(i+1)*minWIDTH-1 -: minWIDTH]; - - readA[(i+1)*minWIDTH -1 -: minWIDTH] = RAM[{addrA, lsbaddr}]; - end - end -end - -assign doA = readA; -assign doB = readB; - -endmodule diff --git a/tests/xilinx_ug901/asym_ram_tdp_write_first.ys b/tests/xilinx_ug901/asym_ram_tdp_write_first.ys deleted file mode 100644 index bbe3cc849..000000000 --- a/tests/xilinx_ug901/asym_ram_tdp_write_first.ys +++ /dev/null @@ -1,29 +0,0 @@ -read_verilog asym_ram_tdp_write_first.v -hierarchy -top asym_ram_tdp_write_first -proc -memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -memory -opt -full - -# TODO -#equiv_opt -run prove: -assert null -miter -equiv -flatten -make_assert -make_outputs gold gate miter -#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter - -design -load postopt -cd asym_ram_tdp_write_first -stat -#Vivado synthesizes 1 RAMB18E1. -select -assert-count 2 t:BUFG -select -assert-count 200 t:FDRE -select -assert-count 10 t:LUT2 -select -assert-count 44 t:LUT3 -select -assert-count 81 t:LUT4 -select -assert-count 104 t:LUT5 -select -assert-count 560 t:LUT6 -select -assert-count 261 t:MUXF7 -select -assert-count 127 t:MUXF8 - - -select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D diff --git a/tests/xilinx_ug901/black_box_1.v b/tests/xilinx_ug901/black_box_1.v deleted file mode 100644 index 40caa1b10..000000000 --- a/tests/xilinx_ug901/black_box_1.v +++ /dev/null @@ -1,19 +0,0 @@ -// Black Box -// black_box_1.v -// -(* black_box *) module black_box1 (in1, in2, dout); -input in1, in2; -output dout; -endmodule - -module black_box_1 (DI_1, DI_2, DOUT); -input DI_1, DI_2; -output DOUT; - -black_box1 U1 ( - .in1(DI_1), - .in2(DI_2), - .dout(DOUT) - ); - -endmodule diff --git a/tests/xilinx_ug901/black_box_1.ys b/tests/xilinx_ug901/black_box_1.ys deleted file mode 100644 index acf0b5761..000000000 --- a/tests/xilinx_ug901/black_box_1.ys +++ /dev/null @@ -1,15 +0,0 @@ -read_verilog black_box_1.v -hierarchy -top black_box_1 -proc -tribuf -flatten -synth -#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd black_box_1 # Constrain all select calls below inside the top module -#Vivado synthesizes 1 black box. -#stat -#select -assert-count 0 t:LUT1 -#select -assert-count 1 t:$_TBUF_ -#select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D diff --git a/tests/xilinx_ug901/bytewrite_ram_1b.v b/tests/xilinx_ug901/bytewrite_ram_1b.v deleted file mode 100644 index 46d86c297..000000000 --- a/tests/xilinx_ug901/bytewrite_ram_1b.v +++ /dev/null @@ -1,42 +0,0 @@ -// Single-Port BRAM with Byte-wide Write Enable -// Read-First mode -// Single-process description -// Compact description of the write with a generate-for -// statement -// Column width and number of columns easily configurable -// -// bytewrite_ram_1b.v -// - -module bytewrite_ram_1b (clk, we, addr, di, do); - -parameter SIZE = 1024; -parameter ADDR_WIDTH = 10; -parameter COL_WIDTH = 8; -parameter NB_COL = 4; - -input clk; -input [NB_COL-1:0] we; -input [ADDR_WIDTH-1:0] addr; -input [NB_COL*COL_WIDTH-1:0] di; -output reg [NB_COL*COL_WIDTH-1:0] do; - -reg [NB_COL*COL_WIDTH-1:0] RAM [SIZE-1:0]; - -always @(posedge clk) -begin - do <= RAM[addr]; -end - -generate genvar i; -for (i = 0; i < NB_COL; i = i+1) -begin -always @(posedge clk) -begin - if (we[i]) - RAM[addr][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= di[(i+1)*COL_WIDTH-1:i*COL_WIDTH]; - end -end -endgenerate - -endmodule diff --git a/tests/xilinx_ug901/bytewrite_ram_1b.ys b/tests/xilinx_ug901/bytewrite_ram_1b.ys deleted file mode 100644 index 4f0967801..000000000 --- a/tests/xilinx_ug901/bytewrite_ram_1b.ys +++ /dev/null @@ -1,22 +0,0 @@ -read_verilog bytewrite_ram_1b.v -hierarchy -top bytewrite_ram_1b -proc -memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -memory -opt -full - -# TODO -#equiv_opt -run prove: -assert null -miter -equiv -flatten -make_assert -make_outputs gold gate miter -#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter - -design -load postopt -cd bytewrite_ram_1b -stat -#Vivado synthesizes 1 RAMB36E1. -select -assert-count 1 t:BUFG -select -assert-count 32 t:LUT2 -select -assert-count 8 t:RAMB36E1 - -select -assert-none t:BUFG t:LUT2 t:RAMB36E1 %% t:* %D diff --git a/tests/xilinx_ug901/bytewrite_tdp_ram_nc.v b/tests/xilinx_ug901/bytewrite_tdp_ram_nc.v deleted file mode 100644 index 1093b0838..000000000 --- a/tests/xilinx_ug901/bytewrite_tdp_ram_nc.v +++ /dev/null @@ -1,78 +0,0 @@ -// -// True-Dual-Port BRAM with Byte-wide Write Enable -// No-Change mode -// -// bytewrite_tdp_ram_nc.v -// -// ByteWide Write Enable, - NO_CHANGE mode template - Vivado recomended -module bytewrite_tdp_ram_nc - #( - //--------------------------------------------------------------- - parameter NUM_COL = 4, - parameter COL_WIDTH = 8, - parameter ADDR_WIDTH = 10, // Addr Width in bits : 2**ADDR_WIDTH = RAM Depth - parameter DATA_WIDTH = NUM_COL*COL_WIDTH // Data Width in bits - //--------------------------------------------------------------- - ) ( - input clkA, - input enaA, - input [NUM_COL-1:0] weA, - input [ADDR_WIDTH-1:0] addrA, - input [DATA_WIDTH-1:0] dinA, - output reg [DATA_WIDTH-1:0] doutA, - - input clkB, - input enaB, - input [NUM_COL-1:0] weB, - input [ADDR_WIDTH-1:0] addrB, - input [DATA_WIDTH-1:0] dinB, - output reg [DATA_WIDTH-1:0] doutB - ); - - - // Core Memory - reg [DATA_WIDTH-1:0] ram_block [(2**ADDR_WIDTH)-1:0]; - - // Port-A Operation - generate - genvar i; - for(i=0;i run-test.mk -exec ${MAKE:-make} -f run-test.mk diff --git a/tests/xilinx_ug901/sfir_shifter.v b/tests/xilinx_ug901/sfir_shifter.v deleted file mode 100644 index a8b144bcd..000000000 --- a/tests/xilinx_ug901/sfir_shifter.v +++ /dev/null @@ -1,19 +0,0 @@ -//sfir_shifter.v -(* dont_touch = "yes" *) -module sfir_shifter #(parameter dsize = 16, nbtap = 4) - (input clk,input [dsize-1:0] datain, output [dsize-1:0] dataout); - - (* srl_style = "srl_register" *) reg [dsize-1:0] tmp [0:2*nbtap-1]; - integer i; - - always @(posedge clk) - begin - tmp[0] <= datain; - for (i=0; i<=2*nbtap-2; i=i+1) - tmp[i+1] <= tmp[i]; - end - - assign dataout = tmp[2*nbtap-1]; - -endmodule -// sfir_shifter diff --git a/tests/xilinx_ug901/sfir_shifter.ys b/tests/xilinx_ug901/sfir_shifter.ys deleted file mode 100644 index b9fbeb8cb..000000000 --- a/tests/xilinx_ug901/sfir_shifter.ys +++ /dev/null @@ -1,16 +0,0 @@ -read_verilog sfir_shifter.v -hierarchy -top sfir_shifter -proc -flatten -#ERROR: Found 32 unproven $equiv cells in 'equiv_status -assert'. -#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) - -cd sfir_shifter -#Vivado synthesizes 32 FDRE, 16 SRL16E. -stat -select -assert-count 1 t:BUFG -select -assert-count 16 t:SRL16E - -select -assert-none t:BUFG t:SRL16E %% t:* %D diff --git a/tests/xilinx_ug901/shift_registers_0.v b/tests/xilinx_ug901/shift_registers_0.v deleted file mode 100644 index 77a3ec893..000000000 --- a/tests/xilinx_ug901/shift_registers_0.v +++ /dev/null @@ -1,22 +0,0 @@ -// 8-bit Shift Register -// Rising edge clock -// Active high clock enable -// Concatenation-based template -// File: shift_registers_0.v - -module shift_registers_0 (clk, clken, SI, SO); -parameter WIDTH = 32; -input clk, clken, SI; -output SO; - -reg [WIDTH-1:0] shreg; - -always @(posedge clk) - begin - if (clken) - shreg = {shreg[WIDTH-2:0], SI}; - end - -assign SO = shreg[WIDTH-1]; - -endmodule diff --git a/tests/xilinx_ug901/shift_registers_0.ys b/tests/xilinx_ug901/shift_registers_0.ys deleted file mode 100644 index 89da1d7cc..000000000 --- a/tests/xilinx_ug901/shift_registers_0.ys +++ /dev/null @@ -1,14 +0,0 @@ -read_verilog shift_registers_0.v -hierarchy -top shift_registers_0 -proc -flatten -#ERROR: Found 2 unproven $equiv cells in 'equiv_status -assert'. -#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check - -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd shift_registers_0 # Constrain all select calls below inside the top module -#Vivado synthesizes 1 BUFG, 2 FDRE, 3 SRLC32E. -select -assert-count 1 t:BUFG -select -assert-count 1 t:SRLC32E -select -assert-none t:BUFG t:SRLC32E %% t:* %D diff --git a/tests/xilinx_ug901/shift_registers_1.v b/tests/xilinx_ug901/shift_registers_1.v deleted file mode 100644 index d50820e7b..000000000 --- a/tests/xilinx_ug901/shift_registers_1.v +++ /dev/null @@ -1,24 +0,0 @@ -// 32-bit Shift Register -// Rising edge clock -// Active high clock enable -// For-loop based template -// File: shift_registers_1.v - -module shift_registers_1 (clk, clken, SI, SO); -parameter WIDTH = 32; -input clk, clken, SI; -output SO; -reg [WIDTH-1:0] shreg; - -integer i; -always @(posedge clk) -begin - if (clken) - begin - for (i = 0; i < WIDTH-1; i = i+1) - shreg[i+1] <= shreg[i]; - shreg[0] <= SI; - end -end -assign SO = shreg[WIDTH-1]; -endmodule diff --git a/tests/xilinx_ug901/shift_registers_1.ys b/tests/xilinx_ug901/shift_registers_1.ys deleted file mode 100644 index b53b6cb25..000000000 --- a/tests/xilinx_ug901/shift_registers_1.ys +++ /dev/null @@ -1,14 +0,0 @@ -read_verilog shift_registers_1.v -hierarchy -top shift_registers_1 -proc -flatten -#ERROR: Found 2 unproven $equiv cells in 'equiv_status -assert'. -#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check - -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd shift_registers_1 # Constrain all select calls below inside the top module -#Vivado synthesizes 1 BUFG, 2 FDRE, 3 SRLC32E. -select -assert-count 1 t:BUFG -select -assert-count 1 t:SRLC32E -select -assert-none t:BUFG t:SRLC32E %% t:* %D diff --git a/tests/xilinx_ug901/squarediffmacc.v b/tests/xilinx_ug901/squarediffmacc.v deleted file mode 100644 index 6535b24c4..000000000 --- a/tests/xilinx_ug901/squarediffmacc.v +++ /dev/null @@ -1,52 +0,0 @@ -// This module performs subtraction of two inputs, squaring on the diff -// and then accumulation -// This can be implemented in 1 DSP Block (Ultrascale architecture) -// File : squarediffmacc.v -module squarediffmacc # ( - //Default parameters were changed because of slow test - //parameter SIZEIN = 16, - //SIZEOUT = 40 - parameter SIZEIN = 8, - SIZEOUT = 20 - ) - ( - input clk, - input ce, - input sload, - input signed [SIZEIN-1:0] a, - input signed [SIZEIN-1:0] b, - output signed [SIZEOUT+1:0] accum_out - ); - -// Declare registers for intermediate values -reg signed [SIZEIN-1:0] a_reg, b_reg; -reg signed [SIZEIN:0] diff_reg; -reg sload_reg; -reg signed [2*SIZEIN+1:0] m_reg; -reg signed [SIZEOUT-1:0] adder_out, old_result; - - always @(sload_reg or adder_out) - if (sload_reg) - old_result <= 0; - else - // 'sload' is now and opens the accumulation loop. - // The accumulator takes the next multiplier output - // in the same cycle. - old_result <= adder_out; - - always @(posedge clk) - if (ce) - begin - a_reg <= a; - b_reg <= b; - diff_reg <= a_reg - b_reg; - m_reg <= diff_reg * diff_reg; - sload_reg <= sload; - // Store accumulation result into a register - adder_out <= old_result + m_reg; - end - - // Output accumulation result - assign accum_out = adder_out; - -endmodule // squarediffmacc diff --git a/tests/xilinx_ug901/squarediffmacc.ys b/tests/xilinx_ug901/squarediffmacc.ys deleted file mode 100644 index 92474bea3..000000000 --- a/tests/xilinx_ug901/squarediffmacc.ys +++ /dev/null @@ -1,23 +0,0 @@ -read_verilog squarediffmacc.v -hierarchy -top squarediffmacc -proc -flatten -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) - -cd squarediffmacc -#Vivado synthesizes 1 DSP48E1, 33 FDRE, 16 LUT. -stat -select -assert-count 1 t:BUFG -select -assert-count 64 t:FDRE -select -assert-count 78 t:LUT2 -select -assert-count 7 t:LUT3 -select -assert-count 11 t:LUT4 -select -assert-count 8 t:LUT5 -select -assert-count 125 t:LUT6 -select -assert-count 44 t:MUXCY -select -assert-count 50 t:MUXF7 -select -assert-count 17 t:MUXF8 -select -assert-count 47 t:XORCY - -select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D diff --git a/tests/xilinx_ug901/squarediffmult.v b/tests/xilinx_ug901/squarediffmult.v deleted file mode 100644 index 0f41b67bc..000000000 --- a/tests/xilinx_ug901/squarediffmult.v +++ /dev/null @@ -1,42 +0,0 @@ -// Squarer support for DSP block (DSP48E2) with -// pre-adder configured -// as subtractor -// File: squarediffmult.v - -module squarediffmult # (parameter SIZEIN = 16) - ( - input clk, ce, rst, - input signed [SIZEIN-1:0] a, b, - output signed [2*SIZEIN+1:0] square_out - ); - - // Declare registers for intermediate values -reg signed [SIZEIN-1:0] a_reg, b_reg; -reg signed [SIZEIN:0] diff_reg; -reg signed [2*SIZEIN+1:0] m_reg, p_reg; - -always @(posedge clk) -begin - if (rst) - begin - a_reg <= 0; - b_reg <= 0; - diff_reg <= 0; - m_reg <= 0; - p_reg <= 0; - end - else - if (ce) - begin - a_reg <= a; - b_reg <= b; - diff_reg <= a_reg - b_reg; - m_reg <= diff_reg * diff_reg; - p_reg <= m_reg; - end -end - -// Output result -assign square_out = p_reg; - -endmodule // squarediffmult diff --git a/tests/xilinx_ug901/squarediffmult.ys b/tests/xilinx_ug901/squarediffmult.ys deleted file mode 100644 index 3468e5bb4..000000000 --- a/tests/xilinx_ug901/squarediffmult.ys +++ /dev/null @@ -1,30 +0,0 @@ -read_verilog squarediffmult.v -hierarchy -top squarediffmult -proc -memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -memory -opt -full - -# TODO -#equiv_opt -run prove: -assert null -miter -equiv -flatten -make_assert -make_outputs gold gate miter -#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter - -design -load postopt -cd squarediffmult -stat -#Vivado synthesizes 16 FDRE, 1 DSP48E1. -select -assert-count 1 t:BUFG -select -assert-count 117 t:FDRE -select -assert-count 223 t:LUT2 -select -assert-count 50 t:LUT3 -select -assert-count 38 t:LUT4 -select -assert-count 56 t:LUT5 -select -assert-count 372 t:LUT6 -select -assert-count 49 t:MUXCY -select -assert-count 99 t:MUXF7 -select -assert-count 26 t:MUXF8 -select -assert-count 51 t:XORCY - -select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D diff --git a/tests/xilinx_ug901/top_mux.v b/tests/xilinx_ug901/top_mux.v deleted file mode 100644 index c23c7491c..000000000 --- a/tests/xilinx_ug901/top_mux.v +++ /dev/null @@ -1,18 +0,0 @@ -// Multiplexer using case statement -module mux4 (sel, a, b, c, d, outmux); -input [1:0] sel; -input [1:0] a, b, c, d; -output [1:0] outmux; -reg [1:0] outmux; - -always @ * - begin - case(sel) - 2'b00 : outmux = a; - 2'b01 : outmux = b; - 2'b10 : outmux = c; - 2'b11 : outmux = d; - endcase - end -endmodule - diff --git a/tests/xilinx_ug901/top_mux.ys b/tests/xilinx_ug901/top_mux.ys deleted file mode 100644 index 0245f3bbc..000000000 --- a/tests/xilinx_ug901/top_mux.ys +++ /dev/null @@ -1,13 +0,0 @@ -read_verilog top_mux.v -hierarchy -top mux4 -proc -flatten -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) - -cd mux4 -#Vivado synthesizes 2 LUT. -stat -select -assert-count 2 t:LUT6 - -select -assert-none t:LUT6 %% t:* %D diff --git a/tests/xilinx_ug901/tristates_1.v b/tests/xilinx_ug901/tristates_1.v deleted file mode 100644 index 0038a9989..000000000 --- a/tests/xilinx_ug901/tristates_1.v +++ /dev/null @@ -1,17 +0,0 @@ -// Tristate Description Using Combinatorial Always Block -// File: tristates_1.v -// -module tristates_1 (T, I, O); -input T, I; -output O; -reg O; - -always @(T or I) -begin - if (~T) - O = I; - else - O = 1'bZ; -end - -endmodule diff --git a/tests/xilinx_ug901/tristates_1.ys b/tests/xilinx_ug901/tristates_1.ys deleted file mode 100644 index 7c13dc227..000000000 --- a/tests/xilinx_ug901/tristates_1.ys +++ /dev/null @@ -1,13 +0,0 @@ -read_verilog tristates_1.v -hierarchy -top tristates_1 -proc -tribuf -flatten -synth -equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd tristates_1 # Constrain all select calls below inside the top module -#Vivado synthesizes 3 IBUF, 1 OBUFT. -select -assert-count 1 t:LUT1 -select -assert-count 1 t:$_TBUF_ -select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D diff --git a/tests/xilinx_ug901/tristates_2.v b/tests/xilinx_ug901/tristates_2.v deleted file mode 100644 index 0c70a1257..000000000 --- a/tests/xilinx_ug901/tristates_2.v +++ /dev/null @@ -1,10 +0,0 @@ -// Tristate Description Using Concurrent Assignment -// File: tristates_2.v -// -module tristates_2 (T, I, O); -input T, I; -output O; - -assign O = (~T) ? I: 1'bZ; - -endmodule diff --git a/tests/xilinx_ug901/tristates_2.ys b/tests/xilinx_ug901/tristates_2.ys deleted file mode 100644 index ba2e1d855..000000000 --- a/tests/xilinx_ug901/tristates_2.ys +++ /dev/null @@ -1,13 +0,0 @@ -read_verilog tristates_2.v -hierarchy -top tristates_2 -proc -tribuf -flatten -synth -equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd tristates_2 # Constrain all select calls below inside the top module -#Vivado synthesizes 3 IBUF, 1 OBUFT. -select -assert-count 1 t:LUT1 -select -assert-count 1 t:$_TBUF_ -select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D diff --git a/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.v b/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.v deleted file mode 100644 index f5e843dc9..000000000 --- a/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.v +++ /dev/null @@ -1,78 +0,0 @@ -// Xilinx UltraRAM Single Port No Change Mode. This code implements -// a parameterizable UltraRAM block in No Change mode. The behavior of this RAM is -// when data is written, the output of RAM is unchanged. Only when write is -// inactive data corresponding to the address is presented on the output port. -// -module xilinx_ultraram_single_port_no_change #( -//Default parameters were changed because of slow test - //parameter AWIDTH = 12, // Address Width - //parameter DWIDTH = 72, // Data Width - //parameter NBPIPE = 3 // Number of pipeline Registers - parameter AWIDTH = 8, // Address Width - parameter DWIDTH = 8, // Data Width - parameter NBPIPE = 3 // Number of pipeline Registers - ) ( - input clk, // Clock - input rst, // Reset - input we, // Write Enable - input regce, // Output Register Enable - input mem_en, // Memory Enable - input [DWIDTH-1:0] din, // Data Input - input [AWIDTH-1:0] addr, // Address Input - output reg [DWIDTH-1:0] dout // Data Output - ); - -(* ram_style = "ultra" *) -reg [DWIDTH-1:0] mem[(1< Date: Tue, 10 Sep 2019 08:36:59 +0300 Subject: Fix latches.ys test --- tests/xilinx/latches.ys | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'tests') diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys index 9ab562bcf..042ee2d4f 100644 --- a/tests/xilinx/latches.ys +++ b/tests/xilinx/latches.ys @@ -11,10 +11,9 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p design -load read synth_xilinx -#cd top - +flatten +cd top select -assert-count 1 t:LUT1 select -assert-count 2 t:LUT3 select -assert-count 3 t:$_DLATCH_P_ -#ERROR: Assertion failed: selection is not empty: t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D -#select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D +select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D -- cgit v1.2.3 From 7bc8f0c2e234641b8af7f8dd991ea65bd9a6ef1a Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Wed, 11 Sep 2019 17:01:19 +0300 Subject: Add comment with expected behavior for latches,tribuf tests;Update adffs test --- tests/xilinx/adffs.v | 18 +++++++----------- tests/xilinx/adffs.ys | 5 ++--- tests/xilinx/latches.ys | 1 + tests/xilinx/tribuf.ys | 1 + 4 files changed, 11 insertions(+), 14 deletions(-) (limited to 'tests') diff --git a/tests/xilinx/adffs.v b/tests/xilinx/adffs.v index 93c8bf52c..05e68caf7 100644 --- a/tests/xilinx/adffs.v +++ b/tests/xilinx/adffs.v @@ -22,30 +22,26 @@ module adffn q <= d; endmodule -module dffsr +module dffs ( input d, clk, pre, clr, output reg q ); initial begin q = 0; end - always @( posedge clk, posedge pre, posedge clr ) - if ( clr ) - q <= 1'b0; - else if ( pre ) + always @( posedge clk ) + if ( pre ) q <= 1'b1; else q <= d; endmodule -module ndffnsnr +module ndffnr ( input d, clk, pre, clr, output reg q ); initial begin q = 0; end - always @( negedge clk, negedge pre, negedge clr ) + always @( negedge clk ) if ( !clr ) q <= 1'b0; - else if ( !pre ) - q <= 1'b1; else q <= d; endmodule @@ -58,7 +54,7 @@ input a, output b,b1,b2,b3 ); -dffsr u_dffsr ( +dffs u_dffs ( .clk (clk ), .clr (clr), .pre (pre), @@ -66,7 +62,7 @@ dffsr u_dffsr ( .q (b ) ); -ndffnsnr u_ndffnsnr ( +ndffnr u_ndffnr ( .clk (clk ), .clr (clr), .pre (pre), diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys index 96d8e176f..38c82a36f 100644 --- a/tests/xilinx/adffs.ys +++ b/tests/xilinx/adffs.ys @@ -9,6 +9,5 @@ cd top # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 3 t:FDRE select -assert-count 1 t:FDRE_1 -select -assert-count 4 t:LUT2 -select -assert-count 4 t:LUT3 -select -assert-none t:BUFG t:FDRE t:FDRE_1 t:LUT2 t:LUT3 %% t:* %D +select -assert-count 5 t:LUT2 +select -assert-none t:BUFG t:FDRE t:FDRE_1 t:LUT2 %% t:* %D diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys index 042ee2d4f..1f643cb4e 100644 --- a/tests/xilinx/latches.ys +++ b/tests/xilinx/latches.ys @@ -15,5 +15,6 @@ flatten cd top select -assert-count 1 t:LUT1 select -assert-count 2 t:LUT3 +#Xilinx Vivado synthesizes LDCE cell for this case. Need support it. select -assert-count 3 t:$_DLATCH_P_ select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D diff --git a/tests/xilinx/tribuf.ys b/tests/xilinx/tribuf.ys index fc7ed37ef..76b00647d 100644 --- a/tests/xilinx/tribuf.ys +++ b/tests/xilinx/tribuf.ys @@ -7,5 +7,6 @@ synth equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module +#Xilinx Vivado synthesizes OBUFT cell for this case. Need support it. select -assert-count 1 t:$_TBUF_ select -assert-none t:$_TBUF_ %% t:* %D -- cgit v1.2.3 From df7fe40529f7e0a26626ac1b0ed12acf66bb40d3 Mon Sep 17 00:00:00 2001 From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com> Date: Wed, 11 Sep 2019 20:34:22 +0300 Subject: Fix div_mod test --- tests/xilinx/div_mod.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys index cc00b1a27..52e536a7f 100644 --- a/tests/xilinx/div_mod.ys +++ b/tests/xilinx/div_mod.ys @@ -6,7 +6,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd top # Constrain all select calls below inside the top module select -assert-count 12 t:LUT1 -select -assert-count 21 t:LUT2 +select -assert-count 23 t:LUT2 select -assert-count 13 t:LUT4 select -assert-count 6 t:LUT5 select -assert-count 80 t:LUT6 -- cgit v1.2.3 From 205f52ffe53778daf9fc1bcdd9bee4b53a6e2a60 Mon Sep 17 00:00:00 2001 From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com> Date: Wed, 11 Sep 2019 21:28:40 +0300 Subject: Fix div_mod test --- tests/xilinx/div_mod.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys index 52e536a7f..e1c4d6912 100644 --- a/tests/xilinx/div_mod.ys +++ b/tests/xilinx/div_mod.ys @@ -7,7 +7,7 @@ cd top # Constrain all select calls below inside the top module select -assert-count 12 t:LUT1 select -assert-count 23 t:LUT2 -select -assert-count 13 t:LUT4 +select -assert-count 12 t:LUT4 select -assert-count 6 t:LUT5 select -assert-count 80 t:LUT6 select -assert-count 65 t:MUXCY -- cgit v1.2.3 From c340d54657688542c5f3a8dabe3f68563dcc8d1c Mon Sep 17 00:00:00 2001 From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com> Date: Thu, 12 Sep 2019 06:24:18 +0300 Subject: Fix div_mod test --- tests/xilinx/div_mod.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys index e1c4d6912..7db336d00 100644 --- a/tests/xilinx/div_mod.ys +++ b/tests/xilinx/div_mod.ys @@ -8,7 +8,7 @@ cd top # Constrain all select calls below inside the top module select -assert-count 12 t:LUT1 select -assert-count 23 t:LUT2 select -assert-count 12 t:LUT4 -select -assert-count 6 t:LUT5 +select -assert-count 9 t:LUT5 select -assert-count 80 t:LUT6 select -assert-count 65 t:MUXCY select -assert-count 36 t:MUXF7 -- cgit v1.2.3 From df6d0b95da89a4a7bd558dab0c112f5c7a989561 Mon Sep 17 00:00:00 2001 From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com> Date: Thu, 12 Sep 2019 07:13:49 +0300 Subject: Fix div_mod test --- tests/xilinx/div_mod.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys index 7db336d00..c5855f1dd 100644 --- a/tests/xilinx/div_mod.ys +++ b/tests/xilinx/div_mod.ys @@ -9,7 +9,7 @@ select -assert-count 12 t:LUT1 select -assert-count 23 t:LUT2 select -assert-count 12 t:LUT4 select -assert-count 9 t:LUT5 -select -assert-count 80 t:LUT6 +select -assert-count 84 t:LUT6 select -assert-count 65 t:MUXCY select -assert-count 36 t:MUXF7 select -assert-count 9 t:MUXF8 -- cgit v1.2.3 From 68f9239c5758e4f48dc290871cf108f85d5f5387 Mon Sep 17 00:00:00 2001 From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com> Date: Thu, 12 Sep 2019 13:58:49 +0300 Subject: Fix div_mod test --- tests/xilinx/div_mod.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys index c5855f1dd..6a4c1e971 100644 --- a/tests/xilinx/div_mod.ys +++ b/tests/xilinx/div_mod.ys @@ -11,7 +11,7 @@ select -assert-count 12 t:LUT4 select -assert-count 9 t:LUT5 select -assert-count 84 t:LUT6 select -assert-count 65 t:MUXCY -select -assert-count 36 t:MUXF7 +select -assert-count 39 t:MUXF7 select -assert-count 9 t:MUXF8 select -assert-count 28 t:XORCY select -assert-none t:LUT1 t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D -- cgit v1.2.3 From bb70eb977dc29dbfe8cfb9af847046f387bd54b2 Mon Sep 17 00:00:00 2001 From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com> Date: Thu, 12 Sep 2019 14:54:01 +0300 Subject: Fix div_mod test --- tests/xilinx/div_mod.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys index 6a4c1e971..4518db8bf 100644 --- a/tests/xilinx/div_mod.ys +++ b/tests/xilinx/div_mod.ys @@ -12,6 +12,6 @@ select -assert-count 9 t:LUT5 select -assert-count 84 t:LUT6 select -assert-count 65 t:MUXCY select -assert-count 39 t:MUXF7 -select -assert-count 9 t:MUXF8 +select -assert-count 15 t:MUXF8 select -assert-count 28 t:XORCY select -assert-none t:LUT1 t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D -- cgit v1.2.3 From 305672170bcd6346bebbb01c843225fe0392a37d Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Tue, 17 Sep 2019 11:53:49 +0300 Subject: adffs test update (equiv_opt -multiclock) --- tests/xilinx/adffs.ys | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'tests') diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys index 38c82a36f..961e08ae9 100644 --- a/tests/xilinx/adffs.ys +++ b/tests/xilinx/adffs.ys @@ -1,13 +1,14 @@ read_verilog adffs.v proc -async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock flatten -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -multiclock -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG -select -assert-count 3 t:FDRE +select -assert-count 2 t:FDCE +select -assert-count 1 t:FDRE select -assert-count 1 t:FDRE_1 -select -assert-count 5 t:LUT2 -select -assert-none t:BUFG t:FDRE t:FDRE_1 t:LUT2 %% t:* %D +select -assert-count 1 t:LUT1 +select -assert-count 2 t:LUT2 +select -assert-none t:BUFG t:FDCE t:FDRE t:FDRE_1 t:LUT1 t:LUT2 %% t:* %D -- cgit v1.2.3 From eded90b6b42117ba427469a6100c74e708c4f142 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 14:16:45 -0700 Subject: Move $x to end as 7f0eec8 --- tests/xilinx/run-test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/xilinx/run-test.sh b/tests/xilinx/run-test.sh index 2c72ca3a9..46716f9a0 100755 --- a/tests/xilinx/run-test.sh +++ b/tests/xilinx/run-test.sh @@ -6,7 +6,7 @@ for x in *.ys; do echo "all:: run-$x" echo "run-$x:" echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" + echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then -- cgit v1.2.3 From a12801843bb400bba8f2f8ce99a3f524ac05b7e8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 14:17:59 -0700 Subject: Add comment for lack of tristate logic pointing to #1225 --- tests/xilinx/tribuf.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/xilinx/tribuf.ys b/tests/xilinx/tribuf.ys index 76b00647d..696be2620 100644 --- a/tests/xilinx/tribuf.ys +++ b/tests/xilinx/tribuf.ys @@ -7,6 +7,6 @@ synth equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -#Xilinx Vivado synthesizes OBUFT cell for this case. Need support it. +# TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225 select -assert-count 1 t:$_TBUF_ select -assert-none t:$_TBUF_ %% t:* %D -- cgit v1.2.3 From 08bd1816e39d2abfbe36ce0b58c0d4506db303e4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 14:20:47 -0700 Subject: Update area for div_mod --- tests/xilinx/div_mod.ys | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'tests') diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys index 4518db8bf..da7e60a9a 100644 --- a/tests/xilinx/div_mod.ys +++ b/tests/xilinx/div_mod.ys @@ -6,12 +6,12 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd top # Constrain all select calls below inside the top module select -assert-count 12 t:LUT1 -select -assert-count 23 t:LUT2 -select -assert-count 12 t:LUT4 -select -assert-count 9 t:LUT5 -select -assert-count 84 t:LUT6 +select -assert-count 19 t:LUT2 +select -assert-count 13 t:LUT4 +select -assert-count 6 t:LUT5 +select -assert-count 82 t:LUT6 select -assert-count 65 t:MUXCY -select -assert-count 39 t:MUXF7 -select -assert-count 15 t:MUXF8 +select -assert-count 37 t:MUXF7 +select -assert-count 11 t:MUXF8 select -assert-count 28 t:XORCY select -assert-none t:LUT1 t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D -- cgit v1.2.3 From 5b7bc3ab85d31920883995636d26dc5b971ca24d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 14:38:06 -0700 Subject: Update mul test to DSP48E1 --- tests/xilinx/mul.ys | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) (limited to 'tests') diff --git a/tests/xilinx/mul.ys b/tests/xilinx/mul.ys index ec30c9c2c..f5306e848 100644 --- a/tests/xilinx/mul.ys +++ b/tests/xilinx/mul.ys @@ -4,12 +4,5 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 12 t:LUT2 -select -assert-count 1 t:LUT3 -select -assert-count 6 t:LUT4 -select -assert-count 1 t:LUT5 -select -assert-count 33 t:LUT6 -select -assert-count 11 t:MUXCY -select -assert-count 1 t:MUXF7 -select -assert-count 12 t:XORCY -select -assert-none t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:XORCY %% t:* %D +select -assert-count 1 t:DSP48E1 +select -assert-none t:DSP48E1 %% t:* %D -- cgit v1.2.3 From 8422ad3e3a5db583f59906f8a5d81587dd777f6d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 14:56:19 -0700 Subject: Use built-in async2sync call as per #1417 --- tests/xilinx/latches.ys | 4 ---- 1 file changed, 4 deletions(-) (limited to 'tests') diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys index 1f643cb4e..795ac9074 100644 --- a/tests/xilinx/latches.ys +++ b/tests/xilinx/latches.ys @@ -4,11 +4,7 @@ design -save read proc async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock flatten -synth_xilinx equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) - -design -load read synth_xilinx flatten -- cgit v1.2.3 From 3b4408432073ec4d9a2b8995b8e08a5bf6175f39 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 19:57:26 -0700 Subject: Add -assert --- tests/xilinx/counter.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/xilinx/counter.ys b/tests/xilinx/counter.ys index b602b74d7..3bb3a8eb0 100644 --- a/tests/xilinx/counter.ys +++ b/tests/xilinx/counter.ys @@ -2,7 +2,7 @@ read_verilog counter.v hierarchy -top top proc flatten -equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -- cgit v1.2.3 From a7fbc8c3fe1e2ad867ffc3456943644e70ab2575 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 08:19:26 +0200 Subject: Test per flip-flop type --- tests/xilinx/adffs.v | 40 ---------------------------------------- tests/xilinx/adffs.ys | 44 +++++++++++++++++++++++++++++++++++++------- 2 files changed, 37 insertions(+), 47 deletions(-) (limited to 'tests') diff --git a/tests/xilinx/adffs.v b/tests/xilinx/adffs.v index 05e68caf7..223b52d21 100644 --- a/tests/xilinx/adffs.v +++ b/tests/xilinx/adffs.v @@ -45,43 +45,3 @@ module ndffnr else q <= d; endmodule - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2,b3 -); - -dffs u_dffs ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b ) - ); - -ndffnr u_ndffnr ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b1 ) - ); - -adff u_adff ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b2 ) - ); - -adffn u_adffn ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b3 ) - ); - -endmodule diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys index 961e08ae9..7edab67c7 100644 --- a/tests/xilinx/adffs.ys +++ b/tests/xilinx/adffs.ys @@ -1,14 +1,44 @@ read_verilog adffs.v +design -save read + proc -flatten -equiv_opt -multiclock -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +hierarchy -top adff +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd adff # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 1 t:FDCE +select -assert-none t:BUFG t:FDCE %% t:* %D + +design -load read +proc +hierarchy -top adffn +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adffn # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 1 t:FDCE +select -assert-count 1 t:LUT1 +select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D +design -load read +proc +hierarchy -top dffs +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffs # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG -select -assert-count 2 t:FDCE select -assert-count 1 t:FDRE +select -assert-count 1 t:LUT2 +select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D + +design -load read +proc +hierarchy -top ndffnr +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd ndffnr # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG select -assert-count 1 t:FDRE_1 -select -assert-count 1 t:LUT1 -select -assert-count 2 t:LUT2 -select -assert-none t:BUFG t:FDCE t:FDRE t:FDRE_1 t:LUT1 t:LUT2 %% t:* %D +select -assert-count 1 t:LUT2 +select -assert-none t:BUFG t:FDRE_1 t:LUT2 %% t:* %D \ No newline at end of file -- cgit v1.2.3 From d37cd267a56295737e95f5bc5e6f446c27605639 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 08:24:37 +0200 Subject: Removed alu and div_mod test as agreed, ignore generated files --- tests/xilinx/.gitignore | 1 + tests/xilinx/alu.v | 19 ------------------- tests/xilinx/alu.ys | 21 --------------------- tests/xilinx/div_mod.v | 13 ------------- tests/xilinx/div_mod.ys | 17 ----------------- 5 files changed, 1 insertion(+), 70 deletions(-) delete mode 100644 tests/xilinx/alu.v delete mode 100644 tests/xilinx/alu.ys delete mode 100644 tests/xilinx/div_mod.v delete mode 100644 tests/xilinx/div_mod.ys (limited to 'tests') diff --git a/tests/xilinx/.gitignore b/tests/xilinx/.gitignore index 54733fb71..89879f209 100644 --- a/tests/xilinx/.gitignore +++ b/tests/xilinx/.gitignore @@ -2,3 +2,4 @@ /*.out /run-test.mk /*_uut.v +/test_macc \ No newline at end of file diff --git a/tests/xilinx/alu.v b/tests/xilinx/alu.v deleted file mode 100644 index f82cc2e21..000000000 --- a/tests/xilinx/alu.v +++ /dev/null @@ -1,19 +0,0 @@ -module top ( - input clock, - input [31:0] dinA, dinB, - input [2:0] opcode, - output reg [31:0] dout -); - always @(posedge clock) begin - case (opcode) - 0: dout <= dinA + dinB; - 1: dout <= dinA - dinB; - 2: dout <= dinA >> dinB; - 3: dout <= $signed(dinA) >>> dinB; - 4: dout <= dinA << dinB; - 5: dout <= dinA & dinB; - 6: dout <= dinA | dinB; - 7: dout <= dinA ^ dinB; - endcase - end -endmodule diff --git a/tests/xilinx/alu.ys b/tests/xilinx/alu.ys deleted file mode 100644 index f85f03928..000000000 --- a/tests/xilinx/alu.ys +++ /dev/null @@ -1,21 +0,0 @@ -read_verilog alu.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - - -select -assert-count 1 t:BUFG -select -assert-count 32 t:LUT1 -select -assert-count 142 t:LUT2 -select -assert-count 55 t:LUT3 -select -assert-count 70 t:LUT4 -select -assert-count 46 t:LUT5 -select -assert-count 625 t:LUT6 -select -assert-count 62 t:MUXCY -select -assert-count 265 t:MUXF7 -select -assert-count 79 t:MUXF8 -select -assert-count 64 t:XORCY -select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D diff --git a/tests/xilinx/div_mod.v b/tests/xilinx/div_mod.v deleted file mode 100644 index 64a36707d..000000000 --- a/tests/xilinx/div_mod.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x % y; -assign B = x / y; - -endmodule diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys deleted file mode 100644 index da7e60a9a..000000000 --- a/tests/xilinx/div_mod.ys +++ /dev/null @@ -1,17 +0,0 @@ -read_verilog div_mod.v -hierarchy -top top -flatten -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 12 t:LUT1 -select -assert-count 19 t:LUT2 -select -assert-count 13 t:LUT4 -select -assert-count 6 t:LUT5 -select -assert-count 82 t:LUT6 -select -assert-count 65 t:MUXCY -select -assert-count 37 t:MUXF7 -select -assert-count 11 t:MUXF8 -select -assert-count 28 t:XORCY -select -assert-none t:LUT1 t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D -- cgit v1.2.3 From 53bc499a907cc3bfbeb91866d8839286ae0dfdf1 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 08:27:49 +0200 Subject: Clean verilog code from not used define block --- tests/xilinx/shifter.v | 6 ------ tests/xilinx/tribuf.v | 6 ------ 2 files changed, 12 deletions(-) (limited to 'tests') diff --git a/tests/xilinx/shifter.v b/tests/xilinx/shifter.v index c55632552..04ae49d83 100644 --- a/tests/xilinx/shifter.v +++ b/tests/xilinx/shifter.v @@ -9,14 +9,8 @@ in always @(posedge clk) begin -`ifndef BUG out <= out >> 1; out[7] <= in; -`else - - out <= out << 1; - out[7] <= in; -`endif end endmodule diff --git a/tests/xilinx/tribuf.v b/tests/xilinx/tribuf.v index 3fa6eb6c6..75149d8ba 100644 --- a/tests/xilinx/tribuf.v +++ b/tests/xilinx/tribuf.v @@ -2,15 +2,9 @@ module tristate (en, i, o); input en; input i; output reg o; -`ifndef BUG always @(en or i) o <= (en)? i : 1'bZ; -`else - - always @(en or i) - o <= (en)? ~i : 1'bZ; -`endif endmodule -- cgit v1.2.3 From fba6229718a45188514e016eec8678f1facb82a4 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 09:19:17 +0200 Subject: Fix formatting --- tests/xilinx/adffs.ys | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys index 7edab67c7..2d23749ac 100644 --- a/tests/xilinx/adffs.ys +++ b/tests/xilinx/adffs.ys @@ -8,8 +8,10 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd adff # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDCE + select -assert-none t:BUFG t:FDCE %% t:* %D + design -load read proc hierarchy -top adffn @@ -19,8 +21,10 @@ cd adffn # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDCE select -assert-count 1 t:LUT1 + select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D + design -load read proc hierarchy -top dffs @@ -30,8 +34,10 @@ cd dffs # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDRE select -assert-count 1 t:LUT2 + select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D + design -load read proc hierarchy -top ndffnr @@ -41,4 +47,5 @@ cd ndffnr # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDRE_1 select -assert-count 1 t:LUT2 -select -assert-none t:BUFG t:FDRE_1 t:LUT2 %% t:* %D \ No newline at end of file + +select -assert-none t:BUFG t:FDRE_1 t:LUT2 %% t:* %D -- cgit v1.2.3 From 487b38b124cbb388bd680cb54cb43c58829ca1d3 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 09:24:22 +0200 Subject: Split latches into separete tests --- tests/xilinx/latches.v | 34 ---------------------------------- tests/xilinx/latches.ys | 35 +++++++++++++++++++++++++++-------- 2 files changed, 27 insertions(+), 42 deletions(-) (limited to 'tests') diff --git a/tests/xilinx/latches.v b/tests/xilinx/latches.v index 9dc43e4c2..adb5d5319 100644 --- a/tests/xilinx/latches.v +++ b/tests/xilinx/latches.v @@ -22,37 +22,3 @@ module latchsr else if ( en ) q <= d; endmodule - - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2 -); - - -latchp u_latchp ( - .en (clk ), - .d (a ), - .q (b ) - ); - - -latchn u_latchn ( - .en (clk ), - .d (a ), - .q (b1 ) - ); - - -latchsr u_latchsr ( - .en (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b2 ) - ); - -endmodule diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys index 795ac9074..68ca42b10 100644 --- a/tests/xilinx/latches.ys +++ b/tests/xilinx/latches.ys @@ -2,15 +2,34 @@ read_verilog latches.v design -save read proc -async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock -flatten +hierarchy -top latchp equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd latchp # Constrain all select calls below inside the top module +select -assert-count 1 t:LDCE -synth_xilinx -flatten -cd top +select -assert-none t:LDCE %% t:* %D + + +design -load read +proc +hierarchy -top latchn +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd latchn # Constrain all select calls below inside the top module +select -assert-count 1 t:LDCE select -assert-count 1 t:LUT1 + +select -assert-none t:LDCE t:LUT1 %% t:* %D + + +design -load read +proc +hierarchy -top latchsr +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd latchsr # Constrain all select calls below inside the top module +select -assert-count 1 t:LDCE select -assert-count 2 t:LUT3 -#Xilinx Vivado synthesizes LDCE cell for this case. Need support it. -select -assert-count 3 t:$_DLATCH_P_ -select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D + +select -assert-none t:LDCE t:LUT3 %% t:* %D -- cgit v1.2.3 From 36af10280136f0fda7b743075ac52e48576abf26 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 09:28:18 +0200 Subject: Test dffs separetely --- tests/xilinx/dffs.v | 22 ---------------------- tests/xilinx/dffs.ys | 23 +++++++++++++++++++---- 2 files changed, 19 insertions(+), 26 deletions(-) (limited to 'tests') diff --git a/tests/xilinx/dffs.v b/tests/xilinx/dffs.v index d97840c43..3418787c9 100644 --- a/tests/xilinx/dffs.v +++ b/tests/xilinx/dffs.v @@ -13,25 +13,3 @@ module dffe if ( en ) q <= d; endmodule - -module top ( -input clk, -input en, -input a, -output b,b1, -); - -dff u_dff ( - .clk (clk ), - .d (a ), - .q (b ) - ); - -dffe u_ndffe ( - .clk (clk ), - .en (en), - .d (a ), - .q (b1 ) - ); - -endmodule diff --git a/tests/xilinx/dffs.ys b/tests/xilinx/dffs.ys index 6a98994c0..2d48a816c 100644 --- a/tests/xilinx/dffs.ys +++ b/tests/xilinx/dffs.ys @@ -1,10 +1,25 @@ read_verilog dffs.v -hierarchy -top top +design -save read + proc -flatten +hierarchy -top dff equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd dff # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG -select -assert-count 2 t:FDRE +select -assert-count 1 t:FDRE + select -assert-none t:BUFG t:FDRE %% t:* %D + + +design -load read +proc +hierarchy -top dffe +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 1 t:FDRE + +select -assert-none t:BUFG t:FDRE %% t:* %D + -- cgit v1.2.3 From a198bcdd4ffe6b09787ea5bf2e69528ace375020 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 09:39:22 +0200 Subject: split muxes synth per type --- tests/xilinx/mux.v | 35 ----------------------------------- tests/xilinx/mux.ys | 43 +++++++++++++++++++++++++++++++++++++++---- 2 files changed, 39 insertions(+), 39 deletions(-) (limited to 'tests') diff --git a/tests/xilinx/mux.v b/tests/xilinx/mux.v index 0814b733e..27bc0bf0b 100644 --- a/tests/xilinx/mux.v +++ b/tests/xilinx/mux.v @@ -63,38 +63,3 @@ module mux16 (D, S, Y); assign Y = D[S]; endmodule - - -module top ( -input [3:0] S, -input [15:0] D, -output M2,M4,M8,M16 -); - -mux2 u_mux2 ( - .S (S[0]), - .A (D[0]), - .B (D[1]), - .Y (M2) - ); - - -mux4 u_mux4 ( - .S (S[1:0]), - .D (D[3:0]), - .Y (M4) - ); - -mux8 u_mux8 ( - .S (S[2:0]), - .D (D[7:0]), - .Y (M8) - ); - -mux16 u_mux16 ( - .S (S[3:0]), - .D (D[15:0]), - .Y (M16) - ); - -endmodule diff --git a/tests/xilinx/mux.ys b/tests/xilinx/mux.ys index 6ecee58f5..4cdb12e47 100644 --- a/tests/xilinx/mux.ys +++ b/tests/xilinx/mux.ys @@ -1,10 +1,45 @@ read_verilog mux.v +design -save read + +proc +hierarchy -top mux2 +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux2 # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT3 + +select -assert-none t:LUT3 %% t:* %D + + +design -load read proc -flatten +hierarchy -top mux4 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT6 + +select -assert-none t:LUT6 %% t:* %D + + +design -load read +proc +hierarchy -top mux8 +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT3 +select -assert-count 2 t:LUT6 -select -assert-count 2 t:LUT3 -select -assert-count 5 t:LUT6 select -assert-none t:LUT3 t:LUT6 %% t:* %D + + +design -load read +proc +hierarchy -top mux16 +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux16 # Constrain all select calls below inside the top module +select -assert-count 5 t:LUT6 + +select -assert-none t:LUT6 %% t:* %D -- cgit v1.2.3 From 1a399c6456b6ca7becf89a5c825b2c8d7b34dc3e Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 09:39:34 +0200 Subject: remove not needed top module --- tests/xilinx/tribuf.v | 15 --------------- tests/xilinx/tribuf.ys | 4 ++-- 2 files changed, 2 insertions(+), 17 deletions(-) (limited to 'tests') diff --git a/tests/xilinx/tribuf.v b/tests/xilinx/tribuf.v index 75149d8ba..c64468253 100644 --- a/tests/xilinx/tribuf.v +++ b/tests/xilinx/tribuf.v @@ -6,18 +6,3 @@ module tristate (en, i, o); always @(en or i) o <= (en)? i : 1'bZ; endmodule - - -module top ( -input en, -input a, -output b -); - -tristate u_tri ( - .en (en ), - .i (a ), - .o (b ) - ); - -endmodule diff --git a/tests/xilinx/tribuf.ys b/tests/xilinx/tribuf.ys index 696be2620..c9cfb8546 100644 --- a/tests/xilinx/tribuf.ys +++ b/tests/xilinx/tribuf.ys @@ -1,12 +1,12 @@ read_verilog tribuf.v -hierarchy -top top +hierarchy -top tristate proc tribuf flatten synth equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd tristate # Constrain all select calls below inside the top module # TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225 select -assert-count 1 t:$_TBUF_ select -assert-none t:$_TBUF_ %% t:* %D -- cgit v1.2.3 From b2f0d75807c99c74f9860098b74e8300514ba9e5 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 09:41:45 +0200 Subject: remove not needed top module --- tests/xilinx/fsm.v | 18 ------------------ tests/xilinx/fsm.ys | 4 ++-- 2 files changed, 2 insertions(+), 20 deletions(-) (limited to 'tests') diff --git a/tests/xilinx/fsm.v b/tests/xilinx/fsm.v index 0605bd102..368fbaace 100644 --- a/tests/xilinx/fsm.v +++ b/tests/xilinx/fsm.v @@ -52,22 +52,4 @@ endcase end - endmodule - - module top ( -input clk, -input rst, -input a, -input b, -output g0, -output g1 -); - -fsm u_fsm ( .clock(clk), - .reset(rst), - .req_0(a), - .req_1(b), - .gnt_0(g0), - .gnt_1(g1)); - endmodule diff --git a/tests/xilinx/fsm.ys b/tests/xilinx/fsm.ys index 3b73891c2..a9e94c2c0 100644 --- a/tests/xilinx/fsm.ys +++ b/tests/xilinx/fsm.ys @@ -1,10 +1,10 @@ read_verilog fsm.v -hierarchy -top top +hierarchy -top fsm proc flatten equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd fsm # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 5 t:FDRE -- cgit v1.2.3 From 980df499abb63e5dfadc29b3326032b55b6dbf18 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 17 Oct 2019 17:24:53 +0200 Subject: Make equivalence work with latest master --- tests/xilinx/adffs.ys | 8 ++++---- tests/xilinx/counter.ys | 2 +- tests/xilinx/latches.ys | 6 +++--- 3 files changed, 8 insertions(+), 8 deletions(-) (limited to 'tests') diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys index 2d23749ac..9e8ba44ab 100644 --- a/tests/xilinx/adffs.ys +++ b/tests/xilinx/adffs.ys @@ -3,7 +3,7 @@ design -save read proc hierarchy -top adff -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adff # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG @@ -15,7 +15,7 @@ select -assert-none t:BUFG t:FDCE %% t:* %D design -load read proc hierarchy -top adffn -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adffn # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG @@ -28,7 +28,7 @@ select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D design -load read proc hierarchy -top dffs -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffs # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG @@ -41,7 +41,7 @@ select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D design -load read proc hierarchy -top ndffnr -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd ndffnr # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG diff --git a/tests/xilinx/counter.ys b/tests/xilinx/counter.ys index 3bb3a8eb0..459541656 100644 --- a/tests/xilinx/counter.ys +++ b/tests/xilinx/counter.ys @@ -2,7 +2,7 @@ read_verilog counter.v hierarchy -top top proc flatten -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys index 68ca42b10..52e96834d 100644 --- a/tests/xilinx/latches.ys +++ b/tests/xilinx/latches.ys @@ -3,7 +3,7 @@ design -save read proc hierarchy -top latchp -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd latchp # Constrain all select calls below inside the top module select -assert-count 1 t:LDCE @@ -14,7 +14,7 @@ select -assert-none t:LDCE %% t:* %D design -load read proc hierarchy -top latchn -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd latchn # Constrain all select calls below inside the top module select -assert-count 1 t:LDCE @@ -26,7 +26,7 @@ select -assert-none t:LDCE t:LUT1 %% t:* %D design -load read proc hierarchy -top latchsr -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd latchsr # Constrain all select calls below inside the top module select -assert-count 1 t:LDCE -- cgit v1.2.3 From e6ad714d20134612521e995c72e4fa06ed791dd3 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 08:06:57 +0200 Subject: hierarchy - proc reorder --- tests/xilinx/.gitignore | 2 +- tests/xilinx/add_sub.ys | 1 + tests/xilinx/adffs.ys | 8 ++++---- tests/xilinx/dffs.ys | 4 ++-- tests/xilinx/latches.ys | 6 +++--- tests/xilinx/logic.ys | 1 + tests/xilinx/macc.ys | 4 ++-- tests/xilinx/mul.ys | 1 + tests/xilinx/mul_unsigned.ys | 3 ++- tests/xilinx/mux.ys | 8 ++++---- 10 files changed, 21 insertions(+), 17 deletions(-) (limited to 'tests') diff --git a/tests/xilinx/.gitignore b/tests/xilinx/.gitignore index 89879f209..c99b79371 100644 --- a/tests/xilinx/.gitignore +++ b/tests/xilinx/.gitignore @@ -2,4 +2,4 @@ /*.out /run-test.mk /*_uut.v -/test_macc \ No newline at end of file +/test_macc diff --git a/tests/xilinx/add_sub.ys b/tests/xilinx/add_sub.ys index 821341f20..f06e7fa01 100644 --- a/tests/xilinx/add_sub.ys +++ b/tests/xilinx/add_sub.ys @@ -1,5 +1,6 @@ read_verilog add_sub.v hierarchy -top top +proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys index 9e8ba44ab..1923b9802 100644 --- a/tests/xilinx/adffs.ys +++ b/tests/xilinx/adffs.ys @@ -1,8 +1,8 @@ read_verilog adffs.v design -save read -proc hierarchy -top adff +proc equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adff # Constrain all select calls below inside the top module @@ -13,8 +13,8 @@ select -assert-none t:BUFG t:FDCE %% t:* %D design -load read -proc hierarchy -top adffn +proc equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adffn # Constrain all select calls below inside the top module @@ -26,8 +26,8 @@ select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D design -load read -proc hierarchy -top dffs +proc equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffs # Constrain all select calls below inside the top module @@ -39,8 +39,8 @@ select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D design -load read -proc hierarchy -top ndffnr +proc equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd ndffnr # Constrain all select calls below inside the top module diff --git a/tests/xilinx/dffs.ys b/tests/xilinx/dffs.ys index 2d48a816c..f1716dabb 100644 --- a/tests/xilinx/dffs.ys +++ b/tests/xilinx/dffs.ys @@ -1,8 +1,8 @@ read_verilog dffs.v design -save read -proc hierarchy -top dff +proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dff # Constrain all select calls below inside the top module @@ -13,8 +13,8 @@ select -assert-none t:BUFG t:FDRE %% t:* %D design -load read -proc hierarchy -top dffe +proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys index 52e96834d..3eb550a42 100644 --- a/tests/xilinx/latches.ys +++ b/tests/xilinx/latches.ys @@ -1,8 +1,8 @@ read_verilog latches.v design -save read -proc hierarchy -top latchp +proc equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd latchp # Constrain all select calls below inside the top module @@ -12,8 +12,8 @@ select -assert-none t:LDCE %% t:* %D design -load read -proc hierarchy -top latchn +proc equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd latchn # Constrain all select calls below inside the top module @@ -24,8 +24,8 @@ select -assert-none t:LDCE t:LUT1 %% t:* %D design -load read -proc hierarchy -top latchsr +proc equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd latchsr # Constrain all select calls below inside the top module diff --git a/tests/xilinx/logic.ys b/tests/xilinx/logic.ys index e138ae6a3..9ae5993aa 100644 --- a/tests/xilinx/logic.ys +++ b/tests/xilinx/logic.ys @@ -1,5 +1,6 @@ read_verilog logic.v hierarchy -top top +proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/xilinx/macc.ys b/tests/xilinx/macc.ys index 417a3b21b..6e884b35a 100644 --- a/tests/xilinx/macc.ys +++ b/tests/xilinx/macc.ys @@ -1,8 +1,8 @@ read_verilog macc.v design -save read -proc hierarchy -top macc +proc #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx miter -equiv -flatten -make_assert -make_outputs gold gate miter @@ -15,8 +15,8 @@ select -assert-count 1 t:DSP48E1 select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D design -load read -proc hierarchy -top macc2 +proc #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx miter -equiv -flatten -make_assert -make_outputs gold gate miter diff --git a/tests/xilinx/mul.ys b/tests/xilinx/mul.ys index f5306e848..66a06efdc 100644 --- a/tests/xilinx/mul.ys +++ b/tests/xilinx/mul.ys @@ -1,5 +1,6 @@ read_verilog mul.v hierarchy -top top +proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/xilinx/mul_unsigned.ys b/tests/xilinx/mul_unsigned.ys index 77990bd68..62495b90c 100644 --- a/tests/xilinx/mul_unsigned.ys +++ b/tests/xilinx/mul_unsigned.ys @@ -1,6 +1,7 @@ read_verilog mul_unsigned.v -proc hierarchy -top mul_unsigned +proc + equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mul_unsigned # Constrain all select calls below inside the top module diff --git a/tests/xilinx/mux.ys b/tests/xilinx/mux.ys index 4cdb12e47..420dece4e 100644 --- a/tests/xilinx/mux.ys +++ b/tests/xilinx/mux.ys @@ -1,8 +1,8 @@ read_verilog mux.v design -save read -proc hierarchy -top mux2 +proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux2 # Constrain all select calls below inside the top module @@ -12,8 +12,8 @@ select -assert-none t:LUT3 %% t:* %D design -load read -proc hierarchy -top mux4 +proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module @@ -23,8 +23,8 @@ select -assert-none t:LUT6 %% t:* %D design -load read -proc hierarchy -top mux8 +proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module @@ -35,8 +35,8 @@ select -assert-none t:LUT3 t:LUT6 %% t:* %D design -load read -proc hierarchy -top mux16 +proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -- cgit v1.2.3 From 0d60902fd97bba4f231f8f600434b8a69562ffff Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 09:04:02 +0200 Subject: hierarchy - proc reorder --- tests/ecp5/add_sub.ys | 1 + tests/ecp5/adffs.ys | 8 ++++---- tests/ecp5/dffs.ys | 4 ++-- tests/ecp5/latches.ys | 6 +++--- tests/ecp5/logic.ys | 1 + tests/ecp5/macc.ys | 2 +- tests/ecp5/mul.ys | 1 + tests/ecp5/mux.ys | 8 ++++---- tests/ecp5/rom.ys | 1 + 9 files changed, 18 insertions(+), 14 deletions(-) (limited to 'tests') diff --git a/tests/ecp5/add_sub.ys b/tests/ecp5/add_sub.ys index 03aec6694..ee72d732f 100644 --- a/tests/ecp5/add_sub.ys +++ b/tests/ecp5/add_sub.ys @@ -1,5 +1,6 @@ read_verilog add_sub.v hierarchy -top top +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys index 658f302d0..b129419d3 100644 --- a/tests/ecp5/adffs.ys +++ b/tests/ecp5/adffs.ys @@ -1,8 +1,8 @@ read_verilog adffs.v design -save read -proc hierarchy -top adff +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adff # Constrain all select calls below inside the top module @@ -10,8 +10,8 @@ select -assert-count 1 t:TRELLIS_FF select -assert-none t:TRELLIS_FF %% t:* %D design -load read -proc hierarchy -top adffn +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adffn # Constrain all select calls below inside the top module @@ -20,8 +20,8 @@ select -assert-count 1 t:LUT4 select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D design -load read -proc hierarchy -top dffs +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffs # Constrain all select calls below inside the top module @@ -30,8 +30,8 @@ select -assert-count 1 t:LUT4 select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D design -load read -proc hierarchy -top ndffnr +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd ndffnr # Constrain all select calls below inside the top module diff --git a/tests/ecp5/dffs.ys b/tests/ecp5/dffs.ys index 93b8595ad..a4f45d2fb 100644 --- a/tests/ecp5/dffs.ys +++ b/tests/ecp5/dffs.ys @@ -1,8 +1,8 @@ read_verilog dffs.v design -save read -proc hierarchy -top dff +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dff # Constrain all select calls below inside the top module @@ -10,8 +10,8 @@ select -assert-count 1 t:TRELLIS_FF select -assert-none t:TRELLIS_FF %% t:* %D design -load read -proc hierarchy -top dffe +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module diff --git a/tests/ecp5/latches.ys b/tests/ecp5/latches.ys index f32998232..fc15a6910 100644 --- a/tests/ecp5/latches.ys +++ b/tests/ecp5/latches.ys @@ -2,8 +2,8 @@ read_verilog latches.v design -save read -proc hierarchy -top latchp +proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_ecp5 cd latchp # Constrain all select calls below inside the top module @@ -13,8 +13,8 @@ select -assert-none t:LUT4 %% t:* %D design -load read -proc hierarchy -top latchn +proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_ecp5 cd latchn # Constrain all select calls below inside the top module @@ -24,8 +24,8 @@ select -assert-none t:LUT4 %% t:* %D design -load read -proc hierarchy -top latchsr +proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_ecp5 cd latchsr # Constrain all select calls below inside the top module diff --git a/tests/ecp5/logic.ys b/tests/ecp5/logic.ys index 34125fea9..4f113a130 100644 --- a/tests/ecp5/logic.ys +++ b/tests/ecp5/logic.ys @@ -1,5 +1,6 @@ read_verilog logic.v hierarchy -top top +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/ecp5/macc.ys b/tests/ecp5/macc.ys index f60281a54..1863ea4d2 100644 --- a/tests/ecp5/macc.ys +++ b/tests/ecp5/macc.ys @@ -1,6 +1,6 @@ read_verilog macc.v -proc hierarchy -top top +proc # Blocked by issue #1358 (Missing ECP5 simulation models) #equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check diff --git a/tests/ecp5/mul.ys b/tests/ecp5/mul.ys index 132340664..0a91f892e 100644 --- a/tests/ecp5/mul.ys +++ b/tests/ecp5/mul.ys @@ -1,5 +1,6 @@ read_verilog mul.v hierarchy -top top +proc # Blocked by issue #1358 (Missing ECP5 simulation models) #equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check diff --git a/tests/ecp5/mux.ys b/tests/ecp5/mux.ys index eada276ba..8cfbd541b 100644 --- a/tests/ecp5/mux.ys +++ b/tests/ecp5/mux.ys @@ -1,8 +1,8 @@ read_verilog mux.v design -save read -proc hierarchy -top mux2 +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux2 # Constrain all select calls below inside the top module @@ -10,8 +10,8 @@ select -assert-count 1 t:LUT4 select -assert-none t:LUT4 %% t:* %D design -load read -proc hierarchy -top mux4 +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module @@ -22,8 +22,8 @@ select -assert-count 2 t:PFUMX select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D design -load read -proc hierarchy -top mux8 +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module @@ -34,8 +34,8 @@ select -assert-count 2 t:PFUMX select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D design -load read -proc hierarchy -top mux16 +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module diff --git a/tests/ecp5/rom.ys b/tests/ecp5/rom.ys index 8a52749a1..98645ae43 100644 --- a/tests/ecp5/rom.ys +++ b/tests/ecp5/rom.ys @@ -1,4 +1,5 @@ read_verilog rom.v +hierarchy -top top proc flatten equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -- cgit v1.2.3 From 46af9a0ff7727c2d47b1dc12501e3328cba1f2e9 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 09:06:43 +0200 Subject: hierarchy - proc reorder --- tests/anlogic/add_sub.ys | 1 + tests/anlogic/dffs.ys | 4 ++-- tests/anlogic/latches.ys | 6 +++--- tests/anlogic/mux.ys | 8 ++++---- 4 files changed, 10 insertions(+), 9 deletions(-) (limited to 'tests') diff --git a/tests/anlogic/add_sub.ys b/tests/anlogic/add_sub.ys index 994cd0d03..b8b67cc46 100644 --- a/tests/anlogic/add_sub.ys +++ b/tests/anlogic/add_sub.ys @@ -1,5 +1,6 @@ read_verilog add_sub.v hierarchy -top top +proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/anlogic/dffs.ys b/tests/anlogic/dffs.ys index 38dffa326..9cbe5fce7 100644 --- a/tests/anlogic/dffs.ys +++ b/tests/anlogic/dffs.ys @@ -1,8 +1,8 @@ read_verilog dffs.v design -save read -proc hierarchy -top dff +proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dff # Constrain all select calls below inside the top module @@ -10,8 +10,8 @@ select -assert-count 1 t:AL_MAP_SEQ select -assert-none t:AL_MAP_SEQ %% t:* %D design -load read -proc hierarchy -top dffe +proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module diff --git a/tests/anlogic/latches.ys b/tests/anlogic/latches.ys index ae9e15ff8..c00c7a25d 100644 --- a/tests/anlogic/latches.ys +++ b/tests/anlogic/latches.ys @@ -1,8 +1,8 @@ read_verilog latches.v design -save read -proc hierarchy -top latchp +proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_anlogic cd latchp # Constrain all select calls below inside the top module @@ -12,8 +12,8 @@ select -assert-none t:AL_MAP_LUT3 %% t:* %D design -load read -proc hierarchy -top latchn +proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_anlogic cd latchn # Constrain all select calls below inside the top module @@ -23,8 +23,8 @@ select -assert-none t:AL_MAP_LUT3 %% t:* %D design -load read -proc hierarchy -top latchsr +proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_anlogic cd latchsr # Constrain all select calls below inside the top module diff --git a/tests/anlogic/mux.ys b/tests/anlogic/mux.ys index 354fc836c..64ed2a2bd 100644 --- a/tests/anlogic/mux.ys +++ b/tests/anlogic/mux.ys @@ -1,8 +1,8 @@ read_verilog mux.v design -save read -proc hierarchy -top mux2 +proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux2 # Constrain all select calls below inside the top module @@ -11,8 +11,8 @@ select -assert-count 1 t:AL_MAP_LUT3 select -assert-none t:AL_MAP_LUT3 %% t:* %D design -load read -proc hierarchy -top mux4 +proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module @@ -21,8 +21,8 @@ select -assert-count 1 t:AL_MAP_LUT6 select -assert-none t:AL_MAP_LUT6 %% t:* %D design -load read -proc hierarchy -top mux8 +proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module @@ -32,8 +32,8 @@ select -assert-count 1 t:AL_MAP_LUT6 select -assert-none t:AL_MAP_LUT4 t:AL_MAP_LUT6 %% t:* %D design -load read -proc hierarchy -top mux16 +proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -- cgit v1.2.3