From 39fdcb892b1b65363fdf7c1bc6d9e2612c1c38e6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 21 Nov 2019 16:27:34 -0800 Subject: async2sync -> clk2fflogic --- tests/various/abc9.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys index 9e732bdc8..f7a3f1fa0 100644 --- a/tests/various/abc9.ys +++ b/tests/various/abc9.ys @@ -26,7 +26,7 @@ select -assert-none t:$lut t:unknown %% t: %D design -load read hierarchy -top abc9_test031 proc -async2sync +clk2fflogic design -save gold abc9 -lut 4 -- cgit v1.2.3 From 6841e3b1c2b2bc3124810f3a8f96ed00a96e954c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 21 Nov 2019 16:33:20 -0800 Subject: Another sloppy mistake! --- tests/various/abc9.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/various/abc9.v b/tests/various/abc9.v index 85828bf30..f0b3f6837 100644 --- a/tests/various/abc9.v +++ b/tests/various/abc9.v @@ -13,6 +13,6 @@ endmodule module abc9_test032(input clk, d, r, output reg q); initial q = 1'b0; always @(negedge clk or negedge r) - if (r) q <= 1'b0; + if (!r) q <= 1'b0; else q <= d; endmodule -- cgit v1.2.3