From 6c79abbf5a3f0ea44f119d1f1ab3262778cf99ce Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Mon, 25 Nov 2019 14:33:21 +0100 Subject: gowin: add and test dff init values --- tests/arch/gowin/init.v | 224 +++++++++++++++++++++++++++++++++++++++++++++++ tests/arch/gowin/init.ys | 72 +++++++++++++++ 2 files changed, 296 insertions(+) create mode 100644 tests/arch/gowin/init.v create mode 100644 tests/arch/gowin/init.ys (limited to 'tests') diff --git a/tests/arch/gowin/init.v b/tests/arch/gowin/init.v new file mode 100644 index 000000000..b51432d0c --- /dev/null +++ b/tests/arch/gowin/init.v @@ -0,0 +1,224 @@ +module myDFF (output reg Q, input CLK, D); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(posedge CLK) + Q <= D; +endmodule + +module myDFFE (output reg Q, input D, CLK, CE); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(posedge CLK) begin + if (CE) + Q <= D; + end +endmodule // DFFE (positive clock edge; clock enable) + + +module myDFFS (output reg Q, input D, CLK, SET); + parameter [0:0] INIT = 1'b1; + initial Q = INIT; + always @(posedge CLK) begin + if (SET) + Q <= 1'b1; + else + Q <= D; + end +endmodule // DFFS (positive clock edge; synchronous set) + + +module myDFFSE (output reg Q, input D, CLK, CE, SET); + parameter [0:0] INIT = 1'b1; + initial Q = INIT; + always @(posedge CLK) begin + if (SET) + Q <= 1'b1; + else if (CE) + Q <= D; +end +endmodule // DFFSE (positive clock edge; synchronous set takes precedence over clock enable) + + +module myDFFR (output reg Q, input D, CLK, RESET); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(posedge CLK) begin + if (RESET) + Q <= 1'b0; + else + Q <= D; + end +endmodule // DFFR (positive clock edge; synchronous reset) + + +module myDFFRE (output reg Q, input D, CLK, CE, RESET); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(posedge CLK) begin + if (RESET) + Q <= 1'b0; + else if (CE) + Q <= D; + end +endmodule // DFFRE (positive clock edge; synchronous reset takes precedence over clock enable) + + +module myDFFP (output reg Q, input D, CLK, PRESET); + parameter [0:0] INIT = 1'b1; + initial Q = INIT; + always @(posedge CLK or posedge PRESET) begin + if(PRESET) + Q <= 1'b1; + else + Q <= D; + end +endmodule // DFFP (positive clock edge; asynchronous preset) + + +module myDFFPE (output reg Q, input D, CLK, CE, PRESET); + parameter [0:0] INIT = 1'b1; + initial Q = INIT; + always @(posedge CLK or posedge PRESET) begin + if(PRESET) + Q <= 1'b1; + else if (CE) + Q <= D; + end +endmodule // DFFPE (positive clock edge; asynchronous preset; clock enable) + + +module myDFFC (output reg Q, input D, CLK, CLEAR); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(posedge CLK or posedge CLEAR) begin + if(CLEAR) + Q <= 1'b0; + else + Q <= D; + end +endmodule // DFFC (positive clock edge; asynchronous clear) + + +module myDFFCE (output reg Q, input D, CLK, CE, CLEAR); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(posedge CLK or posedge CLEAR) begin + if(CLEAR) + Q <= 1'b0; + else if (CE) + Q <= D; + end +endmodule // DFFCE (positive clock edge; asynchronous clear; clock enable) + + +module myDFFN (output reg Q, input CLK, D); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(negedge CLK) + Q <= D; +endmodule + +module myDFFNE (output reg Q, input D, CLK, CE); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(negedge CLK) begin + if (CE) + Q <= D; + end +endmodule // DFFNE (negative clock edge; clock enable) + + +module myDFFNS (output reg Q, input D, CLK, SET); + parameter [0:0] INIT = 1'b1; + initial Q = INIT; + always @(negedge CLK) begin + if (SET) + Q <= 1'b1; + else + Q <= D; + end +endmodule // DFFNS (negative clock edge; synchronous set) + + +module myDFFNSE (output reg Q, input D, CLK, CE, SET); + parameter [0:0] INIT = 1'b1; + initial Q = INIT; + always @(negedge CLK) begin + if (SET) + Q <= 1'b1; + else if (CE) + Q <= D; +end +endmodule // DFFNSE (negative clock edge; synchronous set takes precedence over clock enable) + + +module myDFFNR (output reg Q, input D, CLK, RESET); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(negedge CLK) begin + if (RESET) + Q <= 1'b0; + else + Q <= D; + end +endmodule // DFFNR (negative clock edge; synchronous reset) + + +module myDFFNRE (output reg Q, input D, CLK, CE, RESET); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(negedge CLK) begin + if (RESET) + Q <= 1'b0; + else if (CE) + Q <= D; + end +endmodule // DFFNRE (negative clock edge; synchronous reset takes precedence over clock enable) + + +module myDFFNP (output reg Q, input D, CLK, PRESET); + parameter [0:0] INIT = 1'b1; + initial Q = INIT; + always @(negedge CLK or posedge PRESET) begin + if(PRESET) + Q <= 1'b1; + else + Q <= D; + end +endmodule // DFFNP (negative clock edge; asynchronous preset) + + +module myDFFNPE (output reg Q, input D, CLK, CE, PRESET); + parameter [0:0] INIT = 1'b1; + initial Q = INIT; + always @(negedge CLK or posedge PRESET) begin + if(PRESET) + Q <= 1'b1; + else if (CE) + Q <= D; + end +endmodule // DFFNPE (negative clock edge; asynchronous preset; clock enable) + + +module myDFFNC (output reg Q, input D, CLK, CLEAR); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(negedge CLK or posedge CLEAR) begin + if(CLEAR) + Q <= 1'b0; + else + Q <= D; + end +endmodule // DFFNC (negative clock edge; asynchronous clear) + + +module myDFFNCE (output reg Q, input D, CLK, CE, CLEAR); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(negedge CLK or posedge CLEAR) begin + if(CLEAR) + Q <= 1'b0; + else if (CE) + Q <= D; + end +endmodule // DFFNCE (negative clock edge; asynchronous clear; clock enable) diff --git a/tests/arch/gowin/init.ys b/tests/arch/gowin/init.ys new file mode 100644 index 000000000..dc8206825 --- /dev/null +++ b/tests/arch/gowin/init.ys @@ -0,0 +1,72 @@ +read_verilog init.v +read_verilog -lib +/gowin/cells_sim.v +design -save read + +proc +flatten +synth_gowin -run coarse: + +# check if all init values are handled +check -assert -noinit +# check if every flop mapped correctly +select -assert-count 1 t:DFF +select -assert-count 1 t:DFFC +select -assert-count 1 t:DFFCE +select -assert-count 1 t:DFFE +select -assert-count 1 t:DFFN +select -assert-count 1 t:DFFNC +select -assert-count 1 t:DFFNCE +select -assert-count 1 t:DFFNE +select -assert-count 1 t:DFFNP +select -assert-count 1 t:DFFNPE +select -assert-count 1 t:DFFNR +select -assert-count 1 t:DFFNRE +select -assert-count 1 t:DFFNS +select -assert-count 1 t:DFFNSE +select -assert-count 1 t:DFFP +select -assert-count 1 t:DFFPE +select -assert-count 1 t:DFFR +select -assert-count 1 t:DFFRE +select -assert-count 1 t:DFFS +select -assert-count 1 t:DFFSE + +delete +design -load read + +# these should synth to a flop with reset +chparam -set INIT 1 myDFF myDFFN myDFFE myDFFNE + +# these should give a warning +chparam -set INIT 0 myDFF*S* myDFF*P* +chparam -set INIT 1 myDFF*R* myDFF*C* + +proc +flatten +synth_gowin -run coarse: + +# check the flops mapped as expected +select -assert-count 0 t:DFF +select -assert-count 1 t:DFFC +select -assert-count 1 t:DFFCE +select -assert-count 0 t:DFFE +select -assert-count 0 t:DFFN +select -assert-count 1 t:DFFNC +select -assert-count 1 t:DFFNCE +select -assert-count 0 t:DFFNE +select -assert-count 1 t:DFFNP +select -assert-count 1 t:DFFNPE +select -assert-count 1 t:DFFNR +select -assert-count 1 t:DFFNRE +select -assert-count 2 t:DFFNS +select -assert-count 2 t:DFFNSE +select -assert-count 1 t:DFFP +select -assert-count 1 t:DFFPE +select -assert-count 1 t:DFFR +select -assert-count 1 t:DFFRE +select -assert-count 2 t:DFFS +select -assert-count 2 t:DFFSE + +# check the expected leftover init values +# this would happen if your reset value is not the initial value +# which would be weird +select -assert-count 16 a:init -- cgit v1.2.3 From 72d03dc910da379779f2f7a0a0406dd61593d696 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Mon, 25 Nov 2019 14:50:34 +0100 Subject: attempt to fix formatting --- tests/arch/gowin/init.v | 276 ++++++++++++++++++++++++------------------------ 1 file changed, 138 insertions(+), 138 deletions(-) (limited to 'tests') diff --git a/tests/arch/gowin/init.v b/tests/arch/gowin/init.v index b51432d0c..3c30f602d 100644 --- a/tests/arch/gowin/init.v +++ b/tests/arch/gowin/init.v @@ -6,108 +6,108 @@ module myDFF (output reg Q, input CLK, D); endmodule module myDFFE (output reg Q, input D, CLK, CE); - parameter [0:0] INIT = 1'b0; - initial Q = INIT; - always @(posedge CLK) begin - if (CE) - Q <= D; - end + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(posedge CLK) begin + if (CE) + Q <= D; + end endmodule // DFFE (positive clock edge; clock enable) module myDFFS (output reg Q, input D, CLK, SET); - parameter [0:0] INIT = 1'b1; - initial Q = INIT; - always @(posedge CLK) begin - if (SET) - Q <= 1'b1; - else - Q <= D; - end + parameter [0:0] INIT = 1'b1; + initial Q = INIT; + always @(posedge CLK) begin + if (SET) + Q <= 1'b1; + else + Q <= D; + end endmodule // DFFS (positive clock edge; synchronous set) module myDFFSE (output reg Q, input D, CLK, CE, SET); - parameter [0:0] INIT = 1'b1; - initial Q = INIT; - always @(posedge CLK) begin - if (SET) - Q <= 1'b1; - else if (CE) - Q <= D; + parameter [0:0] INIT = 1'b1; + initial Q = INIT; + always @(posedge CLK) begin + if (SET) + Q <= 1'b1; + else if (CE) + Q <= D; end endmodule // DFFSE (positive clock edge; synchronous set takes precedence over clock enable) module myDFFR (output reg Q, input D, CLK, RESET); - parameter [0:0] INIT = 1'b0; - initial Q = INIT; - always @(posedge CLK) begin - if (RESET) - Q <= 1'b0; - else - Q <= D; - end + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(posedge CLK) begin + if (RESET) + Q <= 1'b0; + else + Q <= D; + end endmodule // DFFR (positive clock edge; synchronous reset) module myDFFRE (output reg Q, input D, CLK, CE, RESET); - parameter [0:0] INIT = 1'b0; - initial Q = INIT; - always @(posedge CLK) begin - if (RESET) - Q <= 1'b0; - else if (CE) - Q <= D; - end + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(posedge CLK) begin + if (RESET) + Q <= 1'b0; + else if (CE) + Q <= D; + end endmodule // DFFRE (positive clock edge; synchronous reset takes precedence over clock enable) module myDFFP (output reg Q, input D, CLK, PRESET); - parameter [0:0] INIT = 1'b1; - initial Q = INIT; - always @(posedge CLK or posedge PRESET) begin - if(PRESET) - Q <= 1'b1; - else - Q <= D; - end + parameter [0:0] INIT = 1'b1; + initial Q = INIT; + always @(posedge CLK or posedge PRESET) begin + if(PRESET) + Q <= 1'b1; + else + Q <= D; + end endmodule // DFFP (positive clock edge; asynchronous preset) module myDFFPE (output reg Q, input D, CLK, CE, PRESET); - parameter [0:0] INIT = 1'b1; - initial Q = INIT; - always @(posedge CLK or posedge PRESET) begin - if(PRESET) - Q <= 1'b1; - else if (CE) - Q <= D; - end + parameter [0:0] INIT = 1'b1; + initial Q = INIT; + always @(posedge CLK or posedge PRESET) begin + if(PRESET) + Q <= 1'b1; + else if (CE) + Q <= D; + end endmodule // DFFPE (positive clock edge; asynchronous preset; clock enable) module myDFFC (output reg Q, input D, CLK, CLEAR); - parameter [0:0] INIT = 1'b0; - initial Q = INIT; - always @(posedge CLK or posedge CLEAR) begin - if(CLEAR) - Q <= 1'b0; - else - Q <= D; - end + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(posedge CLK or posedge CLEAR) begin + if(CLEAR) + Q <= 1'b0; + else + Q <= D; + end endmodule // DFFC (positive clock edge; asynchronous clear) module myDFFCE (output reg Q, input D, CLK, CE, CLEAR); - parameter [0:0] INIT = 1'b0; - initial Q = INIT; - always @(posedge CLK or posedge CLEAR) begin - if(CLEAR) - Q <= 1'b0; - else if (CE) - Q <= D; - end + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(posedge CLK or posedge CLEAR) begin + if(CLEAR) + Q <= 1'b0; + else if (CE) + Q <= D; + end endmodule // DFFCE (positive clock edge; asynchronous clear; clock enable) @@ -119,106 +119,106 @@ module myDFFN (output reg Q, input CLK, D); endmodule module myDFFNE (output reg Q, input D, CLK, CE); - parameter [0:0] INIT = 1'b0; - initial Q = INIT; - always @(negedge CLK) begin - if (CE) - Q <= D; - end + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(negedge CLK) begin + if (CE) + Q <= D; + end endmodule // DFFNE (negative clock edge; clock enable) module myDFFNS (output reg Q, input D, CLK, SET); - parameter [0:0] INIT = 1'b1; - initial Q = INIT; - always @(negedge CLK) begin - if (SET) - Q <= 1'b1; - else - Q <= D; - end + parameter [0:0] INIT = 1'b1; + initial Q = INIT; + always @(negedge CLK) begin + if (SET) + Q <= 1'b1; + else + Q <= D; + end endmodule // DFFNS (negative clock edge; synchronous set) module myDFFNSE (output reg Q, input D, CLK, CE, SET); - parameter [0:0] INIT = 1'b1; - initial Q = INIT; - always @(negedge CLK) begin - if (SET) - Q <= 1'b1; - else if (CE) - Q <= D; + parameter [0:0] INIT = 1'b1; + initial Q = INIT; + always @(negedge CLK) begin + if (SET) + Q <= 1'b1; + else if (CE) + Q <= D; end endmodule // DFFNSE (negative clock edge; synchronous set takes precedence over clock enable) module myDFFNR (output reg Q, input D, CLK, RESET); - parameter [0:0] INIT = 1'b0; - initial Q = INIT; - always @(negedge CLK) begin - if (RESET) - Q <= 1'b0; - else - Q <= D; - end + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(negedge CLK) begin + if (RESET) + Q <= 1'b0; + else + Q <= D; + end endmodule // DFFNR (negative clock edge; synchronous reset) module myDFFNRE (output reg Q, input D, CLK, CE, RESET); - parameter [0:0] INIT = 1'b0; - initial Q = INIT; - always @(negedge CLK) begin - if (RESET) - Q <= 1'b0; - else if (CE) - Q <= D; - end + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(negedge CLK) begin + if (RESET) + Q <= 1'b0; + else if (CE) + Q <= D; + end endmodule // DFFNRE (negative clock edge; synchronous reset takes precedence over clock enable) module myDFFNP (output reg Q, input D, CLK, PRESET); - parameter [0:0] INIT = 1'b1; - initial Q = INIT; - always @(negedge CLK or posedge PRESET) begin - if(PRESET) - Q <= 1'b1; - else - Q <= D; - end + parameter [0:0] INIT = 1'b1; + initial Q = INIT; + always @(negedge CLK or posedge PRESET) begin + if(PRESET) + Q <= 1'b1; + else + Q <= D; + end endmodule // DFFNP (negative clock edge; asynchronous preset) module myDFFNPE (output reg Q, input D, CLK, CE, PRESET); - parameter [0:0] INIT = 1'b1; - initial Q = INIT; - always @(negedge CLK or posedge PRESET) begin - if(PRESET) - Q <= 1'b1; - else if (CE) - Q <= D; - end + parameter [0:0] INIT = 1'b1; + initial Q = INIT; + always @(negedge CLK or posedge PRESET) begin + if(PRESET) + Q <= 1'b1; + else if (CE) + Q <= D; + end endmodule // DFFNPE (negative clock edge; asynchronous preset; clock enable) module myDFFNC (output reg Q, input D, CLK, CLEAR); - parameter [0:0] INIT = 1'b0; - initial Q = INIT; - always @(negedge CLK or posedge CLEAR) begin - if(CLEAR) - Q <= 1'b0; - else - Q <= D; - end + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(negedge CLK or posedge CLEAR) begin + if(CLEAR) + Q <= 1'b0; + else + Q <= D; + end endmodule // DFFNC (negative clock edge; asynchronous clear) module myDFFNCE (output reg Q, input D, CLK, CE, CLEAR); - parameter [0:0] INIT = 1'b0; - initial Q = INIT; - always @(negedge CLK or posedge CLEAR) begin - if(CLEAR) - Q <= 1'b0; - else if (CE) - Q <= D; - end + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(negedge CLK or posedge CLEAR) begin + if(CLEAR) + Q <= 1'b0; + else if (CE) + Q <= D; + end endmodule // DFFNCE (negative clock edge; asynchronous clear; clock enable) -- cgit v1.2.3 From e9ce4e658b2dddfc808e1d0383a5b93a906e2bbb Mon Sep 17 00:00:00 2001 From: David Shah Date: Sun, 1 Dec 2019 20:44:56 +0000 Subject: abc9: Fix breaking of SCCs Signed-off-by: David Shah --- tests/simple_abc9/abc9.v | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'tests') diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 4d5879e6f..de60619d1 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -258,3 +258,9 @@ module abc9_test026(output [3:0] o, p); assign o = { 1'b1, 1'bx }; assign p = { 1'b1, 1'bx, 1'b0 }; endmodule + +module abc9_test030(input [3:0] d, input en, output reg [3:0] q); +always @* + if (en) + q <= d; +endmodule -- cgit v1.2.3 From a3b25b4af899b78d7401ec2ea7cd988d6209e226 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Tue, 3 Dec 2019 15:12:25 +0100 Subject: Use -match-init to not synth contradicting init values --- tests/arch/gowin/init.ys | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) (limited to 'tests') diff --git a/tests/arch/gowin/init.ys b/tests/arch/gowin/init.ys index dc8206825..ddc0e4757 100644 --- a/tests/arch/gowin/init.ys +++ b/tests/arch/gowin/init.ys @@ -36,7 +36,8 @@ design -load read # these should synth to a flop with reset chparam -set INIT 1 myDFF myDFFN myDFFE myDFFNE -# these should give a warning +# async should give a warning +# sync should synth to a mux chparam -set INIT 0 myDFF*S* myDFF*P* chparam -set INIT 1 myDFF*R* myDFF*C* @@ -45,28 +46,29 @@ flatten synth_gowin -run coarse: # check the flops mapped as expected -select -assert-count 0 t:DFF +select -assert-count 1 t:DFF select -assert-count 1 t:DFFC select -assert-count 1 t:DFFCE -select -assert-count 0 t:DFFE -select -assert-count 0 t:DFFN +select -assert-count 1 t:DFFE +select -assert-count 1 t:DFFN select -assert-count 1 t:DFFNC select -assert-count 1 t:DFFNCE -select -assert-count 0 t:DFFNE +select -assert-count 1 t:DFFNE select -assert-count 1 t:DFFNP select -assert-count 1 t:DFFNPE -select -assert-count 1 t:DFFNR -select -assert-count 1 t:DFFNRE +select -assert-count 0 t:DFFNR +select -assert-count 0 t:DFFNRE select -assert-count 2 t:DFFNS select -assert-count 2 t:DFFNSE select -assert-count 1 t:DFFP select -assert-count 1 t:DFFPE -select -assert-count 1 t:DFFR -select -assert-count 1 t:DFFRE +select -assert-count 0 t:DFFR +select -assert-count 0 t:DFFRE select -assert-count 2 t:DFFS select -assert-count 2 t:DFFSE +select -assert-count 12 t:LUT2 # check the expected leftover init values # this would happen if your reset value is not the initial value # which would be weird -select -assert-count 16 a:init +select -assert-count 8 a:init -- cgit v1.2.3 From a7d34a7cb5c0a36139b55e35e75607599d0c2b97 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Tue, 3 Dec 2019 16:56:15 +0100 Subject: update test --- tests/arch/gowin/adffs.ys | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/arch/gowin/adffs.ys b/tests/arch/gowin/adffs.ys index fc7ee01f2..87fba83a6 100644 --- a/tests/arch/gowin/adffs.ys +++ b/tests/arch/gowin/adffs.ys @@ -34,11 +34,12 @@ proc equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffs # Constrain all select calls below inside the top module -select -assert-count 1 t:DFFS +select -assert-count 1 t:DFF +select -assert-count 1 t:LUT2 select -assert-count 4 t:IBUF select -assert-count 1 t:OBUF -select -assert-none t:DFFS t:IBUF t:OBUF %% t:* %D +select -assert-none t:DFF t:LUT2 t:IBUF t:OBUF %% t:* %D design -load read -- cgit v1.2.3 From 2abe38e73e51204976129c776447c2d40578c32f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Wed, 4 Dec 2019 08:44:08 +0100 Subject: iopadmap: Refactor and fix tristate buffer mapping. (#1527) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The previous code for rerouting wires when inserting tristate buffers was overcomplicated and didn't handle all cases correctly (in particular, only cell connections were rewired — internal connections were not). --- tests/techmap/iopadmap.ys | 99 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 tests/techmap/iopadmap.ys (limited to 'tests') diff --git a/tests/techmap/iopadmap.ys b/tests/techmap/iopadmap.ys new file mode 100644 index 000000000..f4345e906 --- /dev/null +++ b/tests/techmap/iopadmap.ys @@ -0,0 +1,99 @@ +read_verilog << EOT +module ibuf ((* iopad_external_pin *) input i, output o); endmodule +module obuf (input i, (* iopad_external_pin *) output o); endmodule +module obuft (input i, input oe, (* iopad_external_pin *) output o); endmodule +module iobuf (input i, input oe, output o, (* iopad_external_pin *) inout io); endmodule + +module a(input i, output o); +assign o = i; +endmodule + +module b(input i, output o); +assign o = i; +ibuf b (.i(i), .o(o)); +endmodule + +module c(input i, output o); +obuf b (.i(i), .o(o)); +endmodule + +module d(input i, oe, output o, o2, o3); +assign o = oe ? i : 1'bz; +assign o2 = o; +assign o3 = ~o; +endmodule + +module e(input i, oe, inout io, output o2, o3); +assign io = oe ? i : 1'bz; +assign o2 = io; +assign o3 = ~io; +endmodule +EOT + +opt_clean +tribuf +simplemap +iopadmap -bits -inpad ibuf o:i -outpad obuf i:o -toutpad obuft oe:i:o -tinoutpad iobuf oe:o:i:io +opt_clean + +select -assert-count 1 a/t:ibuf +select -assert-count 1 a/t:obuf +select -set ib w:i %a %co a/t:ibuf %i +select -set ob w:o %a %ci a/t:obuf %i +select -assert-count 1 @ib +select -assert-count 1 @ob +select -assert-count 1 @ib %co %co @ob %i + +select -assert-count 1 b/t:ibuf +select -assert-count 1 b/t:obuf +select -set ib w:i %a %co b/t:ibuf %i +select -set ob w:o %a %ci b/t:obuf %i +select -assert-count 1 @ib +select -assert-count 1 @ob +select -assert-count 1 @ib %co %co @ob %i + +select -assert-count 1 c/t:ibuf +select -assert-count 1 c/t:obuf +select -set ib w:i %a %co c/t:ibuf %i +select -set ob w:o %a %ci c/t:obuf %i +select -assert-count 1 @ib +select -assert-count 1 @ob +select -assert-count 1 @ib %co %co @ob %i + +select -assert-count 2 d/t:ibuf +select -assert-count 2 d/t:obuf +select -assert-count 1 d/t:obuft +select -set ib w:i %a %co d/t:ibuf %i +select -set oeb w:oe %a %co d/t:ibuf %i +select -set ob w:o %a %ci d/t:obuft %i +select -set o2b w:o2 %a %ci d/t:obuf %i +select -set o3b w:o3 %a %ci d/t:obuf %i +select -assert-count 1 @ib +select -assert-count 1 @oeb +select -assert-count 1 @ob +select -assert-count 1 @o2b +select -assert-count 1 @o3b +select -assert-count 1 @ib %co %co @ob %i +select -assert-count 1 @oeb %co %co @ob %i +select -assert-count 1 @ib %co %co @o2b %i +select -assert-count 1 @ib %co %co t:$_NOT_ %i +select -assert-count 1 @o3b %ci %ci t:$_NOT_ %i + +select -assert-count 2 e/t:ibuf +select -assert-count 2 e/t:obuf +select -assert-count 1 e/t:iobuf +select -set ib w:i %a %co e/t:ibuf %i +select -set oeb w:oe %a %co e/t:ibuf %i +select -set iob w:io %a %ci e/t:iobuf %i +select -set o2b w:o2 %a %ci e/t:obuf %i +select -set o3b w:o3 %a %ci e/t:obuf %i +select -assert-count 1 @ib +select -assert-count 1 @oeb +select -assert-count 1 @iob +select -assert-count 1 @o2b +select -assert-count 1 @o3b +select -assert-count 1 @ib %co %co @iob %i +select -assert-count 1 @oeb %co %co @iob %i +select -assert-count 1 @iob %co %co @o2b %i +select -assert-count 1 @iob %co %co t:$_NOT_ %i +select -assert-count 1 @o3b %ci %ci t:$_NOT_ %i -- cgit v1.2.3 From dcb30b5f4a49379a41fe4e279526b93da31eeabd Mon Sep 17 00:00:00 2001 From: Jan Kowalewski Date: Fri, 6 Dec 2019 09:01:16 +0100 Subject: tests: arch: xilinx: Change order of arguments in macc.sh --- tests/arch/xilinx/macc.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/arch/xilinx/macc.sh b/tests/arch/xilinx/macc.sh index 2272679ee..154a29848 100644 --- a/tests/arch/xilinx/macc.sh +++ b/tests/arch/xilinx/macc.sh @@ -1,3 +1,3 @@ -../../../yosys -qp "synth_xilinx -top macc2; rename -top macc2_uut" macc.v -o macc_uut.v +../../../yosys -qp "synth_xilinx -top macc2; rename -top macc2_uut" -o macc_uut.v macc.v iverilog -o test_macc macc_tb.v macc_uut.v macc.v ../../../techlibs/xilinx/cells_sim.v vvp -N ./test_macc -- cgit v1.2.3