From a12801843bb400bba8f2f8ce99a3f524ac05b7e8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 14:17:59 -0700 Subject: Add comment for lack of tristate logic pointing to #1225 --- tests/xilinx/tribuf.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/xilinx/tribuf.ys b/tests/xilinx/tribuf.ys index 76b00647d..696be2620 100644 --- a/tests/xilinx/tribuf.ys +++ b/tests/xilinx/tribuf.ys @@ -7,6 +7,6 @@ synth equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -#Xilinx Vivado synthesizes OBUFT cell for this case. Need support it. +# TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225 select -assert-count 1 t:$_TBUF_ select -assert-none t:$_TBUF_ %% t:* %D -- cgit v1.2.3