From 9a101dc1f78acb404cc98e0acc4530c238070fd8 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 8 Jul 2016 14:31:06 +0200
Subject: Fixed mem assignment in left-hand-side concatenation

---
 tests/simple/memory.v | 13 +++++++++++++
 1 file changed, 13 insertions(+)

(limited to 'tests')

diff --git a/tests/simple/memory.v b/tests/simple/memory.v
index 9fddce26c..61b36e79a 100644
--- a/tests/simple/memory.v
+++ b/tests/simple/memory.v
@@ -264,3 +264,16 @@ module memtest11(clk, wen, waddr, raddr, wdata, rdata);
 	end
 endmodule
 
+// ----------------------------------------------------------
+
+module memtest12 (
+   input clk,
+   input [1:0] adr,
+   input [1:0] din,
+   output reg [1:0] q
+);
+   reg [1:0] ram [3:0];
+   always@(posedge clk)
+     {ram[adr], q} <= {din, ram[adr]};
+endmodule
+
-- 
cgit v1.2.3