From 8c813632b6c1557f5123ea0cece2738fad40b89b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 27 Nov 2019 00:48:22 -0800
Subject: Revert "submod to bitty rather bussy, for bussy wires used as input
 and output"

This reverts commit cba3073026711e7683c46ba091c56a5c5a041a45.
---
 tests/various/submod.ys | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/various/submod.ys b/tests/various/submod.ys
index a0a3f2da5..552fd4e01 100644
--- a/tests/various/submod.ys
+++ b/tests/various/submod.ys
@@ -52,8 +52,10 @@ sat -verify -prove-asserts -show-ports miter
 
 design -reset
 read_verilog -icells <<EOT
-module top(input d, c, (* init = 1'b1 *) output reg q);
-(* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q));
+module top(input d, c, (* init = 3'b011 *) output reg [2:0] q);
+(* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q[1]));
+DFF s2(.D(d), .C(c), .Q(q[0]));
+DFF s3(.D(d), .C(c), .Q(q[2]));
 endmodule
 
 module DFF(input D, C, output Q);
@@ -62,6 +64,7 @@ endmodule
 EOT
 
 hierarchy -top top
+proc
 
 submod
 dffinit -ff DFF Q INIT
-- 
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