From 7df0e77565ea9dc46d0eeca536d1be47851326e5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 30 Aug 2019 14:35:05 -0700 Subject: Add mul_unsigned test --- tests/xilinx/mul_unsigned.v | 30 ++++++++++++++++++++++++++++++ tests/xilinx/mul_unsigned.ys | 11 +++++++++++ 2 files changed, 41 insertions(+) create mode 100644 tests/xilinx/mul_unsigned.v create mode 100644 tests/xilinx/mul_unsigned.ys (limited to 'tests') diff --git a/tests/xilinx/mul_unsigned.v b/tests/xilinx/mul_unsigned.v new file mode 100644 index 000000000..e3713a642 --- /dev/null +++ b/tests/xilinx/mul_unsigned.v @@ -0,0 +1,30 @@ +/* +Example from: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug901-vivado-synthesis.pdf [p. 89]. +*/ + +// Unsigned 16x24-bit Multiplier +// 1 latency stage on operands +// 3 latency stage after the multiplication +// File: multipliers2.v +// +module mul_unsigned (clk, A, B, RES); +parameter WIDTHA = /*16*/ 6; +parameter WIDTHB = /*24*/ 9; +input clk; +input [WIDTHA-1:0] A; +input [WIDTHB-1:0] B; +output [WIDTHA+WIDTHB-1:0] RES; +reg [WIDTHA-1:0] rA; +reg [WIDTHB-1:0] rB; +reg [WIDTHA+WIDTHB-1:0] M [3:0]; +integer i; +always @(posedge clk) + begin + rA <= A; + rB <= B; + M[0] <= rA * rB; + for (i = 0; i < 3; i = i+1) + M[i+1] <= M[i]; + end +assign RES = M[3]; +endmodule diff --git a/tests/xilinx/mul_unsigned.ys b/tests/xilinx/mul_unsigned.ys new file mode 100644 index 000000000..72d1f37d7 --- /dev/null +++ b/tests/xilinx/mul_unsigned.ys @@ -0,0 +1,11 @@ +read_verilog mul_unsigned.v +proc +hierarchy -top mul_unsigned +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mul_unsigned # Constrain all select calls below inside the top module +stat +select -assert-count 1 t:BUFG +select -assert-count 1 t:DSP48E1 +select -assert-count 15 t:SRL16E +select -assert-none t:DSP48E1 t:SRL16E t:BUFG %% t:* %D -- cgit v1.2.3 From d508dc2906f27b088e9c1c40e7cf2f475e80c15b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 30 Aug 2019 15:01:08 -0700 Subject: Update test for ffM --- tests/xilinx/mul_unsigned.ys | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/xilinx/mul_unsigned.ys b/tests/xilinx/mul_unsigned.ys index 72d1f37d7..30c034afe 100644 --- a/tests/xilinx/mul_unsigned.ys +++ b/tests/xilinx/mul_unsigned.ys @@ -7,5 +7,5 @@ cd mul_unsigned # Constrain all select calls below inside the top module stat select -assert-count 1 t:BUFG select -assert-count 1 t:DSP48E1 -select -assert-count 15 t:SRL16E -select -assert-none t:DSP48E1 t:SRL16E t:BUFG %% t:* %D +select -assert-count 30 t:FDRE +select -assert-none t:DSP48E1 t:FDRE t:BUFG %% t:* %D -- cgit v1.2.3 From 9be9631e5acaa570804e1772caae55f5cfc7a918 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 30 Aug 2019 16:18:14 -0700 Subject: Add macc test, with equiv_opt not currently passing --- tests/xilinx/macc.v | 37 +++++++++++++++++++++++++++++++++++++ tests/xilinx/macc.ys | 17 +++++++++++++++++ 2 files changed, 54 insertions(+) create mode 100644 tests/xilinx/macc.v create mode 100644 tests/xilinx/macc.ys (limited to 'tests') diff --git a/tests/xilinx/macc.v b/tests/xilinx/macc.v new file mode 100644 index 000000000..bae63b5a4 --- /dev/null +++ b/tests/xilinx/macc.v @@ -0,0 +1,37 @@ +// Signed 40-bit streaming accumulator with 16-bit inputs +// File: HDL_Coding_Techniques/multipliers/multipliers4.v +// +module macc # (parameter SIZEIN = /*16*/7, SIZEOUT = 40) + (input clk, ce, sload, + input signed [SIZEIN-1:0] a, b, + output signed [SIZEOUT-1:0] accum_out); + // Declare registers for intermediate values + reg signed [SIZEIN-1:0] a_reg, b_reg; + reg sload_reg; + reg signed [2*SIZEIN:0] mult_reg; + reg signed [SIZEOUT-1:0] adder_out, old_result; + always @(adder_out or sload_reg) begin + //if (sload_reg) + //old_result <= 0; + //else + // 'sload' is now active (=low) and opens the accumulation loop. + // The accumulator takes the next multiplier output in + // the same cycle. + old_result <= adder_out; + a_reg <= a; + b_reg <= b; + end + + always @(posedge clk) + //if (ce) + begin + mult_reg <= a_reg * b_reg; + sload_reg <= sload; + // Store accumulation result into a register + adder_out <= old_result + mult_reg; + end + + // Output accumulation result + assign accum_out = adder_out; + +endmodule // macc diff --git a/tests/xilinx/macc.ys b/tests/xilinx/macc.ys new file mode 100644 index 000000000..62b69f4d2 --- /dev/null +++ b/tests/xilinx/macc.ys @@ -0,0 +1,17 @@ +read_verilog macc.v +proc +hierarchy -top macc +equiv_opt -run :restore -map +/xilinx/cells_sim.v synth_xilinx # equivalency check + +#equiv_miter -trigger miter equiv +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +#equiv_opt -assert -run :prove -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +#miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -set-init-zero -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter + +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd macc # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 1 t:DSP48E1 +select -assert-none t:BUFG t:DSP48E1 %% t:* %D -- cgit v1.2.3 From e68507a71603553426a338bcffb0eccb1653436f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 6 Sep 2019 23:19:03 -0700 Subject: Update macc test --- tests/xilinx/macc.v | 66 ++++++++++++++++++++++++++++------------------------ tests/xilinx/macc.ys | 18 ++++++-------- 2 files changed, 42 insertions(+), 42 deletions(-) (limited to 'tests') diff --git a/tests/xilinx/macc.v b/tests/xilinx/macc.v index bae63b5a4..0bb673316 100644 --- a/tests/xilinx/macc.v +++ b/tests/xilinx/macc.v @@ -1,37 +1,41 @@ // Signed 40-bit streaming accumulator with 16-bit inputs // File: HDL_Coding_Techniques/multipliers/multipliers4.v // -module macc # (parameter SIZEIN = /*16*/7, SIZEOUT = 40) - (input clk, ce, sload, - input signed [SIZEIN-1:0] a, b, - output signed [SIZEOUT-1:0] accum_out); - // Declare registers for intermediate values - reg signed [SIZEIN-1:0] a_reg, b_reg; - reg sload_reg; - reg signed [2*SIZEIN:0] mult_reg; - reg signed [SIZEOUT-1:0] adder_out, old_result; - always @(adder_out or sload_reg) begin - //if (sload_reg) - //old_result <= 0; - //else - // 'sload' is now active (=low) and opens the accumulation loop. - // The accumulator takes the next multiplier output in - // the same cycle. - old_result <= adder_out; - a_reg <= a; - b_reg <= b; - end +// Source: +// https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug901-vivado-synthesis.pdf p.90 +// +module macc # (parameter SIZEIN = 16, SIZEOUT = 40) ( + input clk, ce, sload, + input signed [SIZEIN-1:0] a, b, + output signed [SIZEOUT-1:0] accum_out +); +// Declare registers for intermediate values +reg signed [SIZEIN-1:0] a_reg, b_reg; +reg sload_reg; +reg signed [2*SIZEIN-1:0] mult_reg; +reg signed [SIZEOUT-1:0] adder_out, old_result; +always @* /*(adder_out or sload_reg)*/ begin // Modification necessary to fix sim/synth mismatch + if (sload_reg) + old_result <= 0; + else + // 'sload' is now active (=low) and opens the accumulation loop. + // The accumulator takes the next multiplier output in + // the same cycle. + old_result <= adder_out; +end - always @(posedge clk) - //if (ce) - begin - mult_reg <= a_reg * b_reg; - sload_reg <= sload; - // Store accumulation result into a register - adder_out <= old_result + mult_reg; - end +always @(posedge clk) + if (ce) + begin + a_reg <= a; + b_reg <= b; + mult_reg <= a_reg * b_reg; + sload_reg <= sload; + // Store accumulation result into a register + adder_out <= old_result + mult_reg; + end - // Output accumulation result - assign accum_out = adder_out; + // Output accumulation result + assign accum_out = adder_out; -endmodule // macc +endmodule diff --git a/tests/xilinx/macc.ys b/tests/xilinx/macc.ys index 62b69f4d2..de408162c 100644 --- a/tests/xilinx/macc.ys +++ b/tests/xilinx/macc.ys @@ -1,17 +1,13 @@ read_verilog macc.v proc -hierarchy -top macc -equiv_opt -run :restore -map +/xilinx/cells_sim.v synth_xilinx # equivalency check - -#equiv_miter -trigger miter equiv -#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter - -#equiv_opt -assert -run :prove -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -#miter -equiv -flatten -make_assert -make_outputs gold gate miter -#sat -set-init-zero -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter - +hierarchy -auto-top +#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd macc # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG +select -assert-count 1 t:FDRE select -assert-count 1 t:DSP48E1 -select -assert-none t:BUFG t:DSP48E1 %% t:* %D +select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D -- cgit v1.2.3 From 1fc50a03fcaeebc0d1b12f397c2d31bcd27df715 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 9 Sep 2019 21:40:06 -0700 Subject: Add SIMD test --- tests/xilinx/dsp_simd.ys | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 tests/xilinx/dsp_simd.ys (limited to 'tests') diff --git a/tests/xilinx/dsp_simd.ys b/tests/xilinx/dsp_simd.ys new file mode 100644 index 000000000..956952327 --- /dev/null +++ b/tests/xilinx/dsp_simd.ys @@ -0,0 +1,25 @@ +read_verilog < Date: Wed, 11 Sep 2019 09:09:08 -0700 Subject: Extend test for RSTP and RSTM --- tests/xilinx/macc.v | 36 ++++++++++++++++++++++++++++++++++-- tests/xilinx/macc.ys | 17 ++++++++++++++++- 2 files changed, 50 insertions(+), 3 deletions(-) (limited to 'tests') diff --git a/tests/xilinx/macc.v b/tests/xilinx/macc.v index 0bb673316..c6ad2a578 100644 --- a/tests/xilinx/macc.v +++ b/tests/xilinx/macc.v @@ -35,7 +35,39 @@ always @(posedge clk) adder_out <= old_result + mult_reg; end - // Output accumulation result - assign accum_out = adder_out; +// Output accumulation result +assign accum_out = adder_out; + +endmodule + +// Adapted variant of above +module macc2 # (parameter SIZEIN = 16, SIZEOUT = 40) ( + input clk, ce, rst, + input signed [SIZEIN-1:0] a, b, + output signed [SIZEOUT-1:0] accum_out +); +// Declare registers for intermediate values +reg signed [SIZEIN-1:0] a_reg, b_reg; +reg rst_reg; +reg signed [2*SIZEIN-1:0] mult_reg; +reg signed [SIZEOUT-1:0] adder_out, old_result; +always @(posedge clk) begin + if (ce) + begin + a_reg <= a; + b_reg <= b; + mult_reg <= a_reg * b_reg; + rst_reg <= rst; + // Store accumulation result into a register + adder_out <= adder_out + mult_reg; + end + if (rst) begin + mult_reg <= 0; + adder_out <= 0; + end +end + +// Output accumulation result +assign accum_out = adder_out; endmodule diff --git a/tests/xilinx/macc.ys b/tests/xilinx/macc.ys index de408162c..294b83c69 100644 --- a/tests/xilinx/macc.ys +++ b/tests/xilinx/macc.ys @@ -1,6 +1,8 @@ read_verilog macc.v +design -save read + proc -hierarchy -auto-top +hierarchy -top macc #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx miter -equiv -flatten -make_assert -make_outputs gold gate miter @@ -11,3 +13,16 @@ select -assert-count 1 t:BUFG select -assert-count 1 t:FDRE select -assert-count 1 t:DSP48E1 select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D + +design -load read +proc +hierarchy -top macc2 +#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd macc2 # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 1 t:DSP48E1 +select -assert-none t:BUFG t:DSP48E1 %% t:* %D -- cgit v1.2.3 From 6a95ecd41d31a841537357a1ffaabf4ea5c7ed93 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 11 Sep 2019 10:13:13 -0700 Subject: Update test with a/b reset --- tests/xilinx/macc.v | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/xilinx/macc.v b/tests/xilinx/macc.v index c6ad2a578..5dc99ab8e 100644 --- a/tests/xilinx/macc.v +++ b/tests/xilinx/macc.v @@ -61,10 +61,12 @@ always @(posedge clk) begin // Store accumulation result into a register adder_out <= adder_out + mult_reg; end - if (rst) begin + if (rst) begin + a_reg <= 0; + b_reg <= 0; mult_reg <= 0; adder_out <= 0; - end + end end // Output accumulation result -- cgit v1.2.3 From 7d644f40ed42f3f0c5e5218c5f0274a7bcdfca85 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 11 Sep 2019 17:05:47 -0700 Subject: Add AREG=2 BREG=2 test --- tests/xilinx/macc.v | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/xilinx/macc.v b/tests/xilinx/macc.v index 5dc99ab8e..9d684477f 100644 --- a/tests/xilinx/macc.v +++ b/tests/xilinx/macc.v @@ -47,7 +47,7 @@ module macc2 # (parameter SIZEIN = 16, SIZEOUT = 40) ( output signed [SIZEOUT-1:0] accum_out ); // Declare registers for intermediate values -reg signed [SIZEIN-1:0] a_reg, b_reg; +reg signed [SIZEIN-1:0] a_reg, b_reg, a_reg2, b_reg2; reg rst_reg; reg signed [2*SIZEIN-1:0] mult_reg; reg signed [SIZEOUT-1:0] adder_out, old_result; @@ -56,14 +56,18 @@ always @(posedge clk) begin begin a_reg <= a; b_reg <= b; - mult_reg <= a_reg * b_reg; + a_reg2 <= a_reg; + b_reg2 <= b_reg; + mult_reg <= a_reg2 * b_reg2; rst_reg <= rst; // Store accumulation result into a register adder_out <= adder_out + mult_reg; end if (rst) begin a_reg <= 0; + a_reg2 <= 0; b_reg <= 0; + b_reg2 <= 0; mult_reg <= 0; adder_out <= 0; end -- cgit v1.2.3 From c3cba7ab93bb21f5fa713fd037c77b890544a95c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 18 Sep 2019 12:07:25 -0700 Subject: Refine macc testcase --- tests/xilinx/macc.v | 21 +++++++++++++-------- tests/xilinx/macc.ys | 5 ++++- 2 files changed, 17 insertions(+), 9 deletions(-) (limited to 'tests') diff --git a/tests/xilinx/macc.v b/tests/xilinx/macc.v index 9d684477f..e36b2bab1 100644 --- a/tests/xilinx/macc.v +++ b/tests/xilinx/macc.v @@ -42,26 +42,29 @@ endmodule // Adapted variant of above module macc2 # (parameter SIZEIN = 16, SIZEOUT = 40) ( - input clk, ce, rst, + input clk, + input ce, + input rst, input signed [SIZEIN-1:0] a, b, - output signed [SIZEOUT-1:0] accum_out + output signed [SIZEOUT-1:0] accum_out, + output overflow ); // Declare registers for intermediate values reg signed [SIZEIN-1:0] a_reg, b_reg, a_reg2, b_reg2; -reg rst_reg; -reg signed [2*SIZEIN-1:0] mult_reg; -reg signed [SIZEOUT-1:0] adder_out, old_result; +reg signed [2*SIZEIN-1:0] mult_reg = 0; +reg signed [SIZEOUT:0] adder_out = 0; +reg overflow_reg; always @(posedge clk) begin - if (ce) + //if (ce) begin a_reg <= a; b_reg <= b; a_reg2 <= a_reg; b_reg2 <= b_reg; mult_reg <= a_reg2 * b_reg2; - rst_reg <= rst; // Store accumulation result into a register adder_out <= adder_out + mult_reg; + overflow_reg <= overflow; end if (rst) begin a_reg <= 0; @@ -70,10 +73,12 @@ always @(posedge clk) begin b_reg2 <= 0; mult_reg <= 0; adder_out <= 0; + overflow_reg <= 1'b0; end end +assign overflow = (adder_out >= 2**(SIZEOUT-1)) | overflow_reg; // Output accumulation result -assign accum_out = adder_out; +assign accum_out = overflow ? 2**(SIZEOUT-1)-1 : adder_out; endmodule diff --git a/tests/xilinx/macc.ys b/tests/xilinx/macc.ys index 294b83c69..417a3b21b 100644 --- a/tests/xilinx/macc.ys +++ b/tests/xilinx/macc.ys @@ -25,4 +25,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd macc2 # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:DSP48E1 -select -assert-none t:BUFG t:DSP48E1 %% t:* %D +select -assert-count 1 t:FDRE +select -assert-count 1 t:LUT2 +select -assert-count 41 t:LUT3 +select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:LUT3 %% t:* %D -- cgit v1.2.3 From c9fe4d7992078ca0dec2cb7bcc6c58813e73189d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 18 Sep 2019 12:11:33 -0700 Subject: Add .gitignore --- tests/xilinx/.gitignore | 1 + 1 file changed, 1 insertion(+) (limited to 'tests') diff --git a/tests/xilinx/.gitignore b/tests/xilinx/.gitignore index b48f808a1..54733fb71 100644 --- a/tests/xilinx/.gitignore +++ b/tests/xilinx/.gitignore @@ -1,3 +1,4 @@ /*.log /*.out /run-test.mk +/*_uut.v -- cgit v1.2.3 From c663a3680b13422c568e3dc438e7b971b81a71c3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 18 Sep 2019 12:44:34 -0700 Subject: Remove stat --- tests/xilinx/mul_unsigned.ys | 1 - 1 file changed, 1 deletion(-) (limited to 'tests') diff --git a/tests/xilinx/mul_unsigned.ys b/tests/xilinx/mul_unsigned.ys index 30c034afe..77990bd68 100644 --- a/tests/xilinx/mul_unsigned.ys +++ b/tests/xilinx/mul_unsigned.ys @@ -4,7 +4,6 @@ hierarchy -top mul_unsigned equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mul_unsigned # Constrain all select calls below inside the top module -stat select -assert-count 1 t:BUFG select -assert-count 1 t:DSP48E1 select -assert-count 30 t:FDRE -- cgit v1.2.3 From 65fa8adf6c834cc3c73300a19d4fe96c31b8d361 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 19 Sep 2019 11:02:14 -0700 Subject: Format macc.v --- tests/ice40/macc.v | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'tests') diff --git a/tests/ice40/macc.v b/tests/ice40/macc.v index 6c3676c83..757c36a66 100644 --- a/tests/ice40/macc.v +++ b/tests/ice40/macc.v @@ -13,13 +13,13 @@ reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c; assign c = reg_tmp_c; always @(posedge clk) begin -if(set) -begin -reg_tmp_c <= 0; -end -else -begin -reg_tmp_c <= a * b + c; -end + if(set) + begin + reg_tmp_c <= 0; + end + else + begin + reg_tmp_c <= a * b + c; + end end endmodule -- cgit v1.2.3 From 2f98f9deee063de1e6a57437f1fe885d42916e19 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 19 Sep 2019 18:08:16 -0700 Subject: Add mac.sh and macc_tb.v for testing --- tests/xilinx/macc.sh | 3 ++ tests/xilinx/macc_tb.v | 96 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 99 insertions(+) create mode 100644 tests/xilinx/macc.sh create mode 100644 tests/xilinx/macc_tb.v (limited to 'tests') diff --git a/tests/xilinx/macc.sh b/tests/xilinx/macc.sh new file mode 100644 index 000000000..86e4c2bb6 --- /dev/null +++ b/tests/xilinx/macc.sh @@ -0,0 +1,3 @@ +../../yosys -qp "synth_xilinx -top macc2; rename -top macc2_uut" macc.v -o macc_uut.v +iverilog -o test_macc macc_tb.v macc_uut.v macc.v ../../techlibs/xilinx/cells_sim.v +vvp -N ./test_macc diff --git a/tests/xilinx/macc_tb.v b/tests/xilinx/macc_tb.v new file mode 100644 index 000000000..64aed05c4 --- /dev/null +++ b/tests/xilinx/macc_tb.v @@ -0,0 +1,96 @@ +`timescale 1ns / 1ps + +module testbench; + + parameter SIZEIN = 16, SIZEOUT = 40; + reg clk, ce, rst; + reg signed [SIZEIN-1:0] a, b; + output signed [SIZEOUT-1:0] REF_accum_out, accum_out; + output REF_overflow, overflow; + + integer errcount = 0; + + reg ERROR_FLAG = 0; + + task clkcycle; + begin + #5; + clk = ~clk; + #10; + clk = ~clk; + #2; + ERROR_FLAG = 0; + if (REF_accum_out !== accum_out) begin + $display("ERROR at %1t: REF_accum_out=%b UUT_accum_out=%b DIFF=%b", $time, REF_accum_out, accum_out, REF_accum_out ^ accum_out); + errcount = errcount + 1; + ERROR_FLAG = 1; + end + if (REF_overflow !== overflow) begin + $display("ERROR at %1t: REF_overflow=%b UUT_overflow=%b DIFF=%b", $time, REF_overflow, overflow, REF_overflow ^ overflow); + errcount = errcount + 1; + ERROR_FLAG = 1; + end + #3; + end + endtask + + initial begin + //$dumpfile("test_macc.vcd"); + //$dumpvars(0, testbench); + + #2; + clk = 1'b0; + ce = 1'b0; + a = 0; + b = 0; + + rst = 1'b1; + repeat (10) begin + #10; + clk = 1'b1; + #10; + clk = 1'b0; + #10; + clk = 1'b1; + #10; + clk = 1'b0; + end + rst = 1'b0; + + repeat (10000) begin + clkcycle; + ce = 1; //$urandom & $urandom; + //rst = $urandom & $urandom & $urandom & $urandom & $urandom & $urandom; + a = $urandom & ~(1 << (SIZEIN-1)); + b = $urandom & ~(1 << (SIZEIN-1)); + end + + if (errcount == 0) begin + $display("All tests passed."); + $finish; + end else begin + $display("Caught %1d errors.", errcount); + $stop; + end + end + + macc2 ref ( + .clk(clk), + .ce(ce), + .rst(rst), + .a(a), + .b(b), + .accum_out(REF_accum_out), + .overflow(REF_overflow) + ); + + macc2_uut uut ( + .clk(clk), + .ce(ce), + .rst(rst), + .a(a), + .b(b), + .accum_out(accum_out), + .overflow(overflow) + ); +endmodule -- cgit v1.2.3 From 4100825b810408e25b1773cb1e57d25821f164b5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 19 Sep 2019 22:39:15 -0700 Subject: Add more complicated macc testcase --- tests/ice40/macc.v | 22 ++++++++++++++++++++++ tests/ice40/macc.ys | 22 +++++++++++++++++----- 2 files changed, 39 insertions(+), 5 deletions(-) (limited to 'tests') diff --git a/tests/ice40/macc.v b/tests/ice40/macc.v index 757c36a66..6f68e7500 100644 --- a/tests/ice40/macc.v +++ b/tests/ice40/macc.v @@ -23,3 +23,25 @@ begin end end endmodule + +module top2(clk,a,b,c,hold); +parameter A_WIDTH = 6 /*4*/; +parameter B_WIDTH = 6 /*3*/; +input hold; +input clk; +input signed [(A_WIDTH - 1):0] a; +input signed [(B_WIDTH - 1):0] b; +output signed [(A_WIDTH + B_WIDTH - 1):0] c; +reg signed [A_WIDTH-1:0] reg_a; +reg signed [B_WIDTH-1:0] reg_b; +reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c; +assign c = reg_tmp_c; +always @(posedge clk) +begin + if (!hold) begin + reg_a <= a; + reg_b <= b; + reg_tmp_c <= reg_a * reg_b + c; + end +end +endmodule diff --git a/tests/ice40/macc.ys b/tests/ice40/macc.ys index 0f4c19be5..fd30e79c5 100644 --- a/tests/ice40/macc.ys +++ b/tests/ice40/macc.ys @@ -1,13 +1,25 @@ read_verilog macc.v proc +design -save read + hierarchy -top top -#equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check +equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_MAC16 +select -assert-none t:SB_MAC16 %% t:* %D + +design -load read +hierarchy -top top2 -equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 -dsp -async2sync -equiv_opt -run prove: -assert null +#equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check + +equiv_opt -run :prove -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check +clk2fflogic +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -set-init-zero -seq 4 -verify -prove-asserts -show-ports miter design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd top2 # Constrain all select calls below inside the top module select -assert-count 1 t:SB_MAC16 select -assert-none t:SB_MAC16 %% t:* %D -- cgit v1.2.3