From 8226f2db0b65dffb59c4420de96dccd2e0be36ed Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Thu, 24 Oct 2019 13:39:43 +0200 Subject: ALU sim tweaks --- tests/arch/gowin/mux.ys | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/arch/gowin/mux.ys b/tests/arch/gowin/mux.ys index c9c85019b..d612e4eaa 100644 --- a/tests/arch/gowin/mux.ys +++ b/tests/arch/gowin/mux.ys @@ -42,8 +42,8 @@ proc equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-count 9 t:LUT4 -select -assert-count 3 t:LUT3 +select -assert-count 10 t:LUT4 +select -assert-count 1 t:LUT3 select -assert-count 20 t:IBUF select -assert-count 1 t:OBUF -- cgit v1.2.3