From 7e741714df62338a2037d24721ef99ca8a0c6763 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 22 Nov 2019 09:21:35 +0000
Subject: hierarchy: Correct handling of wildcard port connections with default
 values

Signed-off-by: David Shah <dave@ds0.me>
---
 tests/various/sv_implicit_ports.sh | 11 +++++++++++
 1 file changed, 11 insertions(+)

(limited to 'tests')

diff --git a/tests/various/sv_implicit_ports.sh b/tests/various/sv_implicit_ports.sh
index 13d39cf8b..2faac2e85 100755
--- a/tests/various/sv_implicit_ports.sh
+++ b/tests/various/sv_implicit_ports.sh
@@ -54,3 +54,14 @@ module top(input [7:0] a, output [7:0] q);
 endmodule
 EOT
 ) 2>&1 | grep -F "ERROR: Width mismatch between wire (7 bits) and port (8 bits) for implicit port connection \`b' of cell top.add_i (add)." > /dev/null
+
+# Defaults
+../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
+module add(input [7:0] a = 8'd00, input [7:0] b = 8'd01, output [7:0] q);
+assign q = a + b;
+endmodule
+
+module top(input [7:0] a, output [7:0] q);
+	add add_i(.*);
+endmodule
+EOT
-- 
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