From 7cfdf4ffa7698fa40aae401c2b8b159a6e37011a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 12 Feb 2020 12:16:01 -0800 Subject: verilog: fix $specify3 check --- tests/various/specify.v | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'tests') diff --git a/tests/various/specify.v b/tests/various/specify.v index 5d44d78f7..e4dd132f1 100644 --- a/tests/various/specify.v +++ b/tests/various/specify.v @@ -37,3 +37,10 @@ specify (posedge clk *> (q +: d)) = (3,1); endspecify endmodule + +module test3(input clk, input [1:0] d, output [1:0] q); +specify + (posedge clk => (q +: d)) = (3,1); + (posedge clk *> (q +: d)) = (3,1); +endspecify +endmodule -- cgit v1.2.3 From b523ecf2f45f80488412781ba9a3455a71d64d62 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 13 Feb 2020 08:59:08 -0800 Subject: specify: system timing checks to accept min:typ:max triple --- tests/various/specify.v | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'tests') diff --git a/tests/various/specify.v b/tests/various/specify.v index e4dd132f1..5006e4c38 100644 --- a/tests/various/specify.v +++ b/tests/various/specify.v @@ -44,3 +44,10 @@ specify (posedge clk *> (q +: d)) = (3,1); endspecify endmodule + +module test4(input clk, d, output q); +specify + $setup(d, posedge clk, 1:2:3); + $setuphold(d, posedge clk, 1:2:3, 4:5:6); +endspecify +endmodule -- cgit v1.2.3 From 2e51dc1856aae456e15cafd484997bfbd102175e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 13 Feb 2020 13:06:13 -0800 Subject: verilog: ignore '&&&' when not in -specify mode --- tests/various/specify.v | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'tests') diff --git a/tests/various/specify.v b/tests/various/specify.v index 5006e4c38..aa8aca4bc 100644 --- a/tests/various/specify.v +++ b/tests/various/specify.v @@ -51,3 +51,9 @@ specify $setuphold(d, posedge clk, 1:2:3, 4:5:6); endspecify endmodule + +module test5(input clk, d, e, output q); +specify + $setup(d, posedge clk &&& e, 1:2:3); +endspecify +endmodule -- cgit v1.2.3 From 6b58c1820c7bbacb4730af40e10592823b0eb15c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 13 Feb 2020 13:27:15 -0800 Subject: verilog: improve specify support when not in -specify mode --- tests/various/specify.v | 2 -- tests/various/specify.ys | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) (limited to 'tests') diff --git a/tests/various/specify.v b/tests/various/specify.v index aa8aca4bc..5655ded21 100644 --- a/tests/various/specify.v +++ b/tests/various/specify.v @@ -7,11 +7,9 @@ module test ( if (EN) Q <= D; specify -`ifndef SKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS if (EN) (posedge CLK *> (Q : D)) = (1, 2:3:4); $setup(D, posedge CLK &&& EN, 5); $hold(posedge CLK, D &&& EN, 6); -`endif endspecify endmodule diff --git a/tests/various/specify.ys b/tests/various/specify.ys index 00597e1e2..a2b6038e4 100644 --- a/tests/various/specify.ys +++ b/tests/various/specify.ys @@ -55,4 +55,4 @@ equiv_induct -seq 5 equiv_status -assert design -reset -read_verilog -DSKIP_UNSUPPORTED_IGN_PARSER_CONSTRUCTS specify.v +read_verilog specify.v -- cgit v1.2.3 From d20c1dac73e344dda73ec2b526ffb764efc9fdd8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 13 Feb 2020 17:58:43 -0800 Subject: verilog: ignore ranges too without -specify --- tests/various/specify.v | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'tests') diff --git a/tests/various/specify.v b/tests/various/specify.v index 5655ded21..c160d2ec4 100644 --- a/tests/various/specify.v +++ b/tests/various/specify.v @@ -55,3 +55,10 @@ specify $setup(d, posedge clk &&& e, 1:2:3); endspecify endmodule + +module test6(input clk, d, e, output q); +specify + (d[0] *> q[0]) = (3,1); + (posedge clk[0] => (q[0] +: d[0])) = (3,1); +endspecify +endmodule -- cgit v1.2.3 From 1d401a7991f4c0f133b7355acc400132da1aa4a0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 19 Feb 2020 10:45:10 -0800 Subject: clean: ignore specify-s inside cells when determining whether to keep --- tests/various/specify.ys | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/various/specify.ys b/tests/various/specify.ys index a2b6038e4..9d55b8eb5 100644 --- a/tests/various/specify.ys +++ b/tests/various/specify.ys @@ -55,4 +55,23 @@ equiv_induct -seq 5 equiv_status -assert design -reset -read_verilog specify.v +read_verilog -specify < o) = 1; +endspecify +assign o = ~i; +endmodule + +module test7(input i, output o); + wire w; + test7_sub unused(i, w); + test7_sub used(i, o); +endmodule +EOT +hierarchy +cd test7 +clean +select -assert-count 1 c:used +select -assert-none c:* c:used %d -- cgit v1.2.3