From dd317c92808a73e61e771a123fc4377d3fb78af2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 25 Nov 2019 16:07:35 -0800
Subject: Add testcase where \init is copied

---
 tests/various/submod.ys | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

(limited to 'tests')

diff --git a/tests/various/submod.ys b/tests/various/submod.ys
index 7c6f555ac..f50556d76 100644
--- a/tests/various/submod.ys
+++ b/tests/various/submod.ys
@@ -48,3 +48,21 @@ design -import gate -as gate
 
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
+
+
+design -reset
+read_verilog -icells <<EOT
+module top(input d, c, (* init = 1'b1 *) output reg q);
+(* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q));
+endmodule
+
+module DFF(input D, C, output Q);
+parameter INIT = 1'b0;
+endmodule
+EOT
+
+hierarchy -top top
+
+submod
+dffinit -ff DFF Q INIT
+check -noinit -assert
-- 
cgit v1.2.3


From 6318e3ce6df2484c4cc17856608e2a6354cd643a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 26 Nov 2019 23:38:49 -0800
Subject: Fix wire width

---
 tests/various/submod.ys | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/various/submod.ys b/tests/various/submod.ys
index f50556d76..a0a3f2da5 100644
--- a/tests/various/submod.ys
+++ b/tests/various/submod.ys
@@ -1,8 +1,8 @@
 read_verilog <<EOT
-module top(input a, output [1:0] b);
+module top(input a, output b);
 wire c;
 (* submod="bar" *) sub s1(a, c);
-assign b[0] = c;
+assign b = c;
 endmodule
 
 module sub(input a, output c);
-- 
cgit v1.2.3


From 8c813632b6c1557f5123ea0cece2738fad40b89b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 27 Nov 2019 00:48:22 -0800
Subject: Revert "submod to bitty rather bussy, for bussy wires used as input
 and output"

This reverts commit cba3073026711e7683c46ba091c56a5c5a041a45.
---
 tests/various/submod.ys | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/various/submod.ys b/tests/various/submod.ys
index a0a3f2da5..552fd4e01 100644
--- a/tests/various/submod.ys
+++ b/tests/various/submod.ys
@@ -52,8 +52,10 @@ sat -verify -prove-asserts -show-ports miter
 
 design -reset
 read_verilog -icells <<EOT
-module top(input d, c, (* init = 1'b1 *) output reg q);
-(* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q));
+module top(input d, c, (* init = 3'b011 *) output reg [2:0] q);
+(* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q[1]));
+DFF s2(.D(d), .C(c), .Q(q[0]));
+DFF s3(.D(d), .C(c), .Q(q[2]));
 endmodule
 
 module DFF(input D, C, output Q);
@@ -62,6 +64,7 @@ endmodule
 EOT
 
 hierarchy -top top
+proc
 
 submod
 dffinit -ff DFF Q INIT
-- 
cgit v1.2.3