From 5c68da4150f8e5367138f2c7187f707b20cc19db Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 5 Oct 2019 09:27:12 -0700
Subject: Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf

---
 tests/ice40/wrapcarry.ys | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 tests/ice40/wrapcarry.ys

(limited to 'tests')

diff --git a/tests/ice40/wrapcarry.ys b/tests/ice40/wrapcarry.ys
new file mode 100644
index 000000000..10c029e68
--- /dev/null
+++ b/tests/ice40/wrapcarry.ys
@@ -0,0 +1,22 @@
+read_verilog <<EOT
+module top(input A, B, CI, output O, CO);
+	SB_CARRY carry (
+		.I0(A),
+		.I1(B),
+		.CI(CI),
+		.CO(CO)
+	);
+	SB_LUT4 #(
+		.LUT_INIT(16'b 0110_1001_1001_0110)
+	) adder (
+		.I0(1'b0),
+		.I1(A),
+		.I2(B),
+		.I3(1'b0),
+		.O(O)
+	);
+endmodule
+EOT
+
+ice40_wrapcarry
+select -assert-count 1 t:$__ICE40_CARRY_WRAPPER
-- 
cgit v1.2.3