From 4bfaaea0d52c235bb51c4dc54b07fe301eebe473 Mon Sep 17 00:00:00 2001
From: Jannis Harder <me@jix.one>
Date: Fri, 20 May 2022 21:46:39 +0200
Subject: verilog: fix size and signedness of array querying functions

genrtlil.cc and simplify.cc had inconsistent and slightly broken
handling of signedness for array querying functions. These functions are
defined to return a signed result. Simplify always produced an unsigned
and genrtlil always a signed 32-bit result ignoring the context.

Includes tests for the the relvant edge cases for context dependent
conversions.
---
 tests/verilog/sign_array_query.ys | 52 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)
 create mode 100644 tests/verilog/sign_array_query.ys

(limited to 'tests')

diff --git a/tests/verilog/sign_array_query.ys b/tests/verilog/sign_array_query.ys
new file mode 100644
index 000000000..f955450b7
--- /dev/null
+++ b/tests/verilog/sign_array_query.ys
@@ -0,0 +1,52 @@
+logger -expect-no-warnings
+
+read_verilog -formal <<EOT
+module top(input clk);
+    reg [-1:-1] x;
+    reg good = 0;
+    reg signed [31:0] zero = 0;
+
+    always @(posedge clk) begin
+        case ($left(x) + zero) 36'shfffffffff: good = 1; endcase
+        assert (good);
+    end
+endmodule
+EOT
+
+prep -top top
+sim -n 3 -clock clk
+
+design -reset
+
+read_verilog -formal <<EOT
+module top(input clk);
+    reg [-1:-1] x;
+    reg good = 0;
+
+    always @(posedge clk) begin
+        case ($left(x)) 36'sh0ffffffff: good = 1; (32'h0 + $left(good)): ; endcase
+        assert (good);
+    end
+
+endmodule
+EOT
+
+prep -top top
+sim -n 3 -clock clk
+
+design -reset
+
+read_verilog -formal <<EOT
+module top(input clk);
+    reg [-1:-1] x;
+    reg good = 1;
+
+    always @(posedge clk) begin
+        case (36'sh100000000 + $left(x)) -1: good = 0; endcase
+        assert (good);
+    end
+endmodule
+EOT
+
+prep -top top
+sim -n 3 -clock clk
-- 
cgit v1.2.3