From 81ca776ea44e126b3946fcdd076c2d2e4d2ab34d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 19 Mar 2020 16:59:11 -0700
Subject: opt_expr: add $xor/$xnor/$_XOR_/$_XNOR_ tests

---
 tests/opt/opt_expr_xor.ys | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)
 create mode 100644 tests/opt/opt_expr_xor.ys

(limited to 'tests')

diff --git a/tests/opt/opt_expr_xor.ys b/tests/opt/opt_expr_xor.ys
new file mode 100644
index 000000000..a458c9a27
--- /dev/null
+++ b/tests/opt/opt_expr_xor.ys
@@ -0,0 +1,40 @@
+read_verilog <<EOT
+module top(input a, output [3:0] y);
+assign y[0] = a^1'b0;
+assign y[1] = 1'b1^a;
+assign y[2] = a~^1'b0;
+assign y[3] = 1'b1^~a;
+endmodule
+EOT
+design -save read
+select -assert-count 2 t:$xor
+select -assert-count 2 t:$xnor
+
+equiv_opt opt_expr
+design -load postopt
+select -assert-none t:$xor
+select -assert-none t:$xnor
+select -assert-count 2 t:$_NOT_
+
+
+design -load read
+simplemap
+equiv_opt opt_expr
+design -load postopt
+select -assert-none t:$_XOR_
+select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_
+select -assert-count 3 t:$_NOT_
+
+
+design -reset
+read_verilog -icells <<EOT
+module top(input a, output [1:0] y);
+$_XNOR_ u0(.A(a), .B(1'b0), .Y(y[0]));
+$_XNOR_ u1(.A(1'b1), .B(a), .Y(y[1]));
+endmodule
+EOT
+select -assert-count 2 t:$_XNOR_
+equiv_opt opt_expr
+design -load postopt
+select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_
+select -assert-count 1 t:$_NOT_
-- 
cgit v1.2.3


From 317c18fc6fe22f6b5ad4f0ac82f6abbcfaec2bca Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 20 Mar 2020 11:25:17 -0700
Subject: Simplify breaking tests/arch/*/fsm.ys tests

---
 tests/arch/anlogic/fsm.ys | 5 +----
 tests/arch/efinix/fsm.ys  | 5 ++---
 2 files changed, 3 insertions(+), 7 deletions(-)

(limited to 'tests')

diff --git a/tests/arch/anlogic/fsm.ys b/tests/arch/anlogic/fsm.ys
index 0bcc4e011..eb94177ad 100644
--- a/tests/arch/anlogic/fsm.ys
+++ b/tests/arch/anlogic/fsm.ys
@@ -10,9 +10,6 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd fsm # Constrain all select calls below inside the top module
 
-select -assert-count 1 t:AL_MAP_LUT2
-select -assert-count 5 t:AL_MAP_LUT5
-select -assert-count 1 t:AL_MAP_LUT6
 select -assert-count 6 t:AL_MAP_SEQ
 
-select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D
+select -assert-none t:AL_MAP_LUT* t:AL_MAP_SEQ %% t:* %D
diff --git a/tests/arch/efinix/fsm.ys b/tests/arch/efinix/fsm.ys
index a2db2ad98..aef720d46 100644
--- a/tests/arch/efinix/fsm.ys
+++ b/tests/arch/efinix/fsm.ys
@@ -10,7 +10,6 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd fsm # Constrain all select calls below inside the top module
 
-select -assert-count 1  t:EFX_GBUFCE
-select -assert-count 6  t:EFX_FF
-select -assert-count 15 t:EFX_LUT4
+select -assert-count 1 t:EFX_GBUFCE
+select -assert-count 6 t:EFX_FF
 select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D
-- 
cgit v1.2.3


From 6274f0b075abba2af9193e2245eacee5cc66e4c5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 20 Mar 2020 14:38:50 -0700
Subject: opt_expr: add failing $xnor test

---
 tests/opt/opt_expr_xor.ys | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/opt/opt_expr_xor.ys b/tests/opt/opt_expr_xor.ys
index a458c9a27..21439fd53 100644
--- a/tests/opt/opt_expr_xor.ys
+++ b/tests/opt/opt_expr_xor.ys
@@ -14,7 +14,7 @@ equiv_opt opt_expr
 design -load postopt
 select -assert-none t:$xor
 select -assert-none t:$xnor
-select -assert-count 2 t:$_NOT_
+select -assert-count 2 t:$not
 
 
 design -load read
@@ -38,3 +38,15 @@ equiv_opt opt_expr
 design -load postopt
 select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_
 select -assert-count 1 t:$_NOT_
+
+
+design -reset
+read_verilog <<EOT
+module top(input a, output [1:0] w, x, y, z);
+assign w = a^1'b0;
+assign x = a^1'b1;
+assign y = a~^1'b0;
+assign z = a~^1'b1;
+endmodule
+EOT
+equiv_opt opt_expr
-- 
cgit v1.2.3