From d9c16644626d49b5bb5eb463f2a113e13ad22d69 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 9 Aug 2019 10:08:17 -0700
Subject: Simplify opt_expr tests using equiv_opt

---
 tests/opt/opt_expr.ys | 95 +++++++++++++--------------------------------------
 1 file changed, 23 insertions(+), 72 deletions(-)

(limited to 'tests')

diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys
index 0c61ac881..9f3c0a1cd 100644
--- a/tests/opt/opt_expr.ys
+++ b/tests/opt/opt_expr.ys
@@ -6,24 +6,16 @@ endmodule
 EOT
 
 hierarchy -auto-top
-proc
-design -save gold
 
-opt_expr -fine
-wreduce
+equiv_opt -assert opt_expr -fine
+design -load postopt
 
+wreduce
 select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
 
-design -stash gate
-
-design -import gold -as gold
-design -import gate -as gate
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-
 ##########
 
+design -reset
 read_verilog <<EOT
 module opt_expr_add_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
     assign o = (i << 4) + j;
@@ -31,24 +23,16 @@ endmodule
 EOT
 
 hierarchy -auto-top
-proc
-design -save gold
 
-opt_expr -fine
-wreduce
+equiv_opt -assert opt_expr -fine
+design -load postopt
 
+wreduce
 select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
 
-design -stash gate
-
-design -import gold -as gold
-design -import gate -as gate
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-
 ##########
 
+design -reset
 read_verilog <<EOT
 module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
     assign o = j - (i << 4);
@@ -56,24 +40,16 @@ endmodule
 EOT
 
 hierarchy -auto-top
-proc
-design -save gold
 
-opt_expr -fine
-wreduce
+equiv_opt -assert opt_expr -fine
+design -load postopt
 
+wreduce
 select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
 
-design -stash gate
-
-design -import gold -as gold
-design -import gate -as gate
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-
 ##########
 
+design -reset
 read_verilog <<EOT
 module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
     assign o = j - (i << 4);
@@ -81,24 +57,16 @@ endmodule
 EOT
 
 hierarchy -auto-top
-proc
-design -save gold
 
-opt_expr -fine
-wreduce
+equiv_opt -assert opt_expr -fine
+design -load postopt
 
+wreduce
 select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
 
-design -stash gate
-
-design -import gold -as gold
-design -import gate -as gate
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-
 ##########
 
+design -reset
 read_verilog <<EOT
 module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o);
     assign o = (i << 4) - j;
@@ -106,24 +74,16 @@ endmodule
 EOT
 
 hierarchy -auto-top
-proc
-design -save gold
 
-opt_expr -fine
-wreduce
+equiv_opt -assert opt_expr -fine
+design -load postopt
 
+wreduce
 select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
 
-design -stash gate
-
-design -import gold -as gold
-design -import gate -as gate
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-
 ##########
 
+design -reset
 read_verilog <<EOT
 module opt_expr_sub_test4(input [3:0] i, output [8:0] o);
     assign o = 5'b00010 - i;
@@ -131,18 +91,9 @@ endmodule
 EOT
 
 hierarchy -auto-top
-proc
-design -save gold
 
-opt_expr -fine
-wreduce
+equiv_opt -assert opt_expr -fine
+design -load postopt
 
+wreduce
 select -assert-count 1 t:$sub r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
-
-design -stash gate
-
-design -import gold -as gold
-design -import gate -as gate
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-- 
cgit v1.2.3


From 313c9ec8df2aa0cbc077eb6d725e28336e9fe9e4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 9 Aug 2019 10:13:49 -0700
Subject: Cleanup some more

---
 tests/opt/opt_expr.ys | 12 ------------
 1 file changed, 12 deletions(-)

(limited to 'tests')

diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys
index 9f3c0a1cd..28d57f530 100644
--- a/tests/opt/opt_expr.ys
+++ b/tests/opt/opt_expr.ys
@@ -5,8 +5,6 @@ module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
 endmodule
 EOT
 
-hierarchy -auto-top
-
 equiv_opt -assert opt_expr -fine
 design -load postopt
 
@@ -22,8 +20,6 @@ module opt_expr_add_signed_test(input signed [3:0] i, input signed [7:0] j, outp
 endmodule
 EOT
 
-hierarchy -auto-top
-
 equiv_opt -assert opt_expr -fine
 design -load postopt
 
@@ -39,8 +35,6 @@ module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
 endmodule
 EOT
 
-hierarchy -auto-top
-
 equiv_opt -assert opt_expr -fine
 design -load postopt
 
@@ -56,8 +50,6 @@ module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, out
 endmodule
 EOT
 
-hierarchy -auto-top
-
 equiv_opt -assert opt_expr -fine
 design -load postopt
 
@@ -73,8 +65,6 @@ module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o);
 endmodule
 EOT
 
-hierarchy -auto-top
-
 equiv_opt -assert opt_expr -fine
 design -load postopt
 
@@ -90,8 +80,6 @@ module opt_expr_sub_test4(input [3:0] i, output [8:0] o);
 endmodule
 EOT
 
-hierarchy -auto-top
-
 equiv_opt -assert opt_expr -fine
 design -load postopt
 
-- 
cgit v1.2.3


From 93001116011d46e50c0a24b0bd21c2f07746dc42 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 9 Aug 2019 10:22:06 -0700
Subject: Add new $alu test, remove wreduce

---
 tests/opt/opt_expr.ys | 32 +++++++++++++++++++++-----------
 1 file changed, 21 insertions(+), 11 deletions(-)

(limited to 'tests')

diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys
index 28d57f530..96ab2f31a 100644
--- a/tests/opt/opt_expr.ys
+++ b/tests/opt/opt_expr.ys
@@ -8,8 +8,22 @@ EOT
 equiv_opt -assert opt_expr -fine
 design -load postopt
 
-wreduce
-select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
+select -assert-count 1 t:$add r:A_WIDTH=5 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
+
+##########
+
+design -reset
+read_verilog <<EOT
+module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
+    assign o = (i << 4) + j;
+endmodule
+EOT
+
+alumacc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
 
 ##########
 
@@ -23,8 +37,7 @@ EOT
 equiv_opt -assert opt_expr -fine
 design -load postopt
 
-wreduce
-select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
+select -assert-count 1 t:$add r:A_WIDTH=5 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
 
 ##########
 
@@ -38,8 +51,7 @@ EOT
 equiv_opt -assert opt_expr -fine
 design -load postopt
 
-wreduce
-select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
+select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
 
 ##########
 
@@ -53,8 +65,7 @@ EOT
 equiv_opt -assert opt_expr -fine
 design -load postopt
 
-wreduce
-select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
+select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
 
 ##########
 
@@ -68,8 +79,7 @@ EOT
 equiv_opt -assert opt_expr -fine
 design -load postopt
 
-wreduce
-select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
+select -assert-count 1 t:$sub r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
 
 ##########
 
@@ -80,8 +90,8 @@ module opt_expr_sub_test4(input [3:0] i, output [8:0] o);
 endmodule
 EOT
 
+wreduce
 equiv_opt -assert opt_expr -fine
 design -load postopt
 
-wreduce
 select -assert-count 1 t:$sub r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
-- 
cgit v1.2.3


From 8350dfb80906742068b8ee771d15f0741624fed0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 9 Aug 2019 10:30:53 -0700
Subject: Add alumacc versions of opt_expr tests

---
 tests/opt/opt_expr.ys | 84 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 84 insertions(+)

(limited to 'tests')

diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys
index 96ab2f31a..9f5e845ca 100644
--- a/tests/opt/opt_expr.ys
+++ b/tests/opt/opt_expr.ys
@@ -12,6 +12,7 @@ select -assert-count 1 t:$add r:A_WIDTH=5 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
 
 ##########
 
+# alumacc version of above
 design -reset
 read_verilog <<EOT
 module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
@@ -41,6 +42,22 @@ select -assert-count 1 t:$add r:A_WIDTH=5 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
 
 ##########
 
+# alumacc version of above
+design -reset
+read_verilog <<EOT
+module opt_expr_add_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
+    assign o = (i << 4) + j;
+endmodule
+EOT
+
+alumacc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
+
+##########
+
 design -reset
 read_verilog <<EOT
 module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
@@ -55,6 +72,23 @@ select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
 
 ##########
 
+# alumacc version of above
+design -reset
+read_verilog <<EOT
+module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
+    assign o = j - (i << 4);
+endmodule
+EOT
+
+alumacc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+dump
+select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
+
+##########
+
 design -reset
 read_verilog <<EOT
 module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
@@ -69,6 +103,22 @@ select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
 
 ##########
 
+# alumacc version of above
+design -reset
+read_verilog <<EOT
+module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
+    assign o = j - (i << 4);
+endmodule
+EOT
+
+alumacc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
+
+##########
+
 design -reset
 read_verilog <<EOT
 module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o);
@@ -83,6 +133,23 @@ select -assert-count 1 t:$sub r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
 
 ##########
 
+# alumacc version of above
+design -reset
+read_verilog <<EOT
+module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o);
+    assign o = (i << 4) - j;
+endmodule
+EOT
+
+alumacc
+opt_expr -fine
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$alu r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
+
+##########
+
 design -reset
 read_verilog <<EOT
 module opt_expr_sub_test4(input [3:0] i, output [8:0] o);
@@ -95,3 +162,20 @@ equiv_opt -assert opt_expr -fine
 design -load postopt
 
 select -assert-count 1 t:$sub r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
+
+##########
+
+# alumacc version of above
+design -reset
+read_verilog <<EOT
+module opt_expr_sub_test4(input [3:0] i, output [8:0] o);
+    assign o = 5'b00010 - i;
+endmodule
+EOT
+
+wreduce
+alumacc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$alu r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
-- 
cgit v1.2.3


From 0adf81cb91cc4068cff342bf880ba68b17d183c3 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 9 Aug 2019 12:13:17 -0700
Subject: Add $alu tests

---
 tests/opt/opt_expr.ys | 42 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)

(limited to 'tests')

diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys
index 9f5e845ca..f0306efa1 100644
--- a/tests/opt/opt_expr.ys
+++ b/tests/opt/opt_expr.ys
@@ -179,3 +179,45 @@ equiv_opt -assert opt_expr -fine
 design -load postopt
 
 select -assert-count 1 t:$alu r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
+
+###########
+
+design -reset
+read_verilog -icells <<EOT
+module opt_expr_alu_test_ci0_bi0(input [7:0] a, input [3:0] b, output [8:0] x, y, co);
+    \$alu #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(9)) alu (.A(a), .B({b, 4'b0000}), .CI(1'b0), .BI(1'b0), .X(x), .Y(y), .CO(co));
+endmodule
+EOT
+check
+
+equiv_opt -assert opt_expr -fine
+design -load postopt
+select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
+
+###########
+
+design -reset
+read_verilog -icells <<EOT
+module opt_expr_alu_test_ci1_bi1(input [7:0] a, input [3:0] b, output [8:0] x, y, co);
+    \$alu #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(9)) alu (.A(a), .B({b, 4'b0000}), .CI(1'b1), .BI(1'b1), .X(x), .Y(y), .CO(co));
+endmodule
+EOT
+check
+
+equiv_opt opt_expr -fine
+design -load postopt
+select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
+
+###########
+
+design -reset
+read_verilog -icells <<EOT
+module opt_expr_alu_test_ci0_bi1(input [7:0] a, input [3:0] b, output [8:0] x, y, co);
+    \$alu #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(9)) alu (.A(a), .B({b, 4'b0000}), .CI(1'b0), .BI(1'b1), .X(x), .Y(y), .CO(co));
+endmodule
+EOT
+check
+
+equiv_opt opt_expr -fine
+design -load postopt
+select -assert-count 1 t:$alu r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
-- 
cgit v1.2.3