From 3df66027e0de11913aac4b29d6b4ab79550bfb28 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 31 Mar 2020 11:51:31 -0700 Subject: Add dynamic slicing Verilog testcase --- tests/simple/dynslice.v | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 tests/simple/dynslice.v (limited to 'tests') diff --git a/tests/simple/dynslice.v b/tests/simple/dynslice.v new file mode 100644 index 000000000..7236ac3a5 --- /dev/null +++ b/tests/simple/dynslice.v @@ -0,0 +1,12 @@ +module dynslice ( + input clk , + input [9:0] ctrl , + input [15:0] din , + input [3:0] sel , + output reg [127:0] dout +); +always @(posedge clk) +begin + dout[ctrl*sel+:16] <= din ; +end +endmodule -- cgit v1.2.3