From 378d9e6e0c16e13cf161aec283ab366e2462745c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 16 Dec 2019 13:57:55 -0800
Subject: Add another test

---
 tests/arch/xilinx/blockram.ys | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/arch/xilinx/blockram.ys b/tests/arch/xilinx/blockram.ys
index 4b7716739..bb908cbbf 100644
--- a/tests/arch/xilinx/blockram.ys
+++ b/tests/arch/xilinx/blockram.ys
@@ -84,7 +84,14 @@ design -reset
 read_verilog ../common/blockram.v
 hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1
 setattr -set ram_style "block" m:memory
-dump m:*
+synth_xilinx -top sync_ram_sdp
+cd sync_ram_sdp
+select -assert-count 1 t:RAMB18E1
+
+design -reset
+read_verilog ../common/blockram.v
+hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1
+setattr -set ram_block 1 m:memory
 synth_xilinx -top sync_ram_sdp
 cd sync_ram_sdp
 select -assert-count 1 t:RAMB18E1
-- 
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