From 34a08750fa1a490be09411b07f64f4236eff234e Mon Sep 17 00:00:00 2001 From: gatecat Date: Sat, 15 May 2021 14:40:37 +0100 Subject: intel_alm: Fix illegal carry chains Signed-off-by: gatecat --- tests/arch/intel_alm/add_sub.ys | 4 ++-- tests/arch/intel_alm/counter.ys | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'tests') diff --git a/tests/arch/intel_alm/add_sub.ys b/tests/arch/intel_alm/add_sub.ys index 2d464788b..8f87adf27 100644 --- a/tests/arch/intel_alm/add_sub.ys +++ b/tests/arch/intel_alm/add_sub.ys @@ -4,7 +4,7 @@ equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cycl design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module stat -select -assert-count 8 t:MISTRAL_ALUT_ARITH +select -assert-count 9 t:MISTRAL_ALUT_ARITH select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D design -reset @@ -14,5 +14,5 @@ equiv_opt -assert -map +/intel_alm/common/alm_sim.v synth_intel_alm -family cycl design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module stat -select -assert-count 8 t:MISTRAL_ALUT_ARITH +select -assert-count 9 t:MISTRAL_ALUT_ARITH select -assert-none t:MISTRAL_ALUT_ARITH %% t:* %D diff --git a/tests/arch/intel_alm/counter.ys b/tests/arch/intel_alm/counter.ys index f2f3f14f7..56c9cabb3 100644 --- a/tests/arch/intel_alm/counter.ys +++ b/tests/arch/intel_alm/counter.ys @@ -6,7 +6,7 @@ equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/ design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 2 t:MISTRAL_NOT +select -assert-count 1 t:MISTRAL_NOT select -assert-count 8 t:MISTRAL_ALUT_ARITH select -assert-count 8 t:MISTRAL_FF select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D @@ -21,7 +21,7 @@ equiv_opt -async2sync -map +/intel_alm/common/alm_sim.v -map +/intel_alm/common/ design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 2 t:MISTRAL_NOT +select -assert-count 1 t:MISTRAL_NOT select -assert-count 8 t:MISTRAL_ALUT_ARITH select -assert-count 8 t:MISTRAL_FF select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT_ARITH t:MISTRAL_FF %% t:* %D -- cgit v1.2.3