From 2ef2e2c040d9ff299f1bc6daca891a1236ed877e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 22 Nov 2019 16:41:05 -0800
Subject: Add testcase

---
 tests/various/submod.ys | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)
 create mode 100644 tests/various/submod.ys

(limited to 'tests')

diff --git a/tests/various/submod.ys b/tests/various/submod.ys
new file mode 100644
index 000000000..54455b580
--- /dev/null
+++ b/tests/various/submod.ys
@@ -0,0 +1,26 @@
+read_verilog <<EOT
+module top(input a, output [1:0] b);
+wire c;
+(* submod="bar" *) sub s1(a, c);
+assign b[0] = c;
+endmodule
+
+module sub(input a, output c);
+assign c = a;
+endmodule
+EOT
+
+hierarchy -top top
+proc
+design -save gold
+submod
+flatten
+
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+
-- 
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