From 2b9c75f8e372f6886e073743d1df11bcd1c58281 Mon Sep 17 00:00:00 2001 From: Udi Finkelstein Date: Fri, 9 Mar 2018 10:35:33 +0200 Subject: This PR should be the base for discussion, do not merge it yet! It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements. What it DOES'T do: Detect registers connected to output ports of instances. Where it FAILS: memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals. You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines) --- tests/simple/reg_wire_error.v | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 tests/simple/reg_wire_error.v (limited to 'tests') diff --git a/tests/simple/reg_wire_error.v b/tests/simple/reg_wire_error.v new file mode 100644 index 000000000..ab461b95a --- /dev/null +++ b/tests/simple/reg_wire_error.v @@ -0,0 +1,40 @@ +module sub_mod(input i_in, output o_out); +assign o_out = i_in; +endmodule + +module test(i_clk, i_reg, o_reg, o_wire); +input i_clk; +input i_reg; +output o_reg; +output o_wire; + +// Enable this to see how it doesn't fail on yosys although it should +//reg o_wire; +// Enable this instead of the above to see how logic can be mapped to a wire +logic o_wire; +// Enable this to see how it doesn't fail on yosys although it should +//reg i_reg; +// Disable this to see how it doesn't fail on yosys although it should +reg o_reg; + +logic l_reg; + +// Enable this to tst if logic-turne-reg will catch assignments even if done before it turned into a reg +//assign l_reg = !o_reg; +initial o_reg = 1'b0; +always @(posedge i_clk) +begin + o_reg <= !o_reg; + l_reg <= !o_reg; +end + +assign o_wire = !o_reg; +// Uncomment this to see how a logic already turned intoa reg can be freely assigned on yosys +//assign l_reg = !o_reg; + +sub_mod sm_inst ( + .i_in(1'b1), + .o_out(o_reg) +); +endmodule + -- cgit v1.2.3 From 80d9d15f1c4b73ee73172b06fd2c8c55703aea54 Mon Sep 17 00:00:00 2001 From: Udi Finkelstein Date: Tue, 5 Jun 2018 12:15:59 +0300 Subject: reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files --- tests/simple/reg_wire_error.v | 40 ---------------------------------------- tests/various/reg_wire_error.sv | 40 ++++++++++++++++++++++++++++++++++++++++ tests/various/reg_wire_error.ys | 1 + 3 files changed, 41 insertions(+), 40 deletions(-) delete mode 100644 tests/simple/reg_wire_error.v create mode 100644 tests/various/reg_wire_error.sv create mode 100644 tests/various/reg_wire_error.ys (limited to 'tests') diff --git a/tests/simple/reg_wire_error.v b/tests/simple/reg_wire_error.v deleted file mode 100644 index ab461b95a..000000000 --- a/tests/simple/reg_wire_error.v +++ /dev/null @@ -1,40 +0,0 @@ -module sub_mod(input i_in, output o_out); -assign o_out = i_in; -endmodule - -module test(i_clk, i_reg, o_reg, o_wire); -input i_clk; -input i_reg; -output o_reg; -output o_wire; - -// Enable this to see how it doesn't fail on yosys although it should -//reg o_wire; -// Enable this instead of the above to see how logic can be mapped to a wire -logic o_wire; -// Enable this to see how it doesn't fail on yosys although it should -//reg i_reg; -// Disable this to see how it doesn't fail on yosys although it should -reg o_reg; - -logic l_reg; - -// Enable this to tst if logic-turne-reg will catch assignments even if done before it turned into a reg -//assign l_reg = !o_reg; -initial o_reg = 1'b0; -always @(posedge i_clk) -begin - o_reg <= !o_reg; - l_reg <= !o_reg; -end - -assign o_wire = !o_reg; -// Uncomment this to see how a logic already turned intoa reg can be freely assigned on yosys -//assign l_reg = !o_reg; - -sub_mod sm_inst ( - .i_in(1'b1), - .o_out(o_reg) -); -endmodule - diff --git a/tests/various/reg_wire_error.sv b/tests/various/reg_wire_error.sv new file mode 100644 index 000000000..ab461b95a --- /dev/null +++ b/tests/various/reg_wire_error.sv @@ -0,0 +1,40 @@ +module sub_mod(input i_in, output o_out); +assign o_out = i_in; +endmodule + +module test(i_clk, i_reg, o_reg, o_wire); +input i_clk; +input i_reg; +output o_reg; +output o_wire; + +// Enable this to see how it doesn't fail on yosys although it should +//reg o_wire; +// Enable this instead of the above to see how logic can be mapped to a wire +logic o_wire; +// Enable this to see how it doesn't fail on yosys although it should +//reg i_reg; +// Disable this to see how it doesn't fail on yosys although it should +reg o_reg; + +logic l_reg; + +// Enable this to tst if logic-turne-reg will catch assignments even if done before it turned into a reg +//assign l_reg = !o_reg; +initial o_reg = 1'b0; +always @(posedge i_clk) +begin + o_reg <= !o_reg; + l_reg <= !o_reg; +end + +assign o_wire = !o_reg; +// Uncomment this to see how a logic already turned intoa reg can be freely assigned on yosys +//assign l_reg = !o_reg; + +sub_mod sm_inst ( + .i_in(1'b1), + .o_out(o_reg) +); +endmodule + diff --git a/tests/various/reg_wire_error.ys b/tests/various/reg_wire_error.ys new file mode 100644 index 000000000..b9d03155d --- /dev/null +++ b/tests/various/reg_wire_error.ys @@ -0,0 +1 @@ +read_verilog -sv reg_wire_error.sv -- cgit v1.2.3 From 73d426bc879087ca522ca595a8ba921b647fae27 Mon Sep 17 00:00:00 2001 From: Udi Finkelstein Date: Tue, 5 Jun 2018 17:44:24 +0300 Subject: Modified errors into warnings No longer false warnings for memories and assertions --- tests/various/reg_wire_error.sv | 42 +++++++++++++++++++++++++++++++++++++---- 1 file changed, 38 insertions(+), 4 deletions(-) (limited to 'tests') diff --git a/tests/various/reg_wire_error.sv b/tests/various/reg_wire_error.sv index ab461b95a..fe5ff3abd 100644 --- a/tests/various/reg_wire_error.sv +++ b/tests/various/reg_wire_error.sv @@ -2,11 +2,13 @@ module sub_mod(input i_in, output o_out); assign o_out = i_in; endmodule -module test(i_clk, i_reg, o_reg, o_wire); +module test(i_clk, i, i_reg, o_reg, o_wire, o_mr, o_mw, o_ml); input i_clk; +input i; input i_reg; output o_reg; output o_wire; +output o_mr, o_mw, o_ml; // Enable this to see how it doesn't fail on yosys although it should //reg o_wire; @@ -15,12 +17,12 @@ logic o_wire; // Enable this to see how it doesn't fail on yosys although it should //reg i_reg; // Disable this to see how it doesn't fail on yosys although it should -reg o_reg; +//reg o_reg; logic l_reg; // Enable this to tst if logic-turne-reg will catch assignments even if done before it turned into a reg -//assign l_reg = !o_reg; +assign l_reg = !o_reg; initial o_reg = 1'b0; always @(posedge i_clk) begin @@ -30,11 +32,43 @@ end assign o_wire = !o_reg; // Uncomment this to see how a logic already turned intoa reg can be freely assigned on yosys -//assign l_reg = !o_reg; +assign l_reg = !o_reg; sub_mod sm_inst ( .i_in(1'b1), .o_out(o_reg) ); + +wire mw1[0:1]; +wire mw2[0:1]; +wire mw3[0:1]; +reg mr1[0:1]; +reg mr2[0:1]; +reg mr3[0:1]; +logic ml1[0:1]; +logic ml2[0:1]; +logic ml3[0:1]; + +assign o_mw = mw1[i]; +assign o_mr = mr1[i]; +assign o_ml = ml1[i]; + +assign mw1[1] = 1'b1; +//assign mr1[1] = 1'b1; +assign ml1[1] = 1'b1; +always @(posedge i_clk) +begin + mr2[0] = 1'b0; + mw2[0] = 1'b0; + ml2[0] = 1'b0; +end + +always @(posedge i_clk) +begin + mr3[0] <= 1'b0; + mw3[0] <= 1'b0; + ml3[0] <= 1'b0; +end + endmodule -- cgit v1.2.3