From c38ea9ae65b2a987d6a7ea790abf339944069f9a Mon Sep 17 00:00:00 2001 From: whitequark Date: Thu, 6 Dec 2018 14:28:20 +0000 Subject: equiv_opt: new command, for verifying optimization passes. --- tests/lut/check_map.ys | 13 ++----------- tests/opt/opt_lut.ys | 13 +------------ 2 files changed, 3 insertions(+), 23 deletions(-) (limited to 'tests') diff --git a/tests/lut/check_map.ys b/tests/lut/check_map.ys index 6d659891f..dc0aaffc2 100644 --- a/tests/lut/check_map.ys +++ b/tests/lut/check_map.ys @@ -1,13 +1,4 @@ -design -save preopt - simplemap -techmap -map +/gate2lut.v -D LUT_WIDTH=4 +equiv_opt -assert techmap -map +/gate2lut.v -D LUT_WIDTH=4 +design -load postopt select -assert-count 1 t:$lut -design -stash postopt - -design -copy-from preopt -as preopt top -design -copy-from postopt -as postopt top -equiv_make preopt postopt equiv -prep -flatten -top equiv -equiv_induct -equiv_status -assert diff --git a/tests/opt/opt_lut.ys b/tests/opt/opt_lut.ys index 86ad93bb3..f3c1e2822 100644 --- a/tests/opt/opt_lut.ys +++ b/tests/opt/opt_lut.ys @@ -1,15 +1,4 @@ read_verilog opt_lut.v synth_ice40 ice40_unlut -design -save preopt - -opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3 -design -stash postopt - -design -copy-from preopt -as preopt top -design -copy-from postopt -as postopt top -equiv_make preopt postopt equiv -techmap -map ice40_carry.v -prep -flatten -top equiv -equiv_induct -equiv_status -assert +equiv_opt -map ice40_carry.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3 -- cgit v1.2.3 From 7ff5a9db2d17c384260c2220c9205a7b4891f001 Mon Sep 17 00:00:00 2001 From: whitequark Date: Fri, 7 Dec 2018 16:58:33 +0000 Subject: equiv_opt: pass -D EQUIV when techmapping. This allows avoiding techmap crashes e.g. because of large memories in white-box cell models. --- tests/opt/ice40_carry.v | 3 --- tests/opt/opt_lut.ys | 2 +- 2 files changed, 1 insertion(+), 4 deletions(-) delete mode 100644 tests/opt/ice40_carry.v (limited to 'tests') diff --git a/tests/opt/ice40_carry.v b/tests/opt/ice40_carry.v deleted file mode 100644 index ed938932a..000000000 --- a/tests/opt/ice40_carry.v +++ /dev/null @@ -1,3 +0,0 @@ -module SB_CARRY (output CO, input I0, I1, CI); - assign CO = (I0 && I1) || ((I0 || I1) && CI); -endmodule diff --git a/tests/opt/opt_lut.ys b/tests/opt/opt_lut.ys index f3c1e2822..59b12c351 100644 --- a/tests/opt/opt_lut.ys +++ b/tests/opt/opt_lut.ys @@ -1,4 +1,4 @@ read_verilog opt_lut.v synth_ice40 ice40_unlut -equiv_opt -map ice40_carry.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3 +equiv_opt -map +/ice40/cells_sim.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3 -- cgit v1.2.3