From 75abd908294c599c9987978175b46196146c9d1d Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Thu, 31 Dec 2020 16:14:35 -0700 Subject: sv: complete support for implied task/function port directions --- tests/various/func_port_implied_dir.sv | 23 +++++++++++++++++++++++ tests/various/func_port_implied_dir.ys | 6 ++++++ 2 files changed, 29 insertions(+) create mode 100644 tests/various/func_port_implied_dir.sv create mode 100644 tests/various/func_port_implied_dir.ys (limited to 'tests') diff --git a/tests/various/func_port_implied_dir.sv b/tests/various/func_port_implied_dir.sv new file mode 100644 index 000000000..0424f1b46 --- /dev/null +++ b/tests/various/func_port_implied_dir.sv @@ -0,0 +1,23 @@ +module gate(w, x, y, z); + function automatic integer bar( + integer a + ); + bar = 2 ** a; + endfunction + output integer w = bar(4); + + function automatic integer foo( + input integer a, /* implicitly input */ integer b, + output integer c, /* implicitly output */ integer d + ); + c = 42; + d = 51; + foo = a + b + 1; + endfunction + output integer x, y, z; + initial x = foo(1, 2, y, z); +endmodule + +module gold(w, x, y, z); + output integer w = 16, x = 4, y = 42, z = 51; +endmodule diff --git a/tests/various/func_port_implied_dir.ys b/tests/various/func_port_implied_dir.ys new file mode 100644 index 000000000..b5c22a05b --- /dev/null +++ b/tests/various/func_port_implied_dir.ys @@ -0,0 +1,6 @@ +read_verilog -sv func_port_implied_dir.sv +hierarchy +proc +equiv_make gold gate equiv +equiv_simple +equiv_status -assert -- cgit v1.2.3