From a5ca4eeefb13c24042bae36ea8f640b5529efd93 Mon Sep 17 00:00:00 2001
From: Kamil Rakoczy <krakoczy@antmicro.com>
Date: Wed, 24 Jun 2020 11:45:38 +0200
Subject: Add or-assignment and plus-assignment tests

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
---
 tests/opt/opt_expr_or_assignment.ys   | 15 +++++++++++++++
 tests/opt/opt_expr_plus_assignment.ys | 15 +++++++++++++++
 2 files changed, 30 insertions(+)
 create mode 100644 tests/opt/opt_expr_or_assignment.ys
 create mode 100644 tests/opt/opt_expr_plus_assignment.ys

(limited to 'tests')

diff --git a/tests/opt/opt_expr_or_assignment.ys b/tests/opt/opt_expr_or_assignment.ys
new file mode 100644
index 000000000..21e08550f
--- /dev/null
+++ b/tests/opt/opt_expr_or_assignment.ys
@@ -0,0 +1,15 @@
+read_verilog -sv <<EOT
+module opt_expr_or_test(input [3:0] i, input [7:0] j, output [8:0] o);
+wire[8:0] a = 8'b0;
+initial begin
+	a |= i;
+	a |= j;
+end
+    assign o = a;
+endmodule
+EOT
+proc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$or r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
diff --git a/tests/opt/opt_expr_plus_assignment.ys b/tests/opt/opt_expr_plus_assignment.ys
new file mode 100644
index 000000000..8d8ee5214
--- /dev/null
+++ b/tests/opt/opt_expr_plus_assignment.ys
@@ -0,0 +1,15 @@
+read_verilog -sv <<EOT
+module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
+wire[8:0] a = 8'b0;
+initial begin
+	a += i;
+	a += j;
+end
+    assign o = a;
+endmodule
+EOT
+proc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$add r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
-- 
cgit v1.2.3


From f6d06c9f7b01641a657a9f69ef8ce9cb263ff47b Mon Sep 17 00:00:00 2001
From: Kamil Rakoczy <krakoczy@antmicro.com>
Date: Wed, 24 Jun 2020 14:38:03 +0200
Subject: Add xor-assignment test

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
---
 tests/opt/opt_expr_xor_assignment.ys | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
 create mode 100644 tests/opt/opt_expr_xor_assignment.ys

(limited to 'tests')

diff --git a/tests/opt/opt_expr_xor_assignment.ys b/tests/opt/opt_expr_xor_assignment.ys
new file mode 100644
index 000000000..924185e09
--- /dev/null
+++ b/tests/opt/opt_expr_xor_assignment.ys
@@ -0,0 +1,15 @@
+read_verilog -sv <<EOT
+module opt_expr_xor_test(input [3:0] i, input [7:0] j, output [8:0] o);
+wire[8:0] a = 8'b0;
+initial begin
+	a ^= i;
+	a ^= j;
+end
+    assign o = a;
+endmodule
+EOT
+proc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$xor r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
-- 
cgit v1.2.3


From 470df03f3d6731f0b784ceb4e1b05c8583b230a8 Mon Sep 17 00:00:00 2001
From: Kamil Rakoczy <krakoczy@antmicro.com>
Date: Thu, 25 Jun 2020 14:17:41 +0200
Subject: Move combined assign tests to single file

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
---
 tests/opt/opt_expr_combined_assign.ys | 49 +++++++++++++++++++++++++++++++++++
 tests/opt/opt_expr_or_assignment.ys   | 15 -----------
 tests/opt/opt_expr_plus_assignment.ys | 15 -----------
 tests/opt/opt_expr_xor_assignment.ys  | 15 -----------
 4 files changed, 49 insertions(+), 45 deletions(-)
 create mode 100644 tests/opt/opt_expr_combined_assign.ys
 delete mode 100644 tests/opt/opt_expr_or_assignment.ys
 delete mode 100644 tests/opt/opt_expr_plus_assignment.ys
 delete mode 100644 tests/opt/opt_expr_xor_assignment.ys

(limited to 'tests')

diff --git a/tests/opt/opt_expr_combined_assign.ys b/tests/opt/opt_expr_combined_assign.ys
new file mode 100644
index 000000000..56fbac9de
--- /dev/null
+++ b/tests/opt/opt_expr_combined_assign.ys
@@ -0,0 +1,49 @@
+read_verilog -sv <<EOT
+module opt_expr_or_test(input [3:0] i, input [7:0] j, output [8:0] o);
+wire[8:0] a = 8'b0;
+initial begin
+	a |= i;
+	a |= j;
+end
+    assign o = a;
+endmodule
+EOT
+proc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$or r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
+
+design -reset
+read_verilog -sv <<EOT
+module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
+wire[8:0] a = 8'b0;
+initial begin
+        a += i;
+        a += j;
+end
+    assign o = a;
+endmodule
+EOT
+proc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$add r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
+
+design -reset
+read_verilog -sv <<EOT
+module opt_expr_xor_test(input [3:0] i, input [7:0] j, output [8:0] o);
+wire[8:0] a = 8'b0;
+initial begin
+        a ^= i;
+        a ^= j;
+end
+    assign o = a;
+endmodule
+EOT
+proc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$xor r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
diff --git a/tests/opt/opt_expr_or_assignment.ys b/tests/opt/opt_expr_or_assignment.ys
deleted file mode 100644
index 21e08550f..000000000
--- a/tests/opt/opt_expr_or_assignment.ys
+++ /dev/null
@@ -1,15 +0,0 @@
-read_verilog -sv <<EOT
-module opt_expr_or_test(input [3:0] i, input [7:0] j, output [8:0] o);
-wire[8:0] a = 8'b0;
-initial begin
-	a |= i;
-	a |= j;
-end
-    assign o = a;
-endmodule
-EOT
-proc
-equiv_opt -assert opt_expr -fine
-design -load postopt
-
-select -assert-count 1 t:$or r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
diff --git a/tests/opt/opt_expr_plus_assignment.ys b/tests/opt/opt_expr_plus_assignment.ys
deleted file mode 100644
index 8d8ee5214..000000000
--- a/tests/opt/opt_expr_plus_assignment.ys
+++ /dev/null
@@ -1,15 +0,0 @@
-read_verilog -sv <<EOT
-module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
-wire[8:0] a = 8'b0;
-initial begin
-	a += i;
-	a += j;
-end
-    assign o = a;
-endmodule
-EOT
-proc
-equiv_opt -assert opt_expr -fine
-design -load postopt
-
-select -assert-count 1 t:$add r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
diff --git a/tests/opt/opt_expr_xor_assignment.ys b/tests/opt/opt_expr_xor_assignment.ys
deleted file mode 100644
index 924185e09..000000000
--- a/tests/opt/opt_expr_xor_assignment.ys
+++ /dev/null
@@ -1,15 +0,0 @@
-read_verilog -sv <<EOT
-module opt_expr_xor_test(input [3:0] i, input [7:0] j, output [8:0] o);
-wire[8:0] a = 8'b0;
-initial begin
-	a ^= i;
-	a ^= j;
-end
-    assign o = a;
-endmodule
-EOT
-proc
-equiv_opt -assert opt_expr -fine
-design -load postopt
-
-select -assert-count 1 t:$xor r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
-- 
cgit v1.2.3


From 39c39848a21dc4f4a2c3b17842d854047ba6c16f Mon Sep 17 00:00:00 2001
From: Kamil Rakoczy <krakoczy@antmicro.com>
Date: Thu, 25 Jun 2020 14:20:47 +0200
Subject: Add sub-assign and and-assign tests

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
---
 tests/opt/opt_expr_combined_assign.ys | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

(limited to 'tests')

diff --git a/tests/opt/opt_expr_combined_assign.ys b/tests/opt/opt_expr_combined_assign.ys
index 56fbac9de..b18923c7b 100644
--- a/tests/opt/opt_expr_combined_assign.ys
+++ b/tests/opt/opt_expr_combined_assign.ys
@@ -47,3 +47,37 @@ equiv_opt -assert opt_expr -fine
 design -load postopt
 
 select -assert-count 1 t:$xor r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
+
+design -reset
+read_verilog -sv <<EOT
+module opt_expr_sub_test(input [3:0] i, input [7:0] j, output [8:0] o);
+wire[8:0] a = 8'b0;
+initial begin
+        a -= i;
+        a -= j;
+end
+    assign o = a;
+endmodule
+EOT
+proc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$sub r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
+
+design -reset
+read_verilog -sv <<EOT
+module opt_expr_and_test(input [3:0] i, input [7:0] j, output [8:0] o);
+wire[8:0] a = 8'b11111111;
+initial begin
+        a &= i;
+        a &= j;
+end
+    assign o = a;
+endmodule
+EOT
+proc
+equiv_opt -assert opt_expr -fine
+design -load postopt
+
+select -assert-count 1 t:$and r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i
-- 
cgit v1.2.3