From b84415094c193fbeb2053f0a888689ea1502e7cc Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 23 Apr 2020 15:58:36 -0700 Subject: tests: add opt_expr tests --- tests/opt/bug1758.ys | 21 +++++++++++ tests/opt/opt_expr_and.ys | 85 +++++++++++++++++++++++++++++++++++++++++++ tests/opt/opt_expr_or.ys | 85 +++++++++++++++++++++++++++++++++++++++++++ tests/opt/opt_expr_xnor.ys | 85 +++++++++++++++++++++++++++++++++++++++++++ tests/opt/opt_expr_xor.ys | 89 ++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 365 insertions(+) create mode 100644 tests/opt/bug1758.ys create mode 100644 tests/opt/opt_expr_and.ys create mode 100644 tests/opt/opt_expr_or.ys create mode 100644 tests/opt/opt_expr_xnor.ys (limited to 'tests') diff --git a/tests/opt/bug1758.ys b/tests/opt/bug1758.ys new file mode 100644 index 000000000..85dfaceb8 --- /dev/null +++ b/tests/opt/bug1758.ys @@ -0,0 +1,21 @@ +read_verilog -noopt < Date: Thu, 23 Apr 2020 18:15:07 -0700 Subject: opt_expr: do not group by X, more fixes --- tests/opt/opt_expr_xnor.ys | 2 +- tests/opt/opt_expr_xor.ys | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/opt/opt_expr_xnor.ys b/tests/opt/opt_expr_xnor.ys index d712842d5..eadd3ce56 100644 --- a/tests/opt/opt_expr_xnor.ys +++ b/tests/opt/opt_expr_xnor.ys @@ -80,6 +80,6 @@ select -assert-count t c:$_XOR_ cd miter -equiv -flatten -make_assert -make_outputs gold coarse_keepdc miter3 -sat -verify -prove-asserts -show-ports -enable_undef -set-def in_i miter3 +sat -verify -prove-asserts -show-ports -enable_undef miter3 miter -equiv -flatten -make_assert -make_outputs coarse_keepdc fine_keepdc miter4 sat -verify -prove-asserts -show-ports -enable_undef miter4 diff --git a/tests/opt/opt_expr_xor.ys b/tests/opt/opt_expr_xor.ys index b581ac644..411bc396c 100644 --- a/tests/opt/opt_expr_xor.ys +++ b/tests/opt/opt_expr_xor.ys @@ -136,6 +136,6 @@ select -assert-count t c:$_XOR_ cd miter -equiv -flatten -make_assert -make_outputs gold coarse_keepdc miter3 -sat -verify -prove-asserts -show-ports -enable_undef -set-def in_i miter3 +sat -verify -prove-asserts -show-ports -enable_undef miter3 miter -equiv -flatten -make_assert -make_outputs coarse_keepdc fine_keepdc miter4 sat -verify -prove-asserts -show-ports -enable_undef miter4 -- cgit v1.2.3 From ebd6fa945d4f0afa9a7507e791d13653571c8a63 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 24 Apr 2020 11:16:25 -0700 Subject: tests: opt_expr update xnor/xor tests --- tests/opt/opt_expr_xnor.ys | 6 +++--- tests/opt/opt_expr_xor.ys | 7 +++---- 2 files changed, 6 insertions(+), 7 deletions(-) (limited to 'tests') diff --git a/tests/opt/opt_expr_xnor.ys b/tests/opt/opt_expr_xnor.ys index eadd3ce56..0f9463379 100644 --- a/tests/opt/opt_expr_xnor.ys +++ b/tests/opt/opt_expr_xnor.ys @@ -56,7 +56,7 @@ copy gold fine_keepdc cd coarse opt_expr -fine -select -assert-count 1 t:$xnor # FIXME: Should be zero +select -assert-none t:$xnor cd fine simplemap @@ -71,12 +71,12 @@ sat -verify -prove-asserts -show-ports -enable_undef miter2 cd coarse_keepdc opt_expr -keepdc -fine -select -assert-count 2 t:$xnor $ FIXME: Should be one +select -assert-count 1 t:$xnor cd fine_keepdc simplemap opt_expr -keepdc -select -assert-count t c:$_XOR_ +select -assert-count 0 c:$_XOR_ cd miter -equiv -flatten -make_assert -make_outputs gold coarse_keepdc miter3 diff --git a/tests/opt/opt_expr_xor.ys b/tests/opt/opt_expr_xor.ys index 411bc396c..a879f3ec9 100644 --- a/tests/opt/opt_expr_xor.ys +++ b/tests/opt/opt_expr_xor.ys @@ -111,7 +111,7 @@ copy gold fine_keepdc cd coarse opt_expr -fine -select -assert-count 1 t:$xor # FIXME: Should be zero +select -assert-count 0 t:$xor cd fine simplemap @@ -126,13 +126,12 @@ sat -verify -prove-asserts -show-ports -enable_undef miter2 cd coarse_keepdc opt_expr -keepdc -fine -dump -select -assert-count 2 t:$xor $ FIXME: Should be one +select -assert-count 1 t:$xor cd fine_keepdc simplemap opt_expr -keepdc -select -assert-count t c:$_XOR_ +select -assert-count 3 t:$_XOR_ cd miter -equiv -flatten -make_assert -make_outputs gold coarse_keepdc miter3 -- cgit v1.2.3 From b5f38f834207fab3a563c55568c4543a3b5dcc1f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 24 Apr 2020 14:13:45 -0700 Subject: opt_expr: const_xnor replacement to pad Y with 1'b1 --- tests/opt/opt_expr_xnor.ys | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'tests') diff --git a/tests/opt/opt_expr_xnor.ys b/tests/opt/opt_expr_xnor.ys index 0f9463379..f8ef0d352 100644 --- a/tests/opt/opt_expr_xnor.ys +++ b/tests/opt/opt_expr_xnor.ys @@ -83,3 +83,49 @@ miter -equiv -flatten -make_assert -make_outputs gold coarse_keepdc miter3 sat -verify -prove-asserts -show-ports -enable_undef miter3 miter -equiv -flatten -make_assert -make_outputs coarse_keepdc fine_keepdc miter4 sat -verify -prove-asserts -show-ports -enable_undef miter4 + + +# Single-bit $xnor extension +design -reset +read_verilog -noopt < Date: Fri, 24 Apr 2020 14:31:33 -0700 Subject: tests: fsm to use a randomly-generated seed --- tests/fsm/generate.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'tests') diff --git a/tests/fsm/generate.py b/tests/fsm/generate.py index c8eda0cd1..784e5a054 100644 --- a/tests/fsm/generate.py +++ b/tests/fsm/generate.py @@ -36,9 +36,11 @@ parser.add_argument('-S', '--seed', type = int, help = 'seed for PRNG') parser.add_argument('-c', '--count', type = int, default = 50, help = 'number of test cases to generate') args = parser.parse_args() -if args.seed is not None: - print("PRNG seed: %d" % args.seed) - random.seed(args.seed) +seed = args.seed +if seed is None: + seed = random.randrange(sys.maxsize) +print("PRNG seed: %d" % seed) +random.seed(seed) for idx in range(args.count): with open('temp/uut_%05d.v' % idx, 'w') as f: -- cgit v1.2.3 From 2e911bc806d0a54e4d7e84ef2218ff088ea20b5f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 4 May 2020 12:18:02 -0700 Subject: test: add failing test --- tests/verilog/upto.ys | 5 +++++ 1 file changed, 5 insertions(+) create mode 100644 tests/verilog/upto.ys (limited to 'tests') diff --git a/tests/verilog/upto.ys b/tests/verilog/upto.ys new file mode 100644 index 000000000..d87f4424e --- /dev/null +++ b/tests/verilog/upto.ys @@ -0,0 +1,5 @@ +read_verilog < Date: Tue, 5 May 2020 04:11:16 +0000 Subject: ast/simplify: don't bitblast async ROMs declared as `logic`. Fixes #2020. --- tests/svtypes/logic_rom.sv | 6 ++++++ tests/svtypes/logic_rom.ys | 3 +++ 2 files changed, 9 insertions(+) create mode 100644 tests/svtypes/logic_rom.sv create mode 100644 tests/svtypes/logic_rom.ys (limited to 'tests') diff --git a/tests/svtypes/logic_rom.sv b/tests/svtypes/logic_rom.sv new file mode 100644 index 000000000..45fe0a4ca --- /dev/null +++ b/tests/svtypes/logic_rom.sv @@ -0,0 +1,6 @@ +module top(input [3:0] addr, output [7:0] data); + logic [7:0] mem[0:15]; + assign data = mem[addr]; + integer i; + initial for(i = 0; i < 16; i = i + 1) mem[i] = i; +endmodule diff --git a/tests/svtypes/logic_rom.ys b/tests/svtypes/logic_rom.ys new file mode 100644 index 000000000..7b079c136 --- /dev/null +++ b/tests/svtypes/logic_rom.ys @@ -0,0 +1,3 @@ +read_verilog -sv logic_rom.sv +prep -top top +select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=8 %i -- cgit v1.2.3 From 004999218f52cd5a1308023a474ee608b842a5b7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 5 May 2020 08:01:27 -0700 Subject: techlibs/common: more robustness when *_WIDTH = 0 --- tests/verilog/upto.ys | 1 - 1 file changed, 1 deletion(-) (limited to 'tests') diff --git a/tests/verilog/upto.ys b/tests/verilog/upto.ys index d87f4424e..2f3394761 100644 --- a/tests/verilog/upto.ys +++ b/tests/verilog/upto.ys @@ -2,4 +2,3 @@ read_verilog < Date: Fri, 8 May 2020 11:07:11 -0700 Subject: tests: opt_expr tests that depend on consumex --- tests/opt/opt_expr_consumex.ys | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 tests/opt/opt_expr_consumex.ys (limited to 'tests') diff --git a/tests/opt/opt_expr_consumex.ys b/tests/opt/opt_expr_consumex.ys new file mode 100644 index 000000000..d4af10f22 --- /dev/null +++ b/tests/opt/opt_expr_consumex.ys @@ -0,0 +1,35 @@ +read_verilog < Date: Fri, 8 May 2020 11:12:58 -0700 Subject: test: update opt_expr_alu test --- tests/opt/opt_expr_alu.ys | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/opt/opt_expr_alu.ys b/tests/opt/opt_expr_alu.ys index 9121c0096..477555da9 100644 --- a/tests/opt/opt_expr_alu.ys +++ b/tests/opt/opt_expr_alu.ys @@ -59,9 +59,8 @@ EOT alumacc equiv_opt -assert opt_expr -fine design -load postopt -select -assert-count 1 t:$pos select -assert-count 1 t:$not -select -assert-none t:$pos t:$not %% t:* %D +select -assert-none t:$not %% t:* %D design -reset -- cgit v1.2.3 From b11cf67a8170ee830beedadc7156c4e83e4f1134 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 11 May 2020 10:30:20 -0700 Subject: Setup tests/verilog properly --- tests/verilog/.gitignore | 3 +++ tests/verilog/run-test.sh | 20 ++++++++++++++++++++ 2 files changed, 23 insertions(+) create mode 100644 tests/verilog/.gitignore create mode 100755 tests/verilog/run-test.sh (limited to 'tests') diff --git a/tests/verilog/.gitignore b/tests/verilog/.gitignore new file mode 100644 index 000000000..b48f808a1 --- /dev/null +++ b/tests/verilog/.gitignore @@ -0,0 +1,3 @@ +/*.log +/*.out +/run-test.mk diff --git a/tests/verilog/run-test.sh b/tests/verilog/run-test.sh new file mode 100755 index 000000000..ea56b70f0 --- /dev/null +++ b/tests/verilog/run-test.sh @@ -0,0 +1,20 @@ +#!/usr/bin/env bash +set -e +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log $x" +done +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s" + fi +done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk -- cgit v1.2.3 From e5ce5a4fd532f35cf8dd625b97aa426e4661e119 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 11 May 2020 11:05:19 -0700 Subject: tests: add #2042 testcase --- tests/verilog/bug2042.ys | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 tests/verilog/bug2042.ys (limited to 'tests') diff --git a/tests/verilog/bug2042.ys b/tests/verilog/bug2042.ys new file mode 100644 index 000000000..009e2c20c --- /dev/null +++ b/tests/verilog/bug2042.ys @@ -0,0 +1,12 @@ +logger -expect error "Non-ANSI style task/function arguments not currently supported" 1 +read_verilog < Date: Wed, 13 May 2020 10:11:45 -0700 Subject: tests: update/extend task argument tests --- tests/verilog/bug2042-sv.ys | 34 ++++++++++++++++++++++++++++++++++ tests/verilog/bug2042.ys | 3 +-- 2 files changed, 35 insertions(+), 2 deletions(-) create mode 100644 tests/verilog/bug2042-sv.ys (limited to 'tests') diff --git a/tests/verilog/bug2042-sv.ys b/tests/verilog/bug2042-sv.ys new file mode 100644 index 000000000..9a0d419c8 --- /dev/null +++ b/tests/verilog/bug2042-sv.ys @@ -0,0 +1,34 @@ +read_verilog -sv < Date: Thu, 14 May 2020 00:26:23 -0700 Subject: opt_clean: add init test --- tests/opt/opt_clean_init.ys | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 tests/opt/opt_clean_init.ys (limited to 'tests') diff --git a/tests/opt/opt_clean_init.ys b/tests/opt/opt_clean_init.ys new file mode 100644 index 000000000..bfc383955 --- /dev/null +++ b/tests/opt/opt_clean_init.ys @@ -0,0 +1,13 @@ +logger -expect warning "Initial value conflict for wire '\\y' and value '1'0'" 1 +logger -expect-no-warnings +read_verilog < Date: Thu, 14 May 2020 00:59:38 -0700 Subject: opt_clean: improve warning message --- tests/opt/opt_clean_init.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/opt/opt_clean_init.ys b/tests/opt/opt_clean_init.ys index bfc383955..0d567608d 100644 --- a/tests/opt/opt_clean_init.ys +++ b/tests/opt/opt_clean_init.ys @@ -1,4 +1,4 @@ -logger -expect warning "Initial value conflict for wire '\\y' and value '1'0'" 1 +logger -expect warning "Initial value conflict for \\y resolving to 1'0 but with init 1'1" 1 logger -expect-no-warnings read_verilog < Date: Thu, 14 May 2020 08:36:36 -0700 Subject: test: add another testcase as per @nakengelhardt --- tests/verilog/bug2042-sv.ys | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'tests') diff --git a/tests/verilog/bug2042-sv.ys b/tests/verilog/bug2042-sv.ys index 9a0d419c8..e815d7fc5 100644 --- a/tests/verilog/bug2042-sv.ys +++ b/tests/verilog/bug2042-sv.ys @@ -20,6 +20,31 @@ proc sat -verify -prove-asserts +design -reset +read_verilog -sv < Date: Wed, 15 Apr 2020 12:27:26 -0700 Subject: xilinx: remove no-longer-relevant test --- tests/arch/xilinx/abc9_map.ys | 91 ------------------------------------------- 1 file changed, 91 deletions(-) delete mode 100644 tests/arch/xilinx/abc9_map.ys (limited to 'tests') diff --git a/tests/arch/xilinx/abc9_map.ys b/tests/arch/xilinx/abc9_map.ys deleted file mode 100644 index 4a7b9384a..000000000 --- a/tests/arch/xilinx/abc9_map.ys +++ /dev/null @@ -1,91 +0,0 @@ -read_verilog < Date: Wed, 15 Apr 2020 12:28:03 -0700 Subject: xilinx: update abc9_dff tests --- tests/arch/xilinx/abc9_dff.ys | 63 ++++++++++++++++++++++++++++++------------- 1 file changed, 45 insertions(+), 18 deletions(-) (limited to 'tests') diff --git a/tests/arch/xilinx/abc9_dff.ys b/tests/arch/xilinx/abc9_dff.ys index b457cefce..abe597e2c 100644 --- a/tests/arch/xilinx/abc9_dff.ys +++ b/tests/arch/xilinx/abc9_dff.ys @@ -1,32 +1,59 @@ +logger -nowarn "Yosys has only limited support for tri-state logic at the moment\. .*" + +read_verilog < Date: Wed, 15 Apr 2020 15:41:55 -0700 Subject: abc9: suppress warnings when no compatible + used flop boxes formed --- tests/arch/xilinx/abc9_dff.ys | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/arch/xilinx/abc9_dff.ys b/tests/arch/xilinx/abc9_dff.ys index abe597e2c..15343970f 100644 --- a/tests/arch/xilinx/abc9_dff.ys +++ b/tests/arch/xilinx/abc9_dff.ys @@ -14,6 +14,7 @@ endmodule EOT equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf design -load postopt +select -assert-count 6 t:FD* select -assert-count 6 c:fd2 c:fd3 c:fd4 c:fd6 c:fd7 c:fd8 @@ -32,6 +33,7 @@ endmodule EOT equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf design -load postopt +select -assert-count 4 t:FD* select -assert-count 4 c:fd3 c:fd4 c:fd7 c:fd8 @@ -54,6 +56,6 @@ logger -expect warning "Module 'FDSE' contains a \$_DFF_P_ cell .*" 1 logger -expect warning "Module '\$paramod\\FDSE_1\\INIT=1' contains a \$_DFF_N_ cell .*" 1 equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf design -load postopt -#select -assert-count 4 c:fd3 c:fd4 c:fd7 c:fd8 +select -assert-count 8 t:FD* logger -expect-no-warnings -- cgit v1.2.3 From 48052ad813db3561a959a1921466d571bafa354c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 16 Apr 2020 10:24:02 -0700 Subject: abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too --- tests/various/abc9.ys | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'tests') diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys index 6e2415ad7..7a3a503e4 100644 --- a/tests/various/abc9.ys +++ b/tests/various/abc9.ys @@ -45,14 +45,16 @@ sat -seq 10 -verify -prove-asserts -show-ports miter design -reset read_verilog -icells < Date: Thu, 16 Apr 2020 10:49:33 -0700 Subject: abc9: test to use box file instead of auto --- tests/simple_abc9/abc9.box | 3 +++ tests/simple_abc9/abc9.v | 2 +- tests/simple_abc9/run-test.sh | 2 +- 3 files changed, 5 insertions(+), 2 deletions(-) create mode 100644 tests/simple_abc9/abc9.box (limited to 'tests') diff --git a/tests/simple_abc9/abc9.box b/tests/simple_abc9/abc9.box new file mode 100644 index 000000000..b3c88437c --- /dev/null +++ b/tests/simple_abc9/abc9.box @@ -0,0 +1,3 @@ +MUXF8 1 0 3 1 +#I0 I1 S +0 0 0 # O diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 688b47586..5e969c614 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -213,7 +213,7 @@ module arbiter (clk, rst, request, acknowledge, grant, grant_valid, grant_encode input rst; endmodule -(* abc9_box, blackbox *) +(* abc9_box_id=1, blackbox *) module MUXF8(input I0, I1, S, output O); specify (I0 => O) = 0; diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh index 424d8f417..650e42fca 100755 --- a/tests/simple_abc9/run-test.sh +++ b/tests/simple_abc9/run-test.sh @@ -25,7 +25,7 @@ exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v *.sv EXTRA_FLAGS="-n 300 -p synth -run coarse; \ opt -full; \ techmap; \ - abc9 -lut 4; \ + abc9 -lut 4 -box ../abc9.box; \ clean; \ check -assert; \ select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%; \ -- cgit v1.2.3 From 722540dbf942d2b8acbaf7372001c7d982eb2845 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 16 Apr 2020 12:08:59 -0700 Subject: abc9: not enough to techmap_fail on (* init=1 *), hide them using $__ --- tests/various/abc9.ys | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys index 7a3a503e4..9586091c4 100644 --- a/tests/various/abc9.ys +++ b/tests/various/abc9.ys @@ -50,7 +50,7 @@ $_DFF_P_ ff(.C(clk), .D(d), .Q(w)); assign q = w; endmodule EOT -equiv_opt abc9 -lut 4 -dff +equiv_opt -assert abc9 -lut 4 -dff design -load postopt cd abc9_test036 select -assert-count 1 t:$_DFF_P_ @@ -69,8 +69,27 @@ specify endspecify endmodule -module top(input [1:0] i, output o); +module abc9_test037(input [1:0] i, output o); LUT2 #(.mask(4'b0)) lut (.i(i), .o(o)); endmodule EOT abc9 + + +design -reset +read_verilog -icells < Date: Tue, 21 Apr 2020 12:22:39 -0700 Subject: abc9_ops: add -prep_bypass for auto bypass boxes; refactor Eliminate need for abc9_{,un}map.v in xilinx -prep_dff_{hier,unmap} -> -prep_hier --- tests/arch/xilinx/abc9_dff.ys | 34 +++++++++++++++++++++++++++++----- 1 file changed, 29 insertions(+), 5 deletions(-) (limited to 'tests') diff --git a/tests/arch/xilinx/abc9_dff.ys b/tests/arch/xilinx/abc9_dff.ys index 15343970f..fd343969b 100644 --- a/tests/arch/xilinx/abc9_dff.ys +++ b/tests/arch/xilinx/abc9_dff.ys @@ -46,16 +46,40 @@ FDCE #(.INIT(1)) fd3(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[2])); FDPE #(.INIT(1)) fd4(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[3])); FDRE_1 #(.INIT(1)) fd5(.C(C), .CE(1'b0), .D(D), .R(1'b0), .Q(Q[4])); FDSE_1 #(.INIT(1)) fd6(.C(C), .CE(1'b0), .D(D), .S(1'b0), .Q(Q[5])); -FDCE_1 #(.INIT(1)) fd7(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[6])); +FDCE_1 /*#(.INIT(1))*/ fd7(.C(C), .CE(1'b0), .D(D), .CLR(1'b0), .Q(Q[6])); FDPE_1 #(.INIT(1)) fd8(.C(C), .CE(1'b0), .D(D), .PRE(1'b0), .Q(Q[7])); endmodule EOT -logger -expect warning "Module '\$paramod\\FDRE\\INIT=1' contains a \$_DFF_P_ cell .*" 1 -logger -expect warning "Module '\$paramod\\FDRE_1\\INIT=1' contains a \$_DFF_N_ cell .*" 1 -logger -expect warning "Module 'FDSE' contains a \$_DFF_P_ cell .*" 1 -logger -expect warning "Module '\$paramod\\FDSE_1\\INIT=1' contains a \$_DFF_N_ cell .*" 1 +logger -expect warning "Module '\$paramod\\FDRE\\INIT=1' contains a \$dff cell .*" 1 +logger -expect warning "Module '\$paramod\\FDRE_1\\INIT=1' contains a \$dff cell .*" 1 +logger -expect warning "Module 'FDSE' contains a \$dff cell .*" 1 +logger -expect warning "Module '\$paramod\\FDSE_1\\INIT=1' contains a \$dff cell .*" 1 equiv_opt -assert -multiclock -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad -noclkbuf design -load postopt select -assert-count 8 t:FD* + +design -reset +read_verilog < Date: Thu, 14 May 2020 00:29:45 -0700 Subject: abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it --- tests/various/abc9.ys | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'tests') diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys index 9586091c4..ac714665f 100644 --- a/tests/various/abc9.ys +++ b/tests/various/abc9.ys @@ -78,18 +78,23 @@ abc9 design -reset read_verilog -icells < Date: Thu, 14 May 2020 16:09:41 -0700 Subject: tests: attributes before task enable --- tests/verilog/task_attr.ys | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 tests/verilog/task_attr.ys (limited to 'tests') diff --git a/tests/verilog/task_attr.ys b/tests/verilog/task_attr.ys new file mode 100644 index 000000000..d6e75f85f --- /dev/null +++ b/tests/verilog/task_attr.ys @@ -0,0 +1,28 @@ +read_verilog < Date: Mon, 18 May 2020 18:15:03 +0200 Subject: Add force_downto and force_upto wire attributes. Fixes #2058. --- tests/arch/xilinx/mux.ys | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/arch/xilinx/mux.ys b/tests/arch/xilinx/mux.ys index 99817738d..1b2788448 100644 --- a/tests/arch/xilinx/mux.ys +++ b/tests/arch/xilinx/mux.ys @@ -40,8 +40,10 @@ proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-min 5 t:LUT6 +select -assert-max 2 t:LUT4 +select -assert-min 4 t:LUT6 select -assert-max 7 t:LUT6 select -assert-max 2 t:MUXF7 +dump -select -assert-none t:LUT6 t:MUXF7 %% t:* %D +select -assert-none t:LUT6 t:LUT4 t:MUXF7 %% t:* %D -- cgit v1.2.3 From 33b03ce904f6810437e27ca7a6df4fb1e966fc23 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sun, 24 May 2020 08:48:23 -0700 Subject: xaiger: add testcase --- tests/various/xaiger.ys | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 tests/various/xaiger.ys (limited to 'tests') diff --git a/tests/various/xaiger.ys b/tests/various/xaiger.ys new file mode 100644 index 000000000..f612d2e18 --- /dev/null +++ b/tests/various/xaiger.ys @@ -0,0 +1,13 @@ +read_verilog < Date: Mon, 11 May 2020 09:33:11 -0700 Subject: tests: add #2037 testcase --- tests/verilog/bug2037.ys | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 tests/verilog/bug2037.ys (limited to 'tests') diff --git a/tests/verilog/bug2037.ys b/tests/verilog/bug2037.ys new file mode 100644 index 000000000..afe92022e --- /dev/null +++ b/tests/verilog/bug2037.ys @@ -0,0 +1,9 @@ +logger -expect warning "Attribute\(s\) attached to null statement\. Ignoring\." 1 +logger -expect-no-warnings +read_verilog < Date: Mon, 11 May 2020 10:26:08 -0700 Subject: tests: add an generate-else test too --- tests/verilog/bug2037.ys | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'tests') diff --git a/tests/verilog/bug2037.ys b/tests/verilog/bug2037.ys index afe92022e..42c4b8f5d 100644 --- a/tests/verilog/bug2037.ys +++ b/tests/verilog/bug2037.ys @@ -7,3 +7,37 @@ module test (); if (y) (* foo *) ; endmodule EOT + + +design -reset +logger -expect warning "Attribute\(s\) attached to null statement\. Ignoring\." 3 # cumulative +logger -expect-no-warnings +read_verilog < Date: Thu, 14 May 2020 10:46:40 -0700 Subject: verilog: do not warn for attributes on null statements --- tests/verilog/bug2037.ys | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'tests') diff --git a/tests/verilog/bug2037.ys b/tests/verilog/bug2037.ys index 42c4b8f5d..eb4f0fac4 100644 --- a/tests/verilog/bug2037.ys +++ b/tests/verilog/bug2037.ys @@ -1,4 +1,3 @@ -logger -expect warning "Attribute\(s\) attached to null statement\. Ignoring\." 1 logger -expect-no-warnings read_verilog < Date: Thu, 14 May 2020 16:32:14 -0700 Subject: test: add attribute-before-stmt test from @nakengelhardt --- tests/verilog/bug2037.ys | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'tests') diff --git a/tests/verilog/bug2037.ys b/tests/verilog/bug2037.ys index eb4f0fac4..4b629ba92 100644 --- a/tests/verilog/bug2037.ys +++ b/tests/verilog/bug2037.ys @@ -41,3 +41,18 @@ module test (); endmodule EOT select -assert-none a:* + + +design -reset +read_verilog < Date: Mon, 25 May 2020 10:07:58 -0700 Subject: tests: fix some test warnings --- tests/arch/xilinx/pmgen_xilinx_srl.ys | 2 +- tests/arch/xilinx/xilinx_srl.v | 2 +- tests/various/attrib07_func_call.v | 2 +- tests/various/constmsk_testmap.v | 2 +- tests/various/shregmap.v | 4 ++-- tests/verilog/bug2042-sv.ys | 2 +- 6 files changed, 7 insertions(+), 7 deletions(-) (limited to 'tests') diff --git a/tests/arch/xilinx/pmgen_xilinx_srl.ys b/tests/arch/xilinx/pmgen_xilinx_srl.ys index ea2f20487..e76fb20ab 100644 --- a/tests/arch/xilinx/pmgen_xilinx_srl.ys +++ b/tests/arch/xilinx/pmgen_xilinx_srl.ys @@ -1,6 +1,6 @@ read_verilog -icells < Date: Mon, 25 May 2020 09:35:41 -0700 Subject: tests: xilinx macc test to have initval, shorten BMC depth for runtime --- tests/arch/xilinx/macc.v | 12 ++++++------ tests/arch/xilinx/macc.ys | 4 ++-- 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'tests') diff --git a/tests/arch/xilinx/macc.v b/tests/arch/xilinx/macc.v index e36b2bab1..1645537fd 100644 --- a/tests/arch/xilinx/macc.v +++ b/tests/arch/xilinx/macc.v @@ -10,10 +10,10 @@ module macc # (parameter SIZEIN = 16, SIZEOUT = 40) ( output signed [SIZEOUT-1:0] accum_out ); // Declare registers for intermediate values -reg signed [SIZEIN-1:0] a_reg, b_reg; -reg sload_reg; -reg signed [2*SIZEIN-1:0] mult_reg; -reg signed [SIZEOUT-1:0] adder_out, old_result; +reg signed [SIZEIN-1:0] a_reg = 0, b_reg = 0; +reg sload_reg = 0; +reg signed [2*SIZEIN-1:0] mult_reg = 0; +reg signed [SIZEOUT-1:0] adder_out = 0, old_result; always @* /*(adder_out or sload_reg)*/ begin // Modification necessary to fix sim/synth mismatch if (sload_reg) old_result <= 0; @@ -50,10 +50,10 @@ module macc2 # (parameter SIZEIN = 16, SIZEOUT = 40) ( output overflow ); // Declare registers for intermediate values -reg signed [SIZEIN-1:0] a_reg, b_reg, a_reg2, b_reg2; +reg signed [SIZEIN-1:0] a_reg = 0, b_reg = 0, a_reg2 = 0, b_reg2 = 0; reg signed [2*SIZEIN-1:0] mult_reg = 0; reg signed [SIZEOUT:0] adder_out = 0; -reg overflow_reg; +reg overflow_reg = 0; always @(posedge clk) begin //if (ce) begin diff --git a/tests/arch/xilinx/macc.ys b/tests/arch/xilinx/macc.ys index bf2b36320..61a570f48 100644 --- a/tests/arch/xilinx/macc.ys +++ b/tests/arch/xilinx/macc.ys @@ -6,7 +6,7 @@ proc #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad ### TODO equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter +sat -verify -prove-asserts -seq 3 -show-inputs -show-outputs miter design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd macc # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG @@ -20,7 +20,7 @@ proc #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad ### TODO equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter +sat -verify -prove-asserts -seq 4 -show-inputs -show-outputs miter design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd macc2 # Constrain all select calls below inside the top module -- cgit v1.2.3 From 6228b10c9f354afaa009491b061583e8a686fbd8 Mon Sep 17 00:00:00 2001 From: Alberto Gonzalez Date: Wed, 27 May 2020 07:58:10 +0000 Subject: printattrs: Add test. --- tests/various/printattr.ys | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 tests/various/printattr.ys (limited to 'tests') diff --git a/tests/various/printattr.ys b/tests/various/printattr.ys new file mode 100644 index 000000000..afc6d8eb6 --- /dev/null +++ b/tests/various/printattr.ys @@ -0,0 +1,14 @@ +logger -expect log ".*cells_not_processed=[01]* .*" 1 +logger -expect log ".*src=.< Date: Tue, 21 Apr 2020 16:37:29 +0200 Subject: Expand tests/simple/constmuldivmod.v --- tests/simple/constmuldivmod.v | 42 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/simple/constmuldivmod.v b/tests/simple/constmuldivmod.v index d1d8be862..5dd8f9295 100644 --- a/tests/simple/constmuldivmod.v +++ b/tests/simple/constmuldivmod.v @@ -1,4 +1,4 @@ -module constmuldivmod(input [7:0] A, input [2:0] mode, output reg [7:0] Y); +module constmuldivmod(input [7:0] A, input [5:0] mode, output reg [7:0] Y); always @* begin case (mode) 0: Y = A / 8'd0; @@ -21,6 +21,46 @@ module constmuldivmod(input [7:0] A, input [2:0] mode, output reg [7:0] Y); 13: Y = A % 8'd8; 14: Y = A * 8'd8; + 15: Y = $signed(A) / $signed(8'd0); + 16: Y = $signed(A) % $signed(8'd0); + 17: Y = $signed(A) * $signed(8'd0); + + 18: Y = $signed(A) / $signed(8'd1); + 19: Y = $signed(A) % $signed(8'd1); + 20: Y = $signed(A) * $signed(8'd1); + + 21: Y = $signed(A) / $signed(8'd2); + 22: Y = $signed(A) % $signed(8'd2); + 23: Y = $signed(A) * $signed(8'd2); + + 24: Y = $signed(A) / $signed(8'd4); + 25: Y = $signed(A) % $signed(8'd4); + 26: Y = $signed(A) * $signed(8'd4); + + 27: Y = $signed(A) / $signed(8'd8); + 28: Y = $signed(A) % $signed(8'd8); + 29: Y = $signed(A) * $signed(8'd8); + + 30: Y = $signed(A) / $signed(-8'd0); + 31: Y = $signed(A) % $signed(-8'd0); + 32: Y = $signed(A) * $signed(-8'd0); + + 33: Y = $signed(A) / $signed(-8'd1); + 34: Y = $signed(A) % $signed(-8'd1); + 35: Y = $signed(A) * $signed(-8'd1); + + 36: Y = $signed(A) / $signed(-8'd2); + 37: Y = $signed(A) % $signed(-8'd2); + 38: Y = $signed(A) * $signed(-8'd2); + + 39: Y = $signed(A) / $signed(-8'd4); + 40: Y = $signed(A) % $signed(-8'd4); + 41: Y = $signed(A) * $signed(-8'd4); + + 42: Y = $signed(A) / $signed(-8'd8); + 43: Y = $signed(A) % $signed(-8'd8); + 44: Y = $signed(A) * $signed(-8'd8); + default: Y = 8'd16 * A; endcase end -- cgit v1.2.3 From 0a88f002e50c0196175303068bcb3875a01d2c57 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 1 Jun 2020 13:48:19 +0200 Subject: allow range for mux test --- tests/arch/ice40/mux.ys | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/arch/ice40/mux.ys b/tests/arch/ice40/mux.ys index 99822391d..2b661fd6b 100644 --- a/tests/arch/ice40/mux.ys +++ b/tests/arch/ice40/mux.ys @@ -35,6 +35,7 @@ proc equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-count 11 t:SB_LUT4 +select -assert-min 11 t:SB_LUT4 +select -assert-max 12 t:SB_LUT4 select -assert-none t:SB_LUT4 %% t:* %D -- cgit v1.2.3