From 0b308c68357cc85876c3c86d6e5ac8b9318329ca Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 5 Feb 2020 14:46:48 -0800 Subject: abc9_ops: -reintegrate to use derived_type for box_ports --- tests/arch/xilinx/dffs.ys | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/arch/xilinx/dffs.ys b/tests/arch/xilinx/dffs.ys index dc764b033..deaf16bd6 100644 --- a/tests/arch/xilinx/dffs.ys +++ b/tests/arch/xilinx/dffs.ys @@ -8,7 +8,6 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd dff # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDRE - select -assert-none t:BUFG t:FDRE %% t:* %D @@ -20,6 +19,27 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd dffe # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDRE +select -assert-none t:BUFG t:FDRE %% t:* %D + + +design -load read +hierarchy -top dff +proc +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dff # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 1 t:FDRE +select -assert-none t:BUFG t:FDRE %% t:* %D + +design -load read +hierarchy -top dffe +proc +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 1 t:FDRE select -assert-none t:BUFG t:FDRE %% t:* %D -- cgit v1.2.3