From 8b239ee707a2bf4a868728046d7f64c16d74aa2a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Sep 2019 15:34:04 -0700
Subject: Add quick test

---
 tests/techmap/aigmap.ys | 10 ++++++++++
 1 file changed, 10 insertions(+)
 create mode 100644 tests/techmap/aigmap.ys

(limited to 'tests')

diff --git a/tests/techmap/aigmap.ys b/tests/techmap/aigmap.ys
new file mode 100644
index 000000000..a40aa39f1
--- /dev/null
+++ b/tests/techmap/aigmap.ys
@@ -0,0 +1,10 @@
+read_verilog <<EOT
+module top(input i, j, s, output o, p);
+assign o = s ? j : i;
+assign p = ~i;
+endmodule
+EOT
+
+select t:$mux
+aigmap -select
+select -assert-any %
-- 
cgit v1.2.3


From 369652d4b99181e2f7b875b6c458c1a5a3b0381e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Sep 2019 17:20:39 -0700
Subject: Add test

---
 tests/techmap/techmap_replace.ys | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 tests/techmap/techmap_replace.ys

(limited to 'tests')

diff --git a/tests/techmap/techmap_replace.ys b/tests/techmap/techmap_replace.ys
new file mode 100644
index 000000000..ee5c6bc7e
--- /dev/null
+++ b/tests/techmap/techmap_replace.ys
@@ -0,0 +1,16 @@
+read_verilog <<EOT
+module sub(input i, output o, input j);
+foobar _TECHMAP_REPLACE_(i, o, j);
+wire _TECHMAP_REPLACE_.asdf = i ;
+endmodule
+EOT
+design -stash techmap
+
+read_verilog <<EOT
+module top(input i, output o);
+sub s0(i, o);
+endmodule
+EOT
+
+techmap -map %techmap
+select -assert-any w:s0.asdf
-- 
cgit v1.2.3


From a4f2f7d23cb27f7677236d7a1823f36215c874e9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 2 Oct 2019 12:43:18 -0700
Subject: Extend test with renaming cells with prefix too

---
 tests/techmap/techmap_replace.ys | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'tests')

diff --git a/tests/techmap/techmap_replace.ys b/tests/techmap/techmap_replace.ys
index ee5c6bc7e..c2f42d50b 100644
--- a/tests/techmap/techmap_replace.ys
+++ b/tests/techmap/techmap_replace.ys
@@ -2,6 +2,7 @@ read_verilog <<EOT
 module sub(input i, output o, input j);
 foobar _TECHMAP_REPLACE_(i, o, j);
 wire _TECHMAP_REPLACE_.asdf = i ;
+barfoo _TECHMAP_REPLACE_.blah (i, o, j);
 endmodule
 EOT
 design -stash techmap
@@ -14,3 +15,4 @@ EOT
 
 techmap -map %techmap
 select -assert-any w:s0.asdf
+select -assert-any c:s0.blah
-- 
cgit v1.2.3


From c28d4b804720c2cf0086e921748219150e9631b5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 2 Oct 2019 14:52:40 -0700
Subject: Add test that is expecting to fail

---
 tests/sat/initval.ys | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

(limited to 'tests')

diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys
index 2079d2f34..1627a37e3 100644
--- a/tests/sat/initval.ys
+++ b/tests/sat/initval.ys
@@ -2,3 +2,23 @@ read_verilog -sv initval.v
 proc;;
 
 sat -seq 10 -prove-asserts
+
+read_verilog <<EOT
+module gold(input clk, input i, output reg [1:0] o);
+initial o = 2'b10;
+always @(posedge clk)
+   o[0] <= {i,i};
+endmodule
+
+module gate(input clk, input i, output reg [1:0] o);
+initial o = 2'b10;
+always @(posedge clk)
+   o[0] <= i;
+always @*
+   o[1] <= o[0];
+endmodule
+EOT
+
+proc
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -seq 1 -falsify -prove-asserts -show-ports miter
-- 
cgit v1.2.3


From e730a595eeee1d9936a892c2477c99593d64bcfe Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 2 Oct 2019 17:48:55 -0700
Subject: Add test

---
 tests/various/peepopt.ys | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

(limited to 'tests')

diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys
index 6bca62e2b..dc0acf3ca 100644
--- a/tests/various/peepopt.ys
+++ b/tests/various/peepopt.ys
@@ -173,3 +173,34 @@ select -assert-count 1 t:$dff r:WIDTH=2 %i
 select -assert-count 2 t:$mux
 select -assert-count 2 t:$mux r:WIDTH=2 %i
 select -assert-count 0 t:$logic_not t:$dff t:$mux %% t:* %D
+
+####################
+
+design -reset
+read_verilog <<EOT
+module peepopt_dffmuxext_signed_rst_init(input clk, ce, rstn, input signed [1:0] i, output reg signed [3:0] o);
+    initial o <= 4'b0010;
+    always @(posedge clk) begin
+        if (ce) o <= i;
+        if (!rstn) o <= 4'b1111;
+    end
+endmodule
+EOT
+
+proc
+#equiv_opt -assert peepopt
+
+design -save gold
+peepopt
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -seq 1 -verify -prove-asserts -show-ports miter
+
+design -load postopt
+wreduce
+select -assert-count 1 t:$dff r:WIDTH=2 %i
+select -assert-count 2 t:$mux
+select -assert-count 2 t:$mux r:WIDTH=2 %i
+select -assert-count 0 t:$logic_not t:$dff t:$mux %% t:* %D
-- 
cgit v1.2.3


From f6fabc8fda1eb00b0227f1a91d85b837a0609728 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 2 Oct 2019 18:03:45 -0700
Subject: Update test

---
 tests/various/peepopt.ys | 16 +++-------------
 1 file changed, 3 insertions(+), 13 deletions(-)

(limited to 'tests')

diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys
index dc0acf3ca..734a22408 100644
--- a/tests/various/peepopt.ys
+++ b/tests/various/peepopt.ys
@@ -188,19 +188,9 @@ endmodule
 EOT
 
 proc
-#equiv_opt -assert peepopt
-
-design -save gold
-peepopt
-design -stash gate
-design -import gold -as gold
-design -import gate -as gate
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -seq 1 -verify -prove-asserts -show-ports miter
-
+equiv_opt -assert peepopt
 design -load postopt
-wreduce
-select -assert-count 1 t:$dff r:WIDTH=2 %i
+select -assert-count 1 t:$dff r:WIDTH=4 %i
 select -assert-count 2 t:$mux
-select -assert-count 2 t:$mux r:WIDTH=2 %i
+select -assert-count 2 t:$mux r:WIDTH=4 %i
 select -assert-count 0 t:$logic_not t:$dff t:$mux %% t:* %D
-- 
cgit v1.2.3


From e4bd5aaebf7e329236b10c93eac9ad113231f00e Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 2 Oct 2019 18:12:25 -0700
Subject: Fix test

---
 tests/various/peepopt.ys | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys
index 734a22408..1f18f1c74 100644
--- a/tests/various/peepopt.ys
+++ b/tests/various/peepopt.ys
@@ -188,8 +188,18 @@ endmodule
 EOT
 
 proc
-equiv_opt -assert peepopt
-design -load postopt
+#equiv_opt -assert peepopt
+
+design -save gold
+peepopt
+wreduce
+design -stash gate
+design -import gold -as gold
+design -import gate -as gate
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -seq 1 -verify -prove-asserts -show-ports miter
+
+design -load gate
 select -assert-count 1 t:$dff r:WIDTH=4 %i
 select -assert-count 2 t:$mux
 select -assert-count 2 t:$mux r:WIDTH=4 %i
-- 
cgit v1.2.3


From e9645c7fa7fc349afad103ff8736699bb4dc0412 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 2 Oct 2019 21:26:26 -0700
Subject: Fix broken CI, check reset even for constants, trim rstmux

---
 tests/various/peepopt.ys | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys
index 1f18f1c74..4b130578b 100644
--- a/tests/various/peepopt.ys
+++ b/tests/various/peepopt.ys
@@ -131,8 +131,8 @@ EOT
 proc
 equiv_opt -assert peepopt
 design -load postopt
-select -assert-count 1 t:$dff r:WIDTH=5 %i
-select -assert-count 1 t:$mux r:WIDTH=5 %i
+select -assert-count 1 t:$dff r:WIDTH=4 %i
+select -assert-count 1 t:$mux r:WIDTH=4 %i
 select -assert-count 0 t:$dff t:$mux %% t:* %D
 
 ####################
-- 
cgit v1.2.3


From f6b5e47e40b4a2bda6e5d928480ea218a6a911c2 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Thu, 19 Sep 2019 20:43:13 +0100
Subject: sv: Switch parser to glr, prep for typedef

Signed-off-by: David Shah <dave@ds0.me>
---
 tests/svtypes/typedef1.sv | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 tests/svtypes/typedef1.sv

(limited to 'tests')

diff --git a/tests/svtypes/typedef1.sv b/tests/svtypes/typedef1.sv
new file mode 100644
index 000000000..9e5d02364
--- /dev/null
+++ b/tests/svtypes/typedef1.sv
@@ -0,0 +1,22 @@
+`define STRINGIFY(x) `"x`"
+`define STATIC_ASSERT(x) if(!(x)) $error({"assert failed: ", `STRINGIFY(x)})
+
+module top;
+
+	typedef logic [1:0] uint2_t;
+	typedef logic signed [3:0] int4_t;
+	typedef logic signed [7:0] int8_t;
+	typedef int8_t char_t;
+
+	(* keep *) uint2_t int2 = 2'b10;
+	(* keep *) int4_t int4 = -1;
+	(* keep *) int8_t int8 = int4;
+	(* keep *) char_t ch = int8;
+
+
+	always @* assert(int2 == 2'b10);
+	always @* assert(int4 == 4'b1111);
+	always @* assert(int8 == 8'b11111111);
+	always @* assert(ch   == 8'b11111111);
+
+endmodule
\ No newline at end of file
-- 
cgit v1.2.3


From c9629516120930aedaf52d72fec5d7fabe51d496 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Thu, 19 Sep 2019 21:07:20 +0100
Subject: sv: Fix typedef parameters

Signed-off-by: David Shah <dave@ds0.me>
---
 tests/svtypes/typedef1.sv       | 22 ----------------------
 tests/svtypes/typedef_param.sv  | 22 ++++++++++++++++++++++
 tests/svtypes/typedef_simple.sv | 19 +++++++++++++++++++
 3 files changed, 41 insertions(+), 22 deletions(-)
 delete mode 100644 tests/svtypes/typedef1.sv
 create mode 100644 tests/svtypes/typedef_param.sv
 create mode 100644 tests/svtypes/typedef_simple.sv

(limited to 'tests')

diff --git a/tests/svtypes/typedef1.sv b/tests/svtypes/typedef1.sv
deleted file mode 100644
index 9e5d02364..000000000
--- a/tests/svtypes/typedef1.sv
+++ /dev/null
@@ -1,22 +0,0 @@
-`define STRINGIFY(x) `"x`"
-`define STATIC_ASSERT(x) if(!(x)) $error({"assert failed: ", `STRINGIFY(x)})
-
-module top;
-
-	typedef logic [1:0] uint2_t;
-	typedef logic signed [3:0] int4_t;
-	typedef logic signed [7:0] int8_t;
-	typedef int8_t char_t;
-
-	(* keep *) uint2_t int2 = 2'b10;
-	(* keep *) int4_t int4 = -1;
-	(* keep *) int8_t int8 = int4;
-	(* keep *) char_t ch = int8;
-
-
-	always @* assert(int2 == 2'b10);
-	always @* assert(int4 == 4'b1111);
-	always @* assert(int8 == 8'b11111111);
-	always @* assert(ch   == 8'b11111111);
-
-endmodule
\ No newline at end of file
diff --git a/tests/svtypes/typedef_param.sv b/tests/svtypes/typedef_param.sv
new file mode 100644
index 000000000..13a522f19
--- /dev/null
+++ b/tests/svtypes/typedef_param.sv
@@ -0,0 +1,22 @@
+`define STRINGIFY(x) `"x`"
+`define STATIC_ASSERT(x) if(!(x)) $error({"assert failed: ", `STRINGIFY(x)})
+
+module top;
+
+	typedef logic [1:0] uint2_t;
+	typedef logic signed [3:0] int4_t;
+	typedef logic signed [7:0] int8_t;
+	typedef int8_t char_t;
+
+	parameter uint2_t int2 = 2'b10;
+	localparam int4_t int4 = -1;
+	localparam int8_t int8 = int4;
+	localparam char_t ch = int8;
+
+
+	`STATIC_ASSERT(int2 == 2'b10);
+	`STATIC_ASSERT(int4 == 4'b1111);
+	`STATIC_ASSERT(int8 == 8'b11111111);
+	`STATIC_ASSERT(ch   == 8'b11111111);
+
+endmodule
\ No newline at end of file
diff --git a/tests/svtypes/typedef_simple.sv b/tests/svtypes/typedef_simple.sv
new file mode 100644
index 000000000..0cf2c072c
--- /dev/null
+++ b/tests/svtypes/typedef_simple.sv
@@ -0,0 +1,19 @@
+module top;
+
+	typedef logic [1:0] uint2_t;
+	typedef logic signed [3:0] int4_t;
+	typedef logic signed [7:0] int8_t;
+	typedef int8_t char_t;
+
+	(* keep *) uint2_t int2 = 2'b10;
+	(* keep *) int4_t int4 = -1;
+	(* keep *) int8_t int8 = int4;
+	(* keep *) char_t ch = int8;
+
+
+	always @* assert(int2 == 2'b10);
+	always @* assert(int4 == 4'b1111);
+	always @* assert(int8 == 8'b11111111);
+	always @* assert(ch   == 8'b11111111);
+
+endmodule
\ No newline at end of file
-- 
cgit v1.2.3


From e70e4afb60a41da6d9f6200b20f36f61c6b993b2 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Thu, 19 Sep 2019 21:21:21 +0100
Subject: sv: Fix typedefs in packages

Signed-off-by: David Shah <dave@ds0.me>
---
 tests/svtypes/typedef_package.sv | 11 +++++++++++
 1 file changed, 11 insertions(+)
 create mode 100644 tests/svtypes/typedef_package.sv

(limited to 'tests')

diff --git a/tests/svtypes/typedef_package.sv b/tests/svtypes/typedef_package.sv
new file mode 100644
index 000000000..4aa22b6af
--- /dev/null
+++ b/tests/svtypes/typedef_package.sv
@@ -0,0 +1,11 @@
+package pkg;
+	typedef logic [7:0] uint8_t;
+endpackage
+
+module top;
+
+	(* keep *) pkg::uint8_t a = 8'hAA;
+
+	always @* assert(a == 8'hAA);
+
+endmodule
\ No newline at end of file
-- 
cgit v1.2.3


From 30d23260309ef392a0e69fe5294c38b71ad0692e Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 20 Sep 2019 11:39:15 +0100
Subject: sv: Add support for memory typedefs

Signed-off-by: David Shah <dave@ds0.me>
---
 tests/svtypes/typedef_memory.sv | 10 ++++++++++
 1 file changed, 10 insertions(+)
 create mode 100644 tests/svtypes/typedef_memory.sv

(limited to 'tests')

diff --git a/tests/svtypes/typedef_memory.sv b/tests/svtypes/typedef_memory.sv
new file mode 100644
index 000000000..c848c3287
--- /dev/null
+++ b/tests/svtypes/typedef_memory.sv
@@ -0,0 +1,10 @@
+module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata);
+	typedef logic [3:0] ram16x4_t[0:15];
+
+	ram16x4_t mem;
+
+	always @(posedge clk) begin
+		if (wen) mem[addr] <= wdata;
+		rdata <= mem[addr];
+	end
+endmodule
\ No newline at end of file
-- 
cgit v1.2.3


From af25585170f87506bcc7dbe5afe0fec868290d5b Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 20 Sep 2019 11:46:37 +0100
Subject: sv: Add support for memories of a typedef

Signed-off-by: David Shah <dave@ds0.me>
---
 tests/svtypes/typedef_memory_2.sv | 10 ++++++++++
 1 file changed, 10 insertions(+)
 create mode 100644 tests/svtypes/typedef_memory_2.sv

(limited to 'tests')

diff --git a/tests/svtypes/typedef_memory_2.sv b/tests/svtypes/typedef_memory_2.sv
new file mode 100644
index 000000000..1e8abb155
--- /dev/null
+++ b/tests/svtypes/typedef_memory_2.sv
@@ -0,0 +1,10 @@
+module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata);
+	typedef logic [3:0] nibble;
+
+	nibble mem[0:15];
+
+	always @(posedge clk) begin
+		if (wen) mem[addr] <= wdata;
+		rdata <= mem[addr];
+	end
+endmodule
\ No newline at end of file
-- 
cgit v1.2.3


From abc155715dbe8db5ee95707f7c243f23954ca139 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 20 Sep 2019 13:00:26 +0100
Subject: sv: Add test scripts for typedefs

Signed-off-by: David Shah <dave@ds0.me>
---
 tests/svtypes/.gitignore          |  3 +++
 tests/svtypes/run-test.sh         | 20 ++++++++++++++++++++
 tests/svtypes/typedef_memory.ys   |  3 +++
 tests/svtypes/typedef_memory_2.ys |  4 ++++
 4 files changed, 30 insertions(+)
 create mode 100644 tests/svtypes/.gitignore
 create mode 100755 tests/svtypes/run-test.sh
 create mode 100644 tests/svtypes/typedef_memory.ys
 create mode 100644 tests/svtypes/typedef_memory_2.ys

(limited to 'tests')

diff --git a/tests/svtypes/.gitignore b/tests/svtypes/.gitignore
new file mode 100644
index 000000000..b48f808a1
--- /dev/null
+++ b/tests/svtypes/.gitignore
@@ -0,0 +1,3 @@
+/*.log
+/*.out
+/run-test.mk
diff --git a/tests/svtypes/run-test.sh b/tests/svtypes/run-test.sh
new file mode 100755
index 000000000..09a30eed1
--- /dev/null
+++ b/tests/svtypes/run-test.sh
@@ -0,0 +1,20 @@
+#!/usr/bin/env bash
+set -e
+{
+echo "all::"
+for x in *.ys; do
+	echo "all:: run-$x"
+	echo "run-$x:"
+	echo "	@echo 'Running $x..'"
+	echo "	@../../yosys -ql ${x%.ys}.log $x"
+done
+for x in *.sv; do
+	if [ ! -f "${x%.sv}.ys"  ]; then
+		echo "all:: check-$x"
+		echo "check-$x:"
+		echo "	@echo 'Checking $x..'"
+		echo "	@../../yosys -ql ${x%.sv}.log -p \"prep -top top; sat -verify -prove-asserts\" $x"
+	fi
+done
+} > run-test.mk
+exec ${MAKE:-make} -f run-test.mk
diff --git a/tests/svtypes/typedef_memory.ys b/tests/svtypes/typedef_memory.ys
new file mode 100644
index 000000000..bc1127dc5
--- /dev/null
+++ b/tests/svtypes/typedef_memory.ys
@@ -0,0 +1,3 @@
+read -sv typedef_memory.sv
+prep -top top
+select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i
\ No newline at end of file
diff --git a/tests/svtypes/typedef_memory_2.ys b/tests/svtypes/typedef_memory_2.ys
new file mode 100644
index 000000000..571e28914
--- /dev/null
+++ b/tests/svtypes/typedef_memory_2.ys
@@ -0,0 +1,4 @@
+read -sv typedef_memory_2.sv
+prep -top top
+dump
+select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i
\ No newline at end of file
-- 
cgit v1.2.3


From 9b9d24f15b1b91b64b97e12bd05693f4539762d9 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 20 Sep 2019 18:40:35 +0100
Subject: sv: Improve tests

Signed-off-by: David Shah <dave@ds0.me>
---
 tests/svtypes/typedef_memory.sv   |  2 +-
 tests/svtypes/typedef_memory.ys   |  2 +-
 tests/svtypes/typedef_memory_2.sv |  2 +-
 tests/svtypes/typedef_memory_2.ys |  2 +-
 tests/svtypes/typedef_package.sv  |  2 +-
 tests/svtypes/typedef_param.sv    |  2 +-
 tests/svtypes/typedef_scopes.sv   | 23 +++++++++++++++++++++++
 tests/svtypes/typedef_simple.sv   |  2 +-
 8 files changed, 30 insertions(+), 7 deletions(-)
 create mode 100644 tests/svtypes/typedef_scopes.sv

(limited to 'tests')

diff --git a/tests/svtypes/typedef_memory.sv b/tests/svtypes/typedef_memory.sv
index c848c3287..37e63c1d0 100644
--- a/tests/svtypes/typedef_memory.sv
+++ b/tests/svtypes/typedef_memory.sv
@@ -7,4 +7,4 @@ module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata);
 		if (wen) mem[addr] <= wdata;
 		rdata <= mem[addr];
 	end
-endmodule
\ No newline at end of file
+endmodule
diff --git a/tests/svtypes/typedef_memory.ys b/tests/svtypes/typedef_memory.ys
index bc1127dc5..d0b8cf5bf 100644
--- a/tests/svtypes/typedef_memory.ys
+++ b/tests/svtypes/typedef_memory.ys
@@ -1,3 +1,3 @@
 read -sv typedef_memory.sv
 prep -top top
-select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i
\ No newline at end of file
+select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i
diff --git a/tests/svtypes/typedef_memory_2.sv b/tests/svtypes/typedef_memory_2.sv
index 1e8abb155..6d65131db 100644
--- a/tests/svtypes/typedef_memory_2.sv
+++ b/tests/svtypes/typedef_memory_2.sv
@@ -7,4 +7,4 @@ module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata);
 		if (wen) mem[addr] <= wdata;
 		rdata <= mem[addr];
 	end
-endmodule
\ No newline at end of file
+endmodule
diff --git a/tests/svtypes/typedef_memory_2.ys b/tests/svtypes/typedef_memory_2.ys
index 571e28914..0997beeea 100644
--- a/tests/svtypes/typedef_memory_2.ys
+++ b/tests/svtypes/typedef_memory_2.ys
@@ -1,4 +1,4 @@
 read -sv typedef_memory_2.sv
 prep -top top
 dump
-select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i
\ No newline at end of file
+select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i
diff --git a/tests/svtypes/typedef_package.sv b/tests/svtypes/typedef_package.sv
index 4aa22b6af..bee88b7ae 100644
--- a/tests/svtypes/typedef_package.sv
+++ b/tests/svtypes/typedef_package.sv
@@ -8,4 +8,4 @@ module top;
 
 	always @* assert(a == 8'hAA);
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/tests/svtypes/typedef_param.sv b/tests/svtypes/typedef_param.sv
index 13a522f19..d838dd828 100644
--- a/tests/svtypes/typedef_param.sv
+++ b/tests/svtypes/typedef_param.sv
@@ -19,4 +19,4 @@ module top;
 	`STATIC_ASSERT(int8 == 8'b11111111);
 	`STATIC_ASSERT(ch   == 8'b11111111);
 
-endmodule
\ No newline at end of file
+endmodule
diff --git a/tests/svtypes/typedef_scopes.sv b/tests/svtypes/typedef_scopes.sv
new file mode 100644
index 000000000..340defbbb
--- /dev/null
+++ b/tests/svtypes/typedef_scopes.sv
@@ -0,0 +1,23 @@
+
+typedef logic [3:0] outer_uint4_t;
+
+module top;
+
+	outer_uint4_t u4_i = 8'hA5;
+	always @(*) assert(u4_i == 4'h5);
+
+	typedef logic [3:0] inner_type;
+	inner_type inner_i1 = 8'h5A;
+	always @(*) assert(inner_i1 == 4'hA);
+
+	if (1) begin: genblock
+		typedef logic [7:0] inner_type;
+		inner_type inner_gb_i = 8'hA5;
+		always @(*) assert(inner_gb_i == 8'hA5);
+	end
+
+	inner_type inner_i2 = 8'h42;
+	always @(*) assert(inner_i2 == 4'h2);
+
+
+endmodule
diff --git a/tests/svtypes/typedef_simple.sv b/tests/svtypes/typedef_simple.sv
index 0cf2c072c..8f89910e5 100644
--- a/tests/svtypes/typedef_simple.sv
+++ b/tests/svtypes/typedef_simple.sv
@@ -16,4 +16,4 @@ module top;
 	always @* assert(int8 == 8'b11111111);
 	always @* assert(ch   == 8'b11111111);
 
-endmodule
\ No newline at end of file
+endmodule
-- 
cgit v1.2.3


From 5d680590d6bccd929ed3909248dbb73fb3876e65 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 3 Oct 2019 10:30:33 -0700
Subject: Use equiv_opt -async2sync for xilinx

---
 tests/xilinx/latches.ys | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

(limited to 'tests')

diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys
index ac1102896..bd1dffd21 100644
--- a/tests/xilinx/latches.ys
+++ b/tests/xilinx/latches.ys
@@ -2,9 +2,7 @@ read_verilog latches.v
 
 proc
 flatten
-equiv_opt -assert -run :prove -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-async2sync
-equiv_opt -assert -run prove: -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 
 design -load preopt
 synth_xilinx
-- 
cgit v1.2.3


From bd5889640bbcbb11c80360893fcf17d9399cef8a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 3 Oct 2019 10:45:53 -0700
Subject: Disable equiv check for ice40 latches

---
 tests/ice40/latches.ys | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

(limited to 'tests')

diff --git a/tests/ice40/latches.ys b/tests/ice40/latches.ys
index f3562559e..708734e44 100644
--- a/tests/ice40/latches.ys
+++ b/tests/ice40/latches.ys
@@ -1,14 +1,11 @@
 read_verilog latches.v
-design -save read
 
 proc
-async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock
 flatten
-synth_ice40
-equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+# Can't run any sort of equivalence check because latches are blown to LUTs
+#equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
 
-design -load read
+#design -load preopt
 synth_ice40
 cd top
 select -assert-count 4 t:SB_LUT4
-- 
cgit v1.2.3


From 045f34403889b69f3ac3ac08d96e5cf1fae787d1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 3 Oct 2019 11:11:50 -0700
Subject: Use `sat -tempinduct` and comments for why equiv_opt not sufficient

---
 tests/various/peepopt.ys | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys
index 4b130578b..ee5ad8a1a 100644
--- a/tests/various/peepopt.ys
+++ b/tests/various/peepopt.ys
@@ -188,6 +188,13 @@ endmodule
 EOT
 
 proc
+# NB: equiv_opt uses equiv_induct which covers
+#     only the induction half of temporal induction
+#     --- missing the base-case half
+#     This makes it akin to `sat -tempinduct-inductonly`
+#     instead of `sat -tempinduct-baseonly` or
+#     `sat -tempinduct` which is necessary for this
+#     testcase
 #equiv_opt -assert peepopt
 
 design -save gold
@@ -197,7 +204,7 @@ design -stash gate
 design -import gold -as gold
 design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -seq 1 -verify -prove-asserts -show-ports miter
+sat -tempinduct -verify -prove-asserts -show-ports miter
 
 design -load gate
 select -assert-count 1 t:$dff r:WIDTH=4 %i
-- 
cgit v1.2.3


From 5c68da4150f8e5367138f2c7187f707b20cc19db Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 5 Oct 2019 09:27:12 -0700
Subject: Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf

---
 tests/ice40/wrapcarry.ys | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 tests/ice40/wrapcarry.ys

(limited to 'tests')

diff --git a/tests/ice40/wrapcarry.ys b/tests/ice40/wrapcarry.ys
new file mode 100644
index 000000000..10c029e68
--- /dev/null
+++ b/tests/ice40/wrapcarry.ys
@@ -0,0 +1,22 @@
+read_verilog <<EOT
+module top(input A, B, CI, output O, CO);
+	SB_CARRY carry (
+		.I0(A),
+		.I1(B),
+		.CI(CI),
+		.CO(CO)
+	);
+	SB_LUT4 #(
+		.LUT_INIT(16'b 0110_1001_1001_0110)
+	) adder (
+		.I0(1'b0),
+		.I1(A),
+		.I2(B),
+		.I3(1'b0),
+		.O(O)
+	);
+endmodule
+EOT
+
+ice40_wrapcarry
+select -assert-count 1 t:$__ICE40_CARRY_WRAPPER
-- 
cgit v1.2.3


From 3fb604c75d3e8ee45d35fac8b787cb95a8adcf84 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 8 Oct 2019 12:41:26 -0700
Subject: Revert "Add test that is expecting to fail"

This reverts commit c28d4b804720c2cf0086e921748219150e9631b5.
---
 tests/sat/initval.ys | 20 --------------------
 1 file changed, 20 deletions(-)

(limited to 'tests')

diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys
index 1627a37e3..2079d2f34 100644
--- a/tests/sat/initval.ys
+++ b/tests/sat/initval.ys
@@ -2,23 +2,3 @@ read_verilog -sv initval.v
 proc;;
 
 sat -seq 10 -prove-asserts
-
-read_verilog <<EOT
-module gold(input clk, input i, output reg [1:0] o);
-initial o = 2'b10;
-always @(posedge clk)
-   o[0] <= {i,i};
-endmodule
-
-module gate(input clk, input i, output reg [1:0] o);
-initial o = 2'b10;
-always @(posedge clk)
-   o[0] <= i;
-always @*
-   o[1] <= o[0];
-endmodule
-EOT
-
-proc
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -seq 1 -falsify -prove-asserts -show-ports miter
-- 
cgit v1.2.3


From 2ae7dec5300bb61a90842fefb1e846cd9f667a9e Mon Sep 17 00:00:00 2001
From: SergeyDegtyar <sndegtyar@gmail.com>
Date: Mon, 9 Sep 2019 08:33:26 +0300
Subject: Add tests for Xilinx UG901 examples

---
 tests/xilinx_ug901/asym_ram_sdp_read_wider.v       |  74 +++++++++++++
 tests/xilinx_ug901/asym_ram_sdp_read_wider.ys      |  22 ++++
 tests/xilinx_ug901/asym_ram_sdp_write_wider.v      |  75 +++++++++++++
 tests/xilinx_ug901/asym_ram_sdp_write_wider.ys     |  31 ++++++
 tests/xilinx_ug901/asym_ram_tdp_read_first.v       |  85 ++++++++++++++
 tests/xilinx_ug901/asym_ram_tdp_read_first.ys      |  21 ++++
 tests/xilinx_ug901/asym_ram_tdp_write_first.v      |  92 ++++++++++++++++
 tests/xilinx_ug901/asym_ram_tdp_write_first.ys     |  29 +++++
 tests/xilinx_ug901/black_box_1.v                   |  19 ++++
 tests/xilinx_ug901/black_box_1.ys                  |  15 +++
 tests/xilinx_ug901/bytewrite_ram_1b.v              |  42 +++++++
 tests/xilinx_ug901/bytewrite_ram_1b.ys             |  22 ++++
 tests/xilinx_ug901/bytewrite_tdp_ram_nc.v          |  78 +++++++++++++
 tests/xilinx_ug901/bytewrite_tdp_ram_nc.ys         |  22 ++++
 tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.v  |  71 ++++++++++++
 tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.ys |  21 ++++
 tests/xilinx_ug901/bytewrite_tdp_ram_rf.v          |  61 +++++++++++
 tests/xilinx_ug901/bytewrite_tdp_ram_rf.ys         |  21 ++++
 tests/xilinx_ug901/bytewrite_tdp_ram_wf.v          |  68 ++++++++++++
 tests/xilinx_ug901/bytewrite_tdp_ram_wf.ys         |  23 ++++
 tests/xilinx_ug901/cmacc.v                         | 122 +++++++++++++++++++++
 tests/xilinx_ug901/cmacc.ys                        |  25 +++++
 tests/xilinx_ug901/cmult.v                         |  71 ++++++++++++
 tests/xilinx_ug901/cmult.ys                        |  31 ++++++
 tests/xilinx_ug901/dynamic_shift_registers_1.v     |  21 ++++
 tests/xilinx_ug901/dynamic_shift_registers_1.ys    |  15 +++
 tests/xilinx_ug901/dynpreaddmultadd.v              |  47 ++++++++
 tests/xilinx_ug901/dynpreaddmultadd.ys             |  31 ++++++
 tests/xilinx_ug901/fsm_1.v                         |  42 +++++++
 tests/xilinx_ug901/fsm_1.ys                        |  16 +++
 tests/xilinx_ug901/latches.v                       |  17 +++
 tests/xilinx_ug901/latches.ys                      |  10 ++
 tests/xilinx_ug901/macc.v                          |  47 ++++++++
 tests/xilinx_ug901/macc.ys                         |  23 ++++
 tests/xilinx_ug901/mult_unsigned.v                 |  33 ++++++
 tests/xilinx_ug901/mult_unsigned.ys                |  29 +++++
 tests/xilinx_ug901/presubmult.v                    |  43 ++++++++
 tests/xilinx_ug901/presubmult.ys                   |  23 ++++
 tests/xilinx_ug901/ram_simple_dual_one_clock.v     |  25 +++++
 tests/xilinx_ug901/ram_simple_dual_one_clock.ys    |  20 ++++
 tests/xilinx_ug901/ram_simple_dual_two_clocks.v    |  30 +++++
 tests/xilinx_ug901/ram_simple_dual_two_clocks.ys   |  20 ++++
 tests/xilinx_ug901/rams_dist.v                     |  24 ++++
 tests/xilinx_ug901/rams_dist.ys                    |  21 ++++
 tests/xilinx_ug901/rams_init_file.data             |  64 +++++++++++
 tests/xilinx_ug901/rams_init_file.v                |  24 ++++
 tests/xilinx_ug901/rams_init_file.ys               |  22 ++++
 tests/xilinx_ug901/rams_pipeline.v                 |  42 +++++++
 tests/xilinx_ug901/rams_pipeline.ys                |  22 ++++
 tests/xilinx_ug901/rams_sp_nc.v                    |  26 +++++
 tests/xilinx_ug901/rams_sp_nc.ys                   |  22 ++++
 tests/xilinx_ug901/rams_sp_rf.v                    |  26 +++++
 tests/xilinx_ug901/rams_sp_rf.ys                   |  22 ++++
 tests/xilinx_ug901/rams_sp_rf_rst.v                |  29 +++++
 tests/xilinx_ug901/rams_sp_rf_rst.ys               |  28 +++++
 tests/xilinx_ug901/rams_sp_rom.v                   |  46 ++++++++
 tests/xilinx_ug901/rams_sp_rom.ys                  |  22 ++++
 tests/xilinx_ug901/rams_sp_rom_1.v                 |  53 +++++++++
 tests/xilinx_ug901/rams_sp_rom_1.ys                |  22 ++++
 tests/xilinx_ug901/rams_sp_wf.v                    |  26 +++++
 tests/xilinx_ug901/rams_sp_wf.ys                   |  26 +++++
 tests/xilinx_ug901/rams_tdp_rf_rf.v                |  33 ++++++
 tests/xilinx_ug901/rams_tdp_rf_rf.ys               |  21 ++++
 tests/xilinx_ug901/registers_1.v                   |  25 +++++
 tests/xilinx_ug901/registers_1.ys                  |  12 ++
 tests/xilinx_ug901/run-test.sh                     |  20 ++++
 tests/xilinx_ug901/sfir_shifter.v                  |  19 ++++
 tests/xilinx_ug901/sfir_shifter.ys                 |  16 +++
 tests/xilinx_ug901/shift_registers_0.v             |  22 ++++
 tests/xilinx_ug901/shift_registers_0.ys            |  13 +++
 tests/xilinx_ug901/shift_registers_1.v             |  24 ++++
 tests/xilinx_ug901/shift_registers_1.ys            |  14 +++
 tests/xilinx_ug901/squarediffmacc.v                |  52 +++++++++
 tests/xilinx_ug901/squarediffmacc.ys               |  23 ++++
 tests/xilinx_ug901/squarediffmult.v                |  42 +++++++
 tests/xilinx_ug901/squarediffmult.ys               |  30 +++++
 tests/xilinx_ug901/top_mux.v                       |  18 +++
 tests/xilinx_ug901/top_mux.ys                      |  13 +++
 tests/xilinx_ug901/tristates_1.v                   |  17 +++
 tests/xilinx_ug901/tristates_1.ys                  |  13 +++
 tests/xilinx_ug901/tristates_2.v                   |  10 ++
 tests/xilinx_ug901/tristates_2.ys                  |  13 +++
 .../xilinx_ultraram_single_port_no_change.v        |  78 +++++++++++++
 .../xilinx_ultraram_single_port_no_change.ys       |  25 +++++
 .../xilinx_ultraram_single_port_read_first.v       |  78 +++++++++++++
 .../xilinx_ultraram_single_port_read_first.ys      |  24 ++++
 .../xilinx_ultraram_single_port_write_first.v      |  82 ++++++++++++++
 .../xilinx_ultraram_single_port_write_first.ys     |  24 ++++
 88 files changed, 2961 insertions(+)
 create mode 100644 tests/xilinx_ug901/asym_ram_sdp_read_wider.v
 create mode 100644 tests/xilinx_ug901/asym_ram_sdp_read_wider.ys
 create mode 100644 tests/xilinx_ug901/asym_ram_sdp_write_wider.v
 create mode 100644 tests/xilinx_ug901/asym_ram_sdp_write_wider.ys
 create mode 100644 tests/xilinx_ug901/asym_ram_tdp_read_first.v
 create mode 100644 tests/xilinx_ug901/asym_ram_tdp_read_first.ys
 create mode 100644 tests/xilinx_ug901/asym_ram_tdp_write_first.v
 create mode 100644 tests/xilinx_ug901/asym_ram_tdp_write_first.ys
 create mode 100644 tests/xilinx_ug901/black_box_1.v
 create mode 100644 tests/xilinx_ug901/black_box_1.ys
 create mode 100644 tests/xilinx_ug901/bytewrite_ram_1b.v
 create mode 100644 tests/xilinx_ug901/bytewrite_ram_1b.ys
 create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_nc.v
 create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_nc.ys
 create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.v
 create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.ys
 create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_rf.v
 create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_rf.ys
 create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_wf.v
 create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_wf.ys
 create mode 100644 tests/xilinx_ug901/cmacc.v
 create mode 100644 tests/xilinx_ug901/cmacc.ys
 create mode 100644 tests/xilinx_ug901/cmult.v
 create mode 100644 tests/xilinx_ug901/cmult.ys
 create mode 100644 tests/xilinx_ug901/dynamic_shift_registers_1.v
 create mode 100644 tests/xilinx_ug901/dynamic_shift_registers_1.ys
 create mode 100644 tests/xilinx_ug901/dynpreaddmultadd.v
 create mode 100644 tests/xilinx_ug901/dynpreaddmultadd.ys
 create mode 100644 tests/xilinx_ug901/fsm_1.v
 create mode 100644 tests/xilinx_ug901/fsm_1.ys
 create mode 100644 tests/xilinx_ug901/latches.v
 create mode 100644 tests/xilinx_ug901/latches.ys
 create mode 100644 tests/xilinx_ug901/macc.v
 create mode 100644 tests/xilinx_ug901/macc.ys
 create mode 100644 tests/xilinx_ug901/mult_unsigned.v
 create mode 100644 tests/xilinx_ug901/mult_unsigned.ys
 create mode 100644 tests/xilinx_ug901/presubmult.v
 create mode 100644 tests/xilinx_ug901/presubmult.ys
 create mode 100644 tests/xilinx_ug901/ram_simple_dual_one_clock.v
 create mode 100644 tests/xilinx_ug901/ram_simple_dual_one_clock.ys
 create mode 100644 tests/xilinx_ug901/ram_simple_dual_two_clocks.v
 create mode 100644 tests/xilinx_ug901/ram_simple_dual_two_clocks.ys
 create mode 100644 tests/xilinx_ug901/rams_dist.v
 create mode 100644 tests/xilinx_ug901/rams_dist.ys
 create mode 100644 tests/xilinx_ug901/rams_init_file.data
 create mode 100644 tests/xilinx_ug901/rams_init_file.v
 create mode 100644 tests/xilinx_ug901/rams_init_file.ys
 create mode 100644 tests/xilinx_ug901/rams_pipeline.v
 create mode 100644 tests/xilinx_ug901/rams_pipeline.ys
 create mode 100644 tests/xilinx_ug901/rams_sp_nc.v
 create mode 100644 tests/xilinx_ug901/rams_sp_nc.ys
 create mode 100644 tests/xilinx_ug901/rams_sp_rf.v
 create mode 100644 tests/xilinx_ug901/rams_sp_rf.ys
 create mode 100644 tests/xilinx_ug901/rams_sp_rf_rst.v
 create mode 100644 tests/xilinx_ug901/rams_sp_rf_rst.ys
 create mode 100644 tests/xilinx_ug901/rams_sp_rom.v
 create mode 100644 tests/xilinx_ug901/rams_sp_rom.ys
 create mode 100644 tests/xilinx_ug901/rams_sp_rom_1.v
 create mode 100644 tests/xilinx_ug901/rams_sp_rom_1.ys
 create mode 100644 tests/xilinx_ug901/rams_sp_wf.v
 create mode 100644 tests/xilinx_ug901/rams_sp_wf.ys
 create mode 100644 tests/xilinx_ug901/rams_tdp_rf_rf.v
 create mode 100644 tests/xilinx_ug901/rams_tdp_rf_rf.ys
 create mode 100644 tests/xilinx_ug901/registers_1.v
 create mode 100644 tests/xilinx_ug901/registers_1.ys
 create mode 100755 tests/xilinx_ug901/run-test.sh
 create mode 100644 tests/xilinx_ug901/sfir_shifter.v
 create mode 100644 tests/xilinx_ug901/sfir_shifter.ys
 create mode 100644 tests/xilinx_ug901/shift_registers_0.v
 create mode 100644 tests/xilinx_ug901/shift_registers_0.ys
 create mode 100644 tests/xilinx_ug901/shift_registers_1.v
 create mode 100644 tests/xilinx_ug901/shift_registers_1.ys
 create mode 100644 tests/xilinx_ug901/squarediffmacc.v
 create mode 100644 tests/xilinx_ug901/squarediffmacc.ys
 create mode 100644 tests/xilinx_ug901/squarediffmult.v
 create mode 100644 tests/xilinx_ug901/squarediffmult.ys
 create mode 100644 tests/xilinx_ug901/top_mux.v
 create mode 100644 tests/xilinx_ug901/top_mux.ys
 create mode 100644 tests/xilinx_ug901/tristates_1.v
 create mode 100644 tests/xilinx_ug901/tristates_1.ys
 create mode 100644 tests/xilinx_ug901/tristates_2.v
 create mode 100644 tests/xilinx_ug901/tristates_2.ys
 create mode 100644 tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.v
 create mode 100644 tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.ys
 create mode 100644 tests/xilinx_ug901/xilinx_ultraram_single_port_read_first.v
 create mode 100644 tests/xilinx_ug901/xilinx_ultraram_single_port_read_first.ys
 create mode 100644 tests/xilinx_ug901/xilinx_ultraram_single_port_write_first.v
 create mode 100644 tests/xilinx_ug901/xilinx_ultraram_single_port_write_first.ys

(limited to 'tests')

diff --git a/tests/xilinx_ug901/asym_ram_sdp_read_wider.v b/tests/xilinx_ug901/asym_ram_sdp_read_wider.v
new file mode 100644
index 000000000..0716dffdc
--- /dev/null
+++ b/tests/xilinx_ug901/asym_ram_sdp_read_wider.v
@@ -0,0 +1,74 @@
+// Asymmetric port RAM
+// Read Wider than Write. Read Statement in loop
+//asym_ram_sdp_read_wider.v
+
+module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA, doB);
+parameter WIDTHA = 4;
+parameter SIZEA = 1024;
+parameter ADDRWIDTHA = 10;
+
+parameter WIDTHB = 16;
+parameter SIZEB = 256;
+parameter ADDRWIDTHB = 8;
+input clkA;
+input clkB;
+input weA;
+input enaA, enaB;
+input [ADDRWIDTHA-1:0] addrA;
+input [ADDRWIDTHB-1:0] addrB;
+input [WIDTHA-1:0] diA;
+output [WIDTHB-1:0] doB;
+`define max(a,b) {(a) > (b) ? (a) : (b)}
+`define min(a,b) {(a) < (b) ? (a) : (b)}
+
+function integer log2;
+input integer value;
+reg [31:0] shifted;
+integer res;
+begin
+ if (value < 2)
+  log2 = value;
+ else
+ begin
+  shifted = value-1;
+  for (res=0; shifted>0; res=res+1)
+   shifted = shifted>>1;
+  log2 = res;
+ end
+end
+endfunction
+
+localparam maxSIZE = `max(SIZEA, SIZEB);
+localparam maxWIDTH = `max(WIDTHA, WIDTHB);
+localparam minWIDTH = `min(WIDTHA, WIDTHB);
+
+localparam RATIO = maxWIDTH / minWIDTH;
+localparam log2RATIO = log2(RATIO);
+
+reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
+reg [WIDTHB-1:0] readB;
+
+always @(posedge clkA)
+begin
+ if (enaA) begin 
+  if (weA)
+   RAM[addrA] <= diA;
+ end  
+end
+
+
+always @(posedge clkB)
+begin : ramread
+ integer i;
+ reg [log2RATIO-1:0] lsbaddr;
+ if (enaB) begin
+  for (i = 0; i < RATIO; i = i+1) begin 
+   lsbaddr = i;
+   readB[(i+1)*minWIDTH-1 -: minWIDTH] <= RAM[{addrB, lsbaddr}];
+  end
+ end
+end
+assign doB = readB;
+
+endmodule
+
diff --git a/tests/xilinx_ug901/asym_ram_sdp_read_wider.ys b/tests/xilinx_ug901/asym_ram_sdp_read_wider.ys
new file mode 100644
index 000000000..c63157cdf
--- /dev/null
+++ b/tests/xilinx_ug901/asym_ram_sdp_read_wider.ys
@@ -0,0 +1,22 @@
+read_verilog asym_ram_sdp_read_wider.v
+hierarchy -top asym_ram_sdp_read_wider
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+memory
+opt -full
+
+# TODO
+#equiv_opt -run prove: -assert null
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+
+design -load postopt
+cd asym_ram_sdp_read_wider
+stat
+#Vivado synthesizes 1 RAMB18E1.
+select -assert-count 2 t:BUFG
+select -assert-count 1 t:LUT2
+select -assert-count 4 t:RAMB18E1
+
+select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
diff --git a/tests/xilinx_ug901/asym_ram_sdp_write_wider.v b/tests/xilinx_ug901/asym_ram_sdp_write_wider.v
new file mode 100644
index 000000000..22d12d2ce
--- /dev/null
+++ b/tests/xilinx_ug901/asym_ram_sdp_write_wider.v
@@ -0,0 +1,75 @@
+// Asymmetric port RAM
+// Write wider than Read. Write Statement in a loop.
+// asym_ram_sdp_write_wider.v
+
+module asym_ram_sdp_write_wider (clkA, clkB, weA, enaA, enaB, addrA, addrB, diA, doB);
+parameter WIDTHB = 4;
+//Default parameters were changed because of slow test
+//parameter SIZEB = 1024;
+//parameter ADDRWIDTHB = 10;
+parameter SIZEB = 256;
+parameter ADDRWIDTHB = 8;
+
+//parameter WIDTHA = 16;
+parameter WIDTHA = 8;
+parameter SIZEA = 256;
+parameter ADDRWIDTHA = 8;
+input clkA;
+input clkB;
+input weA;
+input enaA, enaB;
+input [ADDRWIDTHA-1:0] addrA;
+input [ADDRWIDTHB-1:0] addrB;
+input [WIDTHA-1:0] diA;
+output [WIDTHB-1:0] doB;
+`define max(a,b) {(a) > (b) ? (a) : (b)}
+`define min(a,b) {(a) < (b) ? (a) : (b)}
+
+function integer log2;
+input integer value;
+reg [31:0] shifted;
+integer res;
+begin
+ if (value < 2)
+  log2 = value;
+ else
+ begin
+  shifted = value-1;
+  for (res=0; shifted>0; res=res+1)
+   shifted = shifted>>1;
+  log2 = res;
+ end
+end
+endfunction
+
+localparam maxSIZE = `max(SIZEA, SIZEB);
+localparam maxWIDTH = `max(WIDTHA, WIDTHB);
+localparam minWIDTH = `min(WIDTHA, WIDTHB);
+
+localparam RATIO = maxWIDTH / minWIDTH;
+localparam log2RATIO = log2(RATIO);
+
+reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
+reg [WIDTHB-1:0] readB;
+
+always @(posedge clkB) begin
+ if (enaB) begin
+  readB <= RAM[addrB];
+ end
+end
+assign doB = readB;
+
+always @(posedge clkA)
+begin : ramwrite
+ integer i;
+ reg [log2RATIO-1:0] lsbaddr;
+ for (i=0; i< RATIO; i= i+ 1) begin : write1
+  lsbaddr = i;
+  if (enaA) begin
+   if (weA)
+    RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH];
+  end
+ end
+end
+
+endmodule
diff --git a/tests/xilinx_ug901/asym_ram_sdp_write_wider.ys b/tests/xilinx_ug901/asym_ram_sdp_write_wider.ys
new file mode 100644
index 000000000..229d98df6
--- /dev/null
+++ b/tests/xilinx_ug901/asym_ram_sdp_write_wider.ys
@@ -0,0 +1,31 @@
+read_verilog asym_ram_sdp_write_wider.v
+hierarchy -top asym_ram_sdp_write_wider
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+memory
+opt -full
+
+# TODO
+#equiv_opt -run prove: -assert null
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+
+design -load postopt
+cd asym_ram_sdp_write_wider
+stat
+#Vivado synthesizes 1 RAMB18E1.
+select -assert-count 2 t:BUFG
+select -assert-count 1028 t:FDRE
+select -assert-count 170 t:LUT2
+select -assert-count 6 t:LUT3
+select -assert-count 518 t:LUT4
+select -assert-count 10 t:LUT5
+select -assert-count 484 t:LUT6
+select -assert-count 157 t:MUXF7
+select -assert-count 3 t:MUXF8
+
+#RRAM128X1D will be synthesized in case when the parameter WIDTHA=4
+#select -assert-count 8 t:RAM128X1D
+
+select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D
diff --git a/tests/xilinx_ug901/asym_ram_tdp_read_first.v b/tests/xilinx_ug901/asym_ram_tdp_read_first.v
new file mode 100644
index 000000000..2b807a382
--- /dev/null
+++ b/tests/xilinx_ug901/asym_ram_tdp_read_first.v
@@ -0,0 +1,85 @@
+// Asymetric RAM - TDP  
+// READ_FIRST MODE.
+// asym_ram_tdp_read_first.v
+
+
+module asym_ram_tdp_read_first (clkA, clkB, enaA, weA, enaB, weB, addrA, addrB, diA, doA, diB, doB);
+parameter WIDTHB = 4;
+parameter SIZEB = 1024;
+parameter ADDRWIDTHB = 10;
+parameter WIDTHA = 16;
+parameter SIZEA = 256;
+parameter ADDRWIDTHA = 8;
+input clkA;
+input clkB;
+input weA, weB;
+input enaA, enaB;
+
+input [ADDRWIDTHA-1:0] addrA;
+input [ADDRWIDTHB-1:0] addrB;
+input [WIDTHA-1:0] diA;
+input [WIDTHB-1:0] diB;
+
+output [WIDTHA-1:0] doA;
+output [WIDTHB-1:0] doB;
+
+`define max(a,b) {(a) > (b) ? (a) : (b)}
+`define min(a,b) {(a) < (b) ? (a) : (b)}
+
+function integer log2;
+input integer value;
+reg [31:0] shifted;
+integer res;
+begin
+ if (value < 2)
+  log2 = value;
+ else
+ begin
+  shifted = value-1;
+  for (res=0; shifted>0; res=res+1)
+   shifted = shifted>>1;
+  log2 = res;
+ end
+end
+endfunction
+
+localparam maxSIZE = `max(SIZEA, SIZEB);
+localparam maxWIDTH = `max(WIDTHA, WIDTHB);
+localparam minWIDTH = `min(WIDTHA, WIDTHB);
+
+localparam RATIO = maxWIDTH / minWIDTH;
+localparam log2RATIO = log2(RATIO);
+
+reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
+reg [WIDTHA-1:0] readA;
+reg [WIDTHB-1:0] readB;
+
+always @(posedge clkB)
+begin
+ if (enaB) begin
+  readB <= RAM[addrB] ;
+  if (weB)
+   RAM[addrB] <= diB;
+ end  
+end
+
+
+always @(posedge clkA)
+begin : portA
+ integer i;
+ reg [log2RATIO-1:0] lsbaddr ;
+  for (i=0; i< RATIO; i= i+ 1) begin 
+   lsbaddr = i;
+  if (enaA) begin
+   readA[(i+1)*minWIDTH -1 -: minWIDTH] <= RAM[{addrA, lsbaddr}];
+
+   if (weA)
+    RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH];
+  end
+ end
+end
+
+assign doA = readA;
+assign doB = readB;
+
+endmodule
diff --git a/tests/xilinx_ug901/asym_ram_tdp_read_first.ys b/tests/xilinx_ug901/asym_ram_tdp_read_first.ys
new file mode 100644
index 000000000..5f96b800c
--- /dev/null
+++ b/tests/xilinx_ug901/asym_ram_tdp_read_first.ys
@@ -0,0 +1,21 @@
+read_verilog asym_ram_tdp_read_first.v
+hierarchy -top asym_ram_tdp_read_first
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+memory
+opt -full
+
+# TODO
+#equiv_opt -run prove: -assert null
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+
+design -load postopt
+cd asym_ram_tdp_read_first
+stat
+#Vivado synthesizes 1 RAMB18E1.
+select -assert-count 1 t:$mem
+select -assert-count 2 t:LUT2
+
+select -assert-none t:$mem t:LUT2 %% t:* %D
diff --git a/tests/xilinx_ug901/asym_ram_tdp_write_first.v b/tests/xilinx_ug901/asym_ram_tdp_write_first.v
new file mode 100644
index 000000000..90187ea26
--- /dev/null
+++ b/tests/xilinx_ug901/asym_ram_tdp_write_first.v
@@ -0,0 +1,92 @@
+// Asymmetric port RAM - TDP
+// WRITE_FIRST MODE.
+// asym_ram_tdp_write_first.v
+
+
+module asym_ram_tdp_write_first (clkA, clkB, enaA, weA, enaB, weB, addrA, addrB, diA, doA, diB, doB);
+parameter WIDTHB = 4;
+//Default parameters were changed because of slow test
+//parameter SIZEB = 1024;
+//parameter ADDRWIDTHB = 10;
+parameter SIZEB = 32;
+parameter ADDRWIDTHB = 8;
+
+//parameter WIDTHA = 16;
+parameter WIDTHA = 4;
+//parameter SIZEA = 256;
+parameter SIZEA = 32;
+parameter ADDRWIDTHA = 8;
+input clkA;
+input clkB;
+input weA, weB;
+input enaA, enaB;
+
+input [ADDRWIDTHA-1:0] addrA;
+input [ADDRWIDTHB-1:0] addrB;
+input [WIDTHA-1:0] diA;
+input [WIDTHB-1:0] diB;
+
+output [WIDTHA-1:0] doA;
+output [WIDTHB-1:0] doB;
+
+`define max(a,b) {(a) > (b) ? (a) : (b)}
+`define min(a,b) {(a) < (b) ? (a) : (b)}
+
+function integer log2;
+input integer value;
+reg [31:0] shifted;
+integer res;
+begin
+ if (value < 2)
+  log2 = value;
+ else
+ begin
+  shifted = value-1;
+  for (res=0; shifted>0; res=res+1)
+   shifted = shifted>>1;
+  log2 = res;
+ end
+end
+endfunction
+
+localparam maxSIZE = `max(SIZEA, SIZEB);
+localparam maxWIDTH = `max(WIDTHA, WIDTHB);
+localparam minWIDTH = `min(WIDTHA, WIDTHB);
+
+localparam RATIO = maxWIDTH / minWIDTH;
+localparam log2RATIO = log2(RATIO);
+
+reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
+reg [WIDTHA-1:0] readA;
+reg [WIDTHB-1:0] readB;
+
+always @(posedge clkB)
+begin
+ if (enaB) begin
+  if (weB)
+   RAM[addrB] = diB;
+  readB = RAM[addrB] ;
+ end
+end
+
+
+always @(posedge clkA)
+begin : portA
+ integer i;
+ reg [log2RATIO-1:0] lsbaddr ;
+  for (i=0; i< RATIO; i= i+ 1) begin
+   lsbaddr = i;
+   if (enaA) begin
+
+   if (weA)
+    RAM[{addrA, lsbaddr}] = diA[(i+1)*minWIDTH-1 -: minWIDTH];
+
+   readA[(i+1)*minWIDTH -1 -: minWIDTH] = RAM[{addrA, lsbaddr}];
+  end
+ end
+end
+
+assign doA = readA;
+assign doB = readB;
+
+endmodule
diff --git a/tests/xilinx_ug901/asym_ram_tdp_write_first.ys b/tests/xilinx_ug901/asym_ram_tdp_write_first.ys
new file mode 100644
index 000000000..bbe3cc849
--- /dev/null
+++ b/tests/xilinx_ug901/asym_ram_tdp_write_first.ys
@@ -0,0 +1,29 @@
+read_verilog asym_ram_tdp_write_first.v
+hierarchy -top asym_ram_tdp_write_first
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+memory
+opt -full
+
+# TODO
+#equiv_opt -run prove: -assert null
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+
+design -load postopt
+cd asym_ram_tdp_write_first
+stat
+#Vivado synthesizes 1 RAMB18E1.
+select -assert-count 2 t:BUFG
+select -assert-count 200 t:FDRE
+select -assert-count 10 t:LUT2
+select -assert-count 44 t:LUT3
+select -assert-count 81 t:LUT4
+select -assert-count 104 t:LUT5
+select -assert-count 560 t:LUT6
+select -assert-count 261 t:MUXF7
+select -assert-count 127 t:MUXF8
+
+
+select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D
diff --git a/tests/xilinx_ug901/black_box_1.v b/tests/xilinx_ug901/black_box_1.v
new file mode 100644
index 000000000..40caa1b10
--- /dev/null
+++ b/tests/xilinx_ug901/black_box_1.v
@@ -0,0 +1,19 @@
+// Black Box
+// black_box_1.v
+// 
+(* black_box *) module black_box1 (in1, in2, dout);
+input in1, in2;
+output dout;
+endmodule
+
+module black_box_1 (DI_1, DI_2, DOUT);
+input DI_1, DI_2;
+output DOUT;
+
+black_box1 U1 (
+                .in1(DI_1),
+                .in2(DI_2),
+                .dout(DOUT)
+              );
+
+endmodule
diff --git a/tests/xilinx_ug901/black_box_1.ys b/tests/xilinx_ug901/black_box_1.ys
new file mode 100644
index 000000000..acf0b5761
--- /dev/null
+++ b/tests/xilinx_ug901/black_box_1.ys
@@ -0,0 +1,15 @@
+read_verilog black_box_1.v
+hierarchy -top black_box_1
+proc
+tribuf
+flatten
+synth
+#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd black_box_1 # Constrain all select calls below inside the top module
+#Vivado synthesizes 1 black box.
+#stat
+#select -assert-count 0 t:LUT1
+#select -assert-count 1 t:$_TBUF_
+#select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D
diff --git a/tests/xilinx_ug901/bytewrite_ram_1b.v b/tests/xilinx_ug901/bytewrite_ram_1b.v
new file mode 100644
index 000000000..46d86c297
--- /dev/null
+++ b/tests/xilinx_ug901/bytewrite_ram_1b.v
@@ -0,0 +1,42 @@
+// Single-Port BRAM with Byte-wide Write Enable
+// Read-First mode
+// Single-process description
+// Compact description of the write with a generate-for 
+//   statement
+// Column width and number of columns easily configurable
+//
+// bytewrite_ram_1b.v
+//
+
+module bytewrite_ram_1b (clk, we, addr, di, do);
+
+parameter SIZE = 1024; 
+parameter ADDR_WIDTH = 10; 
+parameter COL_WIDTH = 8; 
+parameter NB_COL = 4;
+
+input clk;
+input [NB_COL-1:0] we;
+input [ADDR_WIDTH-1:0] addr;
+input [NB_COL*COL_WIDTH-1:0] di;
+output reg [NB_COL*COL_WIDTH-1:0] do;
+
+reg [NB_COL*COL_WIDTH-1:0] RAM [SIZE-1:0];
+
+always @(posedge clk)
+begin
+    do <= RAM[addr];
+end
+
+generate genvar i;
+for (i = 0; i < NB_COL; i = i+1)
+begin
+always @(posedge clk)
+begin
+    if (we[i])
+        RAM[addr][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= di[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
+    end 
+end
+endgenerate
+
+endmodule
diff --git a/tests/xilinx_ug901/bytewrite_ram_1b.ys b/tests/xilinx_ug901/bytewrite_ram_1b.ys
new file mode 100644
index 000000000..4f0967801
--- /dev/null
+++ b/tests/xilinx_ug901/bytewrite_ram_1b.ys
@@ -0,0 +1,22 @@
+read_verilog bytewrite_ram_1b.v
+hierarchy -top bytewrite_ram_1b
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+memory
+opt -full
+
+# TODO
+#equiv_opt -run prove: -assert null
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+
+design -load postopt
+cd bytewrite_ram_1b
+stat
+#Vivado synthesizes 1 RAMB36E1.
+select -assert-count 1 t:BUFG
+select -assert-count 32 t:LUT2
+select -assert-count 8 t:RAMB36E1
+
+select -assert-none t:BUFG t:LUT2 t:RAMB36E1 %% t:* %D
diff --git a/tests/xilinx_ug901/bytewrite_tdp_ram_nc.v b/tests/xilinx_ug901/bytewrite_tdp_ram_nc.v
new file mode 100644
index 000000000..1093b0838
--- /dev/null
+++ b/tests/xilinx_ug901/bytewrite_tdp_ram_nc.v
@@ -0,0 +1,78 @@
+//
+// True-Dual-Port BRAM with Byte-wide Write Enable
+//      No-Change mode
+//
+// bytewrite_tdp_ram_nc.v
+//
+// ByteWide Write Enable, - NO_CHANGE mode template - Vivado recomended
+module bytewrite_tdp_ram_nc
+  #(
+    //---------------------------------------------------------------
+    parameter   NUM_COL                 =   4,
+    parameter   COL_WIDTH               =   8,
+    parameter   ADDR_WIDTH              =  10, // Addr  Width in bits : 2**ADDR_WIDTH = RAM Depth
+    parameter   DATA_WIDTH              =  NUM_COL*COL_WIDTH  // Data  Width in bits
+    //---------------------------------------------------------------
+    ) (
+       input clkA,
+       input enaA, 
+       input [NUM_COL-1:0] weA,
+       input [ADDR_WIDTH-1:0] addrA,
+       input [DATA_WIDTH-1:0] dinA,
+       output reg [DATA_WIDTH-1:0] doutA,
+       
+       input clkB,
+       input enaB,
+       input [NUM_COL-1:0] weB,
+       input [ADDR_WIDTH-1:0] addrB,
+       input [DATA_WIDTH-1:0] dinB,
+       output reg [DATA_WIDTH-1:0] doutB
+       );
+
+   
+   // Core Memory  
+   reg [DATA_WIDTH-1:0]            ram_block [(2**ADDR_WIDTH)-1:0];
+   
+   // Port-A Operation
+   generate
+      genvar                       i;
+      for(i=0;i<NUM_COL;i=i+1) begin
+         always @ (posedge clkA) begin
+            if(enaA) begin
+               if(weA[i]) begin
+                  ram_block[addrA][i*COL_WIDTH +: COL_WIDTH] <= dinA[i*COL_WIDTH +: COL_WIDTH];
+               end
+            end
+         end
+      end
+   endgenerate
+   
+   always @ (posedge clkA) begin
+      if(enaA) begin
+         if (~|weA)
+           doutA <= ram_block[addrA];
+      end
+   end
+   
+   
+   // Port-B Operation:
+   generate
+      for(i=0;i<NUM_COL;i=i+1) begin
+         always @ (posedge clkB) begin
+            if(enaB) begin
+               if(weB[i]) begin
+                  ram_block[addrB][i*COL_WIDTH +: COL_WIDTH] <= dinB[i*COL_WIDTH +: COL_WIDTH];
+               end
+            end
+         end
+      end
+   endgenerate
+   
+   always @ (posedge clkB) begin
+      if(enaB) begin
+         if (~|weB)
+           doutB <= ram_block[addrB];
+      end
+   end
+   
+endmodule // bytewrite_tdp_ram_nc
diff --git a/tests/xilinx_ug901/bytewrite_tdp_ram_nc.ys b/tests/xilinx_ug901/bytewrite_tdp_ram_nc.ys
new file mode 100644
index 000000000..b6818e322
--- /dev/null
+++ b/tests/xilinx_ug901/bytewrite_tdp_ram_nc.ys
@@ -0,0 +1,22 @@
+read_verilog bytewrite_tdp_ram_nc.v
+hierarchy -top bytewrite_tdp_ram_nc
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+memory
+opt -full
+
+# TODO
+#equiv_opt -run prove: -assert null
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+
+design -load postopt
+cd bytewrite_tdp_ram_nc
+stat
+#Vivado synthesizes 1 RAMB36E1.
+select -assert-count 1 t:$mem
+select -assert-count 8 t:LUT2
+select -assert-count 64 t:LUT3
+select -assert-count 2 t:LUT5
+select -assert-none t:LUT2 t:LUT3 t:LUT5 t:$mem %% t:* %D
diff --git a/tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.v b/tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.v
new file mode 100644
index 000000000..349aa2aec
--- /dev/null
+++ b/tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.v
@@ -0,0 +1,71 @@
+// ByteWide Write Enable, - Alternate READ_FIRST mode template - Vivado recomended
+// bytewrite_tdp_ram_readfirst2.v
+module bytewrite_tdp_ram_readfirst2
+  #(
+    //-------------------------------------------------------------------------
+    parameter   NUM_COL                 =   4,
+    parameter   COL_WIDTH               =   8,
+    parameter   ADDR_WIDTH              =  10, // Addr  Width in bits : 2**ADDR_WIDTH = RAM Depth
+    parameter   DATA_WIDTH              =  NUM_COL*COL_WIDTH  // Data  Width in bits
+    //-------------------------------------------------------------------------
+    ) (
+       input clkA,
+       input enaA, 
+       input [NUM_COL-1:0] weA,
+       input [ADDR_WIDTH-1:0] addrA,
+       input [DATA_WIDTH-1:0] dinA,
+       output reg [DATA_WIDTH-1:0] doutA,
+       
+       input clkB,
+       input enaB,
+       input [NUM_COL-1:0] weB,
+       input [ADDR_WIDTH-1:0] addrB,
+       input [DATA_WIDTH-1:0] dinB,
+       output reg [DATA_WIDTH-1:0] doutB
+       );
+   
+   
+   // Core Memory  
+   reg [DATA_WIDTH-1:0]            ram_block [(2**ADDR_WIDTH)-1:0];
+   
+   // Port-A Operation
+   generate
+      genvar                       i;
+      for(i=0;i<NUM_COL;i=i+1) begin
+         always @ (posedge clkA) begin
+            if(enaA) begin
+               if(weA[i]) begin
+                  ram_block[addrA][i*COL_WIDTH +: COL_WIDTH] <= dinA[i*COL_WIDTH +: COL_WIDTH];
+               end
+            end
+         end
+      end
+   endgenerate
+   
+   always @ (posedge clkA) begin
+      if(enaA) begin
+         doutA <= ram_block[addrA];
+      end
+   end
+   
+   
+   // Port-B Operation:
+   generate
+      for(i=0;i<NUM_COL;i=i+1) begin
+         always @ (posedge clkB) begin
+            if(enaB) begin
+               if(weB[i]) begin
+                  ram_block[addrB][i*COL_WIDTH +: COL_WIDTH] <= dinB[i*COL_WIDTH +: COL_WIDTH];
+               end
+            end
+         end
+      end
+   endgenerate
+   
+   always @ (posedge clkB) begin
+      if(enaB) begin
+         doutB <= ram_block[addrB];
+      end
+   end
+
+endmodule // bytewrite_tdp_ram_readfirst2
diff --git a/tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.ys b/tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.ys
new file mode 100644
index 000000000..3273d0d43
--- /dev/null
+++ b/tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.ys
@@ -0,0 +1,21 @@
+read_verilog bytewrite_tdp_ram_readfirst2.v
+hierarchy -top bytewrite_tdp_ram_readfirst2
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+memory
+opt -full
+
+# TODO
+#equiv_opt -run prove: -assert null
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+
+design -load postopt
+cd bytewrite_tdp_ram_readfirst2
+stat
+#Vivado synthesizes 1 RAMB36E1.
+select -assert-count 1 t:$mem
+select -assert-count 8 t:LUT2
+select -assert-count 64 t:LUT3
+select -assert-none t:LUT2 t:LUT3 t:$mem %% t:* %D
diff --git a/tests/xilinx_ug901/bytewrite_tdp_ram_rf.v b/tests/xilinx_ug901/bytewrite_tdp_ram_rf.v
new file mode 100644
index 000000000..72dad9d8f
--- /dev/null
+++ b/tests/xilinx_ug901/bytewrite_tdp_ram_rf.v
@@ -0,0 +1,61 @@
+// True-Dual-Port BRAM with Byte-wide Write Enable
+//      Read-First mode 
+// bytewrite_tdp_ram_rf.v
+//
+
+module bytewrite_tdp_ram_rf
+ #(
+//--------------------------------------------------------------------------
+parameter   NUM_COL             =   4,
+parameter   COL_WIDTH           =   8,
+parameter   ADDR_WIDTH          =  10, 
+// Addr  Width in bits : 2 *ADDR_WIDTH = RAM Depth
+parameter   DATA_WIDTH      =  NUM_COL*COL_WIDTH  // Data  Width in bits
+    //----------------------------------------------------------------------
+  ) (
+     input clkA,
+     input enaA, 
+     input [NUM_COL-1:0] weA,
+     input [ADDR_WIDTH-1:0] addrA,
+     input [DATA_WIDTH-1:0] dinA,
+     output reg [DATA_WIDTH-1:0] doutA,
+
+     input clkB,
+     input enaB,
+     input [NUM_COL-1:0] weB,
+     input [ADDR_WIDTH-1:0] addrB,
+     input [DATA_WIDTH-1:0] dinB,
+     output reg [DATA_WIDTH-1:0] doutB
+     );
+
+
+   // Core Memory  
+   reg [DATA_WIDTH-1:0]   ram_block [(2**ADDR_WIDTH)-1:0];
+
+   integer                i;
+   // Port-A Operation
+   always @ (posedge clkA) begin
+      if(enaA) begin
+         for(i=0;i<NUM_COL;i=i+1) begin
+            if(weA[i]) begin
+               ram_block[addrA][i*COL_WIDTH +: COL_WIDTH] <= dinA[i*COL_WIDTH +: COL_WIDTH];
+            end
+         end
+         doutA <= ram_block[addrA];  
+      end
+   end
+
+   // Port-B Operation:
+   always @ (posedge clkB) begin
+      if(enaB) begin
+         for(i=0;i<NUM_COL;i=i+1) begin
+            if(weB[i]) begin
+               ram_block[addrB][i*COL_WIDTH +: COL_WIDTH] <= dinB[i*COL_WIDTH +: COL_WIDTH];
+            end
+         end     
+         
+         doutB <= ram_block[addrB];  
+      end
+   end
+
+endmodule // bytewrite_tdp_ram_rf
diff --git a/tests/xilinx_ug901/bytewrite_tdp_ram_rf.ys b/tests/xilinx_ug901/bytewrite_tdp_ram_rf.ys
new file mode 100644
index 000000000..2a34d9abe
--- /dev/null
+++ b/tests/xilinx_ug901/bytewrite_tdp_ram_rf.ys
@@ -0,0 +1,21 @@
+read_verilog bytewrite_tdp_ram_rf.v
+hierarchy -top bytewrite_tdp_ram_rf
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+memory
+opt -full
+
+# TODO
+#equiv_opt -run prove: -assert null
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+
+design -load postopt
+cd bytewrite_tdp_ram_rf
+stat
+#Vivado synthesizes 1 RAMB36E1.
+select -assert-count 1 t:$mem
+select -assert-count 8 t:LUT2
+select -assert-count 64 t:LUT3
+select -assert-none t:LUT2 t:LUT3 t:$mem %% t:* %D
diff --git a/tests/xilinx_ug901/bytewrite_tdp_ram_wf.v b/tests/xilinx_ug901/bytewrite_tdp_ram_wf.v
new file mode 100644
index 000000000..d39565e52
--- /dev/null
+++ b/tests/xilinx_ug901/bytewrite_tdp_ram_wf.v
@@ -0,0 +1,68 @@
+// True-Dual-Port BRAM with Byte-wide Write Enable
+//      Write-First mode
+// File: HDL_Coding_Techniques/rams/bytewrite_tdp_ram_wf.v
+//
+// ByteWide Write Enable, - WRITE_FIRST mode template - Vivado recomended
+module bytewrite_tdp_ram_wf
+  #(
+    //----------------------------------------------------------------------
+parameter   NUM_COL         =   4,
+parameter   COL_WIDTH       =   8,
+parameter   ADDR_WIDTH      =  10, 
+// Addr  Width in bits : 2**ADDR_WIDTH = RAM Depth
+parameter   DATA_WIDTH      =  NUM_COL*COL_WIDTH  // Data  Width in bits
+    //----------------------------------------------------------------------
+    ) (
+       input clkA,
+       input enaA, 
+       input [NUM_COL-1:0] weA,
+       input [ADDR_WIDTH-1:0] addrA,
+       input [DATA_WIDTH-1:0] dinA,
+       output reg [DATA_WIDTH-1:0] doutA,
+       
+       input clkB,
+       input enaB,
+       input [NUM_COL-1:0] weB,
+       input [ADDR_WIDTH-1:0] addrB,
+       input [DATA_WIDTH-1:0] dinB,
+       output reg [DATA_WIDTH-1:0] doutB
+       );
+   
+   
+   // Core Memory  
+   reg [DATA_WIDTH-1:0]            ram_block [(2**ADDR_WIDTH)-1:0];
+   
+   // Port-A Operation
+   generate
+      genvar                       i;
+      for(i=0;i<NUM_COL;i=i+1) begin
+         always @ (posedge clkA) begin
+            if(enaA) begin
+               if(weA[i]) begin
+                  ram_block[addrA][i*COL_WIDTH +: COL_WIDTH] <= dinA[i*COL_WIDTH +: COL_WIDTH];
+                  doutA[i*COL_WIDTH +: COL_WIDTH]  <= dinA[i*COL_WIDTH +: COL_WIDTH] ;
+               end else begin
+                  doutA[i*COL_WIDTH +: COL_WIDTH]  <= ram_block[addrA][i*COL_WIDTH +: COL_WIDTH] ;
+               end
+            end
+         end
+      end
+   endgenerate
+   
+   // Port-B Operation:
+   generate
+      for(i=0;i<NUM_COL;i=i+1) begin
+         always @ (posedge clkB) begin
+            if(enaB) begin
+               if(weB[i]) begin
+                  ram_block[addrB][i*COL_WIDTH +: COL_WIDTH] <= dinB[i*COL_WIDTH +: COL_WIDTH];
+                  doutB[i*COL_WIDTH +: COL_WIDTH]  <= dinB[i*COL_WIDTH +: COL_WIDTH] ;
+               end else begin 
+                  doutB[i*COL_WIDTH +: COL_WIDTH]  <= ram_block[addrB][i*COL_WIDTH +: COL_WIDTH] ;
+               end
+            end     
+         end
+      end
+   endgenerate
+   
+endmodule // bytewrite_tdp_ram_wf
diff --git a/tests/xilinx_ug901/bytewrite_tdp_ram_wf.ys b/tests/xilinx_ug901/bytewrite_tdp_ram_wf.ys
new file mode 100644
index 000000000..b681d0c2b
--- /dev/null
+++ b/tests/xilinx_ug901/bytewrite_tdp_ram_wf.ys
@@ -0,0 +1,23 @@
+read_verilog bytewrite_tdp_ram_wf.v
+hierarchy -top bytewrite_tdp_ram_wf
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+memory
+opt -full
+
+# TODO
+#equiv_opt -run prove: -assert null
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+
+design -load postopt
+cd bytewrite_tdp_ram_wf
+stat
+#Vivado synthesizes 1 RAMB36E1.
+select -assert-count 1 t:$mem
+select -assert-count 2 t:BUFG
+select -assert-count 64 t:FDRE
+select -assert-count 8 t:LUT2
+select -assert-count 128 t:LUT3
+select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:$mem %% t:* %D
diff --git a/tests/xilinx_ug901/cmacc.v b/tests/xilinx_ug901/cmacc.v
new file mode 100644
index 000000000..038402daf
--- /dev/null
+++ b/tests/xilinx_ug901/cmacc.v
@@ -0,0 +1,122 @@
+// Complex Multiplier with accumulation (pr+i.pi) = (ar+i.ai)*(br+i.bi)
+// File: cmacc.v
+// The RTL below describes a complex multiplier with accumulation
+// which can be packed into 3 DSP blocks (Ultrascale architecture)
+//Default parameters were changed because of slow test
+//module cmacc # (parameter AWIDTH = 16, BWIDTH = 18, SIZEOUT = 40)
+module cmacc # (parameter AWIDTH = 4, BWIDTH = 5, SIZEOUT = 9)
+  (
+   input clk,
+   input sload,
+   input signed [AWIDTH-1:0] ar,
+   input signed [AWIDTH-1:0] ai,
+  input signed [BWIDTH-1:0]   br,
+  input signed [BWIDTH-1:0]   bi,
+  output signed [SIZEOUT-1:0] pr,
+  output signed [SIZEOUT-1:0] pi);
+
+  reg signed [AWIDTH-1:0]  ai_d, ai_dd, ai_ddd, ai_dddd;
+  reg signed [AWIDTH-1:0] ar_d, ar_dd, ar_ddd, ar_dddd;
+  reg signed [BWIDTH-1:0] bi_d, bi_dd, bi_ddd, br_d, br_dd, br_ddd;
+  reg signed [AWIDTH:0] addcommon;
+  reg signed [BWIDTH:0] addr, addi;
+  reg signed [AWIDTH+BWIDTH:0] mult0, multr, multi;
+  reg signed [SIZEOUT-1:0] pr_int, pi_int, old_result_real, old_result_im;
+  reg signed [AWIDTH+BWIDTH:0] common, commonr1, commonr2;
+
+  reg sload_reg;
+
+ `ifdef SIM
+  initial
+  begin
+    ai_d = 0;
+    ai_dd = 0;
+    ai_ddd = 0;
+    ai_dddd = 0;
+    ar_d = 0;
+    ar_dd = 0;
+    ar_ddd = 0;
+    ar_dddd = 0;
+    bi_d = 0;
+    bi_dd = 0;
+    bi_ddd = 0;
+    br_d = 0;
+    br_dd = 0;
+    br_ddd = 0;
+  end
+ `endif
+
+  always @(posedge clk)
+  begin
+    ar_d      <= ar;
+    ar_dd     <= ar_d;
+    ai_d      <= ai;
+    ai_dd     <= ai_d;
+    br_d      <= br;
+    br_dd     <= br_d;
+    br_ddd    <= br_dd;
+    bi_d      <= bi;
+    bi_dd     <= bi_d;
+    bi_ddd    <= bi_dd;
+    sload_reg <= sload;
+  end
+
+  // Common factor (ar ai) x bi, shared for the calculations of the real and imaginary final products
+  //
+  always @(posedge clk)
+  begin
+    addcommon <= ar_d - ai_d;
+    mult0     <= addcommon * bi_dd;
+    common    <= mult0;
+  end
+
+  // Accumulation loop (combinatorial) for *Real*
+  //
+  always @(sload_reg or pr_int)
+  if (sload_reg)
+  old_result_real <= 0;
+  else
+  // 'sload' is now and opens the accumulation loop.
+  // The accumulator takes the next multiplier output
+  // in the same cycle.
+  old_result_real <= pr_int;
+
+  // Real product
+  //
+  always @(posedge clk)
+  begin
+    ar_ddd   <= ar_dd;
+    ar_dddd  <= ar_ddd;
+    addr     <= br_ddd - bi_ddd;
+    multr    <= addr * ar_dddd;
+    commonr1 <= common;
+    pr_int   <= multr + commonr1 + old_result_real;
+  end
+
+  // Accumulation loop (combinatorial) for *Imaginary*
+  //
+  always @(sload_reg or pi_int)
+  if (sload_reg)
+  old_result_im <= 0;
+  else
+  // 'sload' is now and opens the accumulation loop.
+  // The accumulator takes the next multiplier output
+  // in the same cycle.
+  old_result_im <= pi_int;
+
+  // Imaginary product
+  //
+  always @(posedge clk)
+  begin
+    ai_ddd   <= ai_dd;
+    ai_dddd  <= ai_ddd;
+    addi     <= br_ddd + bi_ddd;
+    multi    <= addi * ai_dddd;
+    commonr2 <= common;
+    pi_int   <= multi + commonr2 + old_result_im;
+  end
+
+  assign pr = pr_int;
+  assign pi = pi_int;
+
+endmodule // cmacc
diff --git a/tests/xilinx_ug901/cmacc.ys b/tests/xilinx_ug901/cmacc.ys
new file mode 100644
index 000000000..c1ac931c8
--- /dev/null
+++ b/tests/xilinx_ug901/cmacc.ys
@@ -0,0 +1,25 @@
+read_verilog cmacc.v
+hierarchy -top cmacc
+proc
+flatten
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+
+cd cmacc
+#Vivado synthesizes 5 DSP48E1, 32 FDRE, 18 LUT.
+stat
+select -assert-count 1 t:BUFG
+select -assert-count 77 t:FDRE
+select -assert-count 5 t:LUT1
+select -assert-count 46 t:LUT2
+select -assert-count 25 t:LUT3
+select -assert-count 8 t:LUT4
+select -assert-count 16 t:LUT5
+select -assert-count 85 t:LUT6
+select -assert-count 54 t:MUXCY
+select -assert-count 8 t:MUXF7
+select -assert-count 2 t:MUXF8
+select -assert-count 22 t:SRL16E
+select -assert-count 62 t:XORCY
+
+select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:SRL16E t:XORCY %% t:* %D
diff --git a/tests/xilinx_ug901/cmult.v b/tests/xilinx_ug901/cmult.v
new file mode 100644
index 000000000..d5d85a28c
--- /dev/null
+++ b/tests/xilinx_ug901/cmult.v
@@ -0,0 +1,71 @@
+//
+// Complex Multiplier (pr+i.pi) = (ar+i.ai)*(br+i.bi)
+// file: cmult.v
+
+module cmult # (parameter AWIDTH = 16, BWIDTH = 18)
+   (
+    input clk,
+    input signed [AWIDTH-1:0]      ar, ai,
+    input signed [BWIDTH-1:0]      br, bi,
+    output signed [AWIDTH+BWIDTH:0] pr, pi
+   );
+
+reg signed [AWIDTH-1:0] ai_d, ai_dd, ai_ddd, ai_dddd   ; 
+reg signed [AWIDTH-1:0] ar_d, ar_dd, ar_ddd, ar_dddd   ; 
+reg signed [BWIDTH-1:0] bi_d, bi_dd, bi_ddd, br_d, br_dd, br_ddd ; 
+reg signed [AWIDTH:0]  addcommon     ; 
+reg signed [BWIDTH:0]  addr, addi     ; 
+reg signed [AWIDTH+BWIDTH:0] mult0, multr, multi, pr_int, pi_int  ; 
+reg signed [AWIDTH+BWIDTH:0] common, commonr1, commonr2   ; 
+  
+always @(posedge clk)
+ begin
+  ar_d   <= ar;
+  ar_dd  <= ar_d;
+  ai_d   <= ai;
+  ai_dd  <= ai_d;
+  br_d   <= br;
+  br_dd  <= br_d;
+  br_ddd <= br_dd;
+  bi_d   <= bi;
+  bi_dd  <= bi_d;
+  bi_ddd <= bi_dd;
+ end
+ 
+// Common factor (ar ai) x bi, shared for the calculations of the real and imaginary final products
+// 
+always @(posedge clk)
+ begin
+  addcommon <= ar_d - ai_d;
+  mult0     <= addcommon * bi_dd;
+  common    <= mult0;
+ end
+
+// Real product
+//
+always @(posedge clk)
+ begin
+   ar_ddd   <= ar_dd;
+   ar_dddd  <= ar_ddd;
+   addr     <= br_ddd - bi_ddd;
+   multr    <= addr * ar_dddd;
+   commonr1 <= common;
+   pr_int   <= multr + commonr1;
+ end
+
+// Imaginary product
+//
+always @(posedge clk)
+ begin
+  ai_ddd   <= ai_dd;
+  ai_dddd  <= ai_ddd;
+  addi     <= br_ddd + bi_ddd;
+  multi    <= addi * ai_dddd;
+  commonr2 <= common;
+  pi_int   <= multi + commonr2;
+ end
+
+assign pr = pr_int;
+assign pi = pi_int;
+   
+endmodule // cmult
diff --git a/tests/xilinx_ug901/cmult.ys b/tests/xilinx_ug901/cmult.ys
new file mode 100644
index 000000000..605f00983
--- /dev/null
+++ b/tests/xilinx_ug901/cmult.ys
@@ -0,0 +1,31 @@
+read_verilog cmult.v
+hierarchy -top cmult
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+memory
+opt -full
+
+# TODO
+#equiv_opt -run prove: -assert null
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+
+design -load postopt
+cd cmult
+#Vivado synthesizes 3 DSP48E1, 68 FDRE.
+select -assert-count 1 t:BUFG
+select -assert-count 281 t:FDRE
+select -assert-count 18 t:LUT1
+select -assert-count 467 t:LUT2
+select -assert-count 187 t:LUT3
+select -assert-count 98 t:LUT4
+select -assert-count 165 t:LUT5
+select -assert-count 1596 t:LUT6
+select -assert-count 222 t:MUXCY
+select -assert-count 393 t:MUXF7
+select -assert-count 121 t:MUXF8
+select -assert-count 85 t:SRL16E
+select -assert-count 230 t:XORCY
+
+select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:SRL16E t:XORCY %% t:* %D
diff --git a/tests/xilinx_ug901/dynamic_shift_registers_1.v b/tests/xilinx_ug901/dynamic_shift_registers_1.v
new file mode 100644
index 000000000..b69c022cd
--- /dev/null
+++ b/tests/xilinx_ug901/dynamic_shift_registers_1.v
@@ -0,0 +1,21 @@
+// 32-bit dynamic shift register.
+// Download: 
+// File: dynamic_shift_registers_1.v
+
+module dynamic_shift_register_1 (CLK, CE, SEL, SI, DO);
+parameter SELWIDTH = 5;
+input CLK, CE, SI;
+input [SELWIDTH-1:0] SEL;
+output DO;
+
+localparam DATAWIDTH = 2**SELWIDTH;
+reg [DATAWIDTH-1:0] data;
+
+assign DO = data[SEL];
+
+always @(posedge CLK)
+ begin
+  if (CE == 1'b1)
+    data <= {data[DATAWIDTH-2:0], SI};
+  end 
+endmodule
diff --git a/tests/xilinx_ug901/dynamic_shift_registers_1.ys b/tests/xilinx_ug901/dynamic_shift_registers_1.ys
new file mode 100644
index 000000000..994e12a3e
--- /dev/null
+++ b/tests/xilinx_ug901/dynamic_shift_registers_1.ys
@@ -0,0 +1,15 @@
+read_verilog dynamic_shift_registers_1.v
+hierarchy -top dynamic_shift_register_1
+proc
+flatten
+
+#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dynamic_shift_register_1 # Constrain all select calls below inside the top module
+#Vivado synthesizes 1 BUFG, 3 SRLC32E.
+stat
+select -assert-count 1 t:BUFG
+select -assert-count 1 t:SRLC32E
+select -assert-none t:BUFG t:SRLC32E %% t:* %D
diff --git a/tests/xilinx_ug901/dynpreaddmultadd.v b/tests/xilinx_ug901/dynpreaddmultadd.v
new file mode 100644
index 000000000..e3bb3a86c
--- /dev/null
+++ b/tests/xilinx_ug901/dynpreaddmultadd.v
@@ -0,0 +1,47 @@
+// Pre-add/subtract select with Dynamic control
+// dynpreaddmultadd.v
+//Default parameters were changed because of slow test.
+//module dynpreaddmultadd  # (parameter SIZEIN = 16)
+module dynpreaddmultadd  # (parameter SIZEIN = 8)
+        (
+          input clk, ce, rst, subadd,
+          input  signed [SIZEIN-1:0] a, b, c, d,
+          output signed [2*SIZEIN:0] dynpreaddmultadd_out
+        );
+
+// Declare registers for intermediate values
+reg signed [SIZEIN-1:0] a_reg, b_reg, c_reg;
+reg signed [SIZEIN:0]   add_reg;
+reg signed [2*SIZEIN:0] d_reg, m_reg, p_reg;
+
+always @(posedge clk)
+begin
+ if (rst)
+  begin
+   a_reg   <= 0;
+   b_reg   <= 0;
+   c_reg   <= 0;
+   d_reg   <= 0;
+   add_reg <= 0;
+   m_reg   <= 0;
+   p_reg   <= 0;
+  end
+ else if (ce)
+  begin
+   a_reg   <= a;
+   b_reg   <= b;
+   c_reg   <= c;
+   d_reg   <= d;
+   if (subadd)
+    add_reg <= a_reg - b_reg;
+   else
+    add_reg <= a_reg + b_reg;
+   m_reg   <= add_reg * c_reg;
+   p_reg   <= m_reg + d_reg;
+  end
+end
+
+// Output accumulation result
+assign dynpreaddmultadd_out = p_reg;
+
+endmodule // dynpreaddmultadd
diff --git a/tests/xilinx_ug901/dynpreaddmultadd.ys b/tests/xilinx_ug901/dynpreaddmultadd.ys
new file mode 100644
index 000000000..f74128dae
--- /dev/null
+++ b/tests/xilinx_ug901/dynpreaddmultadd.ys
@@ -0,0 +1,31 @@
+read_verilog dynpreaddmultadd.v
+hierarchy -top dynpreaddmultadd
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+memory
+opt -full
+
+# TODO
+#equiv_opt -run prove: -assert null
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+
+design -load postopt
+cd dynpreaddmultadd
+
+#Vivado synthesizes 1 DSP48E1.
+select -assert-count 1 t:BUFG
+select -assert-count 75 t:FDRE
+select -assert-count 8 t:LUT1
+select -assert-count 131 t:LUT2
+select -assert-count 19 t:LUT3
+select -assert-count 26 t:LUT4
+select -assert-count 12 t:LUT5
+select -assert-count 142 t:LUT6
+select -assert-count 48 t:MUXCY
+select -assert-count 50 t:MUXF7
+select -assert-count 15 t:MUXF8
+select -assert-count 52 t:XORCY
+
+select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
diff --git a/tests/xilinx_ug901/fsm_1.v b/tests/xilinx_ug901/fsm_1.v
new file mode 100644
index 000000000..ee3571d0d
--- /dev/null
+++ b/tests/xilinx_ug901/fsm_1.v
@@ -0,0 +1,42 @@
+// State Machine with single sequential block
+//fsm_1.v
+module fsm_1(clk,reset,flag,sm_out);
+input clk,reset,flag;
+output reg sm_out;
+
+parameter s1 = 3'b000;
+parameter s2 = 3'b001;
+parameter s3 = 3'b010;
+parameter s4 = 3'b011;
+parameter s5 = 3'b111;
+
+reg [2:0] state;
+
+always@(posedge clk)
+  begin
+    if(reset)
+      begin
+        state <= s1;
+        sm_out  <= 1'b1;
+      end
+  else
+    begin
+     case(state)
+       s1: if(flag) 
+            begin 
+              state <= s2; 
+              sm_out <= 1'b1; 
+            end
+           else
+            begin
+              state <= s3;
+              sm_out <= 1'b0;
+            end
+       s2: begin state <= s4; sm_out <= 1'b0; end
+       s3: begin state <= s4; sm_out <= 1'b0; end
+       s4: begin state <= s5; sm_out <= 1'b1; end
+       s5: begin state <= s1; sm_out <= 1'b1; end
+     endcase
+    end
+ end
+endmodule
diff --git a/tests/xilinx_ug901/fsm_1.ys b/tests/xilinx_ug901/fsm_1.ys
new file mode 100644
index 000000000..192966163
--- /dev/null
+++ b/tests/xilinx_ug901/fsm_1.ys
@@ -0,0 +1,16 @@
+read_verilog fsm_1.v
+hierarchy -top fsm_1
+proc
+flatten
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd fsm_1 # Constrain all select calls below inside the top module
+#Vivado synthesizes 2 LUT5, 2 LUT4, 1 LUT3, 4 FDRE.
+stat
+select -assert-count 1 t:BUFG
+select -assert-count 4 t:FDRE
+select -assert-count 2 t:LUT4
+select -assert-count 2 t:LUT5
+select -assert-count 1 t:LUT6
+
+select -assert-none t:BUFG t:FDRE t:LUT4 t:LUT5 t:LUT6 %% t:* %D
diff --git a/tests/xilinx_ug901/latches.v b/tests/xilinx_ug901/latches.v
new file mode 100644
index 000000000..09d0f9f73
--- /dev/null
+++ b/tests/xilinx_ug901/latches.v
@@ -0,0 +1,17 @@
+// Latch with Positive Gate and Asynchronous Reset
+// File: latches.v
+module latches (
+                input G,
+                input D,
+                input CLR,
+                output reg Q
+               );
+always @ *
+begin
+ if(CLR)
+  Q = 0;
+ else if(G)
+  Q = D;
+end
+
+endmodule               
diff --git a/tests/xilinx_ug901/latches.ys b/tests/xilinx_ug901/latches.ys
new file mode 100644
index 000000000..be4a8de94
--- /dev/null
+++ b/tests/xilinx_ug901/latches.ys
@@ -0,0 +1,10 @@
+read_verilog latches.v
+proc
+hierarchy -top latches
+flatten
+synth_xilinx
+#Vivado synthesizes 1 BUFG, 8 LDCE.
+select -assert-count 2 t:LUT2
+select -assert-count 1 t:$_DLATCH_P_
+#ERROR: Assertion failed: selection is not empty: t:LUT2 t:$_DLATCH_P_ %% t:* %D
+#select -assert-none t:LUT2 t:$_DLATCH_P_ %% t:* %D
diff --git a/tests/xilinx_ug901/macc.v b/tests/xilinx_ug901/macc.v
new file mode 100644
index 000000000..9db8ea2c9
--- /dev/null
+++ b/tests/xilinx_ug901/macc.v
@@ -0,0 +1,47 @@
+// Signed 40-bit streaming accumulator with 16-bit inputs
+// File: macc.v
+//
+module macc  # (
+				//Default parameters were changed because of slow test
+               // parameter SIZEIN = 16, SIZEOUT = 40
+               // parameter SIZEIN = 12, SIZEOUT = 30
+                parameter SIZEIN = 8, SIZEOUT = 20
+               )
+               (
+                input clk, ce, sload,
+                input signed  [SIZEIN-1:0]  a, b,
+                output signed [SIZEOUT-1:0] accum_out
+               );
+
+   // Declare registers for intermediate values
+reg signed [SIZEIN-1:0]  a_reg, b_reg;
+reg                      sload_reg;
+reg signed [2*SIZEIN:0]  mult_reg;
+reg signed [SIZEOUT-1:0] adder_out, old_result;
+
+always @(adder_out or sload_reg)
+begin
+  if (sload_reg)
+    old_result <= 0;
+  else
+   // 'sload' is now active (=low) and opens the accumulation loop.
+   // The accumulator takes the next multiplier output in
+   // the same cycle.
+    old_result <= adder_out;
+end
+
+always @(posedge clk)
+ if (ce)
+   begin
+      a_reg <= a;
+      b_reg <= b;
+      mult_reg <= a_reg * b_reg;
+      sload_reg <= sload;
+      // Store accumulation result into a register
+      adder_out <= old_result + mult_reg;
+   end
+
+// Output accumulation result
+assign accum_out = adder_out;
+
+endmodule // macc
diff --git a/tests/xilinx_ug901/macc.ys b/tests/xilinx_ug901/macc.ys
new file mode 100644
index 000000000..5a78a352c
--- /dev/null
+++ b/tests/xilinx_ug901/macc.ys
@@ -0,0 +1,23 @@
+read_verilog macc.v
+hierarchy -top macc
+proc
+flatten
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+
+cd macc
+#Vivado synthesizes 1 DSP48E1, 1 FDRE. (When SIZEIN = 12, SIZEOUT = 30)
+stat
+select -assert-count 1 t:BUFG
+select -assert-count 53 t:FDRE
+select -assert-count 64 t:LUT2
+select -assert-count 10 t:LUT3
+select -assert-count 22 t:LUT4
+select -assert-count 14 t:LUT5
+select -assert-count 123 t:LUT6
+select -assert-count 34 t:MUXCY
+select -assert-count 41 t:MUXF7
+select -assert-count 14 t:MUXF8
+select -assert-count 36 t:XORCY
+
+select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
diff --git a/tests/xilinx_ug901/mult_unsigned.v b/tests/xilinx_ug901/mult_unsigned.v
new file mode 100644
index 000000000..466c16cf8
--- /dev/null
+++ b/tests/xilinx_ug901/mult_unsigned.v
@@ -0,0 +1,33 @@
+// Unsigned 16x24-bit Multiplier
+// 1 latency stage on operands
+// 3 latency stage after the multiplication
+// File: multipliers2.v
+//
+module mult_unsigned (clk, A, B, RES);
+//Default parameters were changed because of slow test
+//parameter WIDTHA = 16;
+//parameter WIDTHB = 24;
+parameter WIDTHA = 8;
+parameter WIDTHB = 12;
+input clk;
+input [WIDTHA-1:0] A;
+input [WIDTHB-1:0] B;
+output [WIDTHA+WIDTHB-1:0] RES;
+
+reg [WIDTHA-1:0] rA;
+reg [WIDTHB-1:0] rB;
+reg [WIDTHA+WIDTHB-1:0] M [3:0];
+
+integer i;
+always @(posedge clk)
+ begin
+  rA <= A;
+  rB <= B;
+  M[0] <= rA * rB;
+  for (i = 0; i < 3; i = i+1)
+    M[i+1] <= M[i];
+ end
+
+assign RES = M[3];
+
+endmodule
diff --git a/tests/xilinx_ug901/mult_unsigned.ys b/tests/xilinx_ug901/mult_unsigned.ys
new file mode 100644
index 000000000..a929ca3ad
--- /dev/null
+++ b/tests/xilinx_ug901/mult_unsigned.ys
@@ -0,0 +1,29 @@
+read_verilog mult_unsigned.v
+hierarchy -top mult_unsigned
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+memory
+opt -full
+
+# TODO
+#equiv_opt -run prove: -assert null
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+
+design -load postopt
+cd mult_unsigned
+
+#Vivado synthesizes 1 DSP48E1, 40 FDRE.
+select -assert-count 1 t:BUFG
+select -assert-count 20 t:FDRE
+select -assert-count 33 t:LUT2
+select -assert-count 1 t:LUT3
+select -assert-count 11 t:LUT4
+select -assert-count 4 t:LUT5
+select -assert-count 139 t:LUT6
+select -assert-count 19 t:MUXCY
+select -assert-count 35 t:MUXF7
+select -assert-count 20 t:SRL16E
+select -assert-count 20 t:XORCY
+select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:SRL16E t:XORCY %% t:* %D
diff --git a/tests/xilinx_ug901/presubmult.v b/tests/xilinx_ug901/presubmult.v
new file mode 100644
index 000000000..30e6133ff
--- /dev/null
+++ b/tests/xilinx_ug901/presubmult.v
@@ -0,0 +1,43 @@
+//
+// Pre-adder support in subtract mode for DSP block
+// File: presubmult.v
+
+module presubmult  # (//Default parameters were changed because of slow test
+					// parameter SIZEIN = 16
+                      parameter SIZEIN = 8
+                     )
+                     (
+                      input clk, ce, rst,
+                      input  signed [SIZEIN-1:0] a, b, c,
+                      output signed [2*SIZEIN:0] presubmult_out
+                     );
+
+// Declare registers for intermediate values
+reg signed [SIZEIN-1:0] a_reg, b_reg, c_reg;
+reg signed [SIZEIN:0]   add_reg;
+reg signed [2*SIZEIN:0] m_reg, p_reg;
+
+always @(posedge clk)
+ if (rst)
+  begin
+     a_reg   <= 0;
+     b_reg   <= 0;
+     c_reg   <= 0;
+     add_reg <= 0;
+     m_reg   <= 0;
+     p_reg   <= 0;
+  end
+ else if (ce)
+  begin
+     a_reg   <= a;
+     b_reg   <= b;
+     c_reg   <= c;
+     add_reg <= a - b;
+     m_reg   <= add_reg * c_reg;
+     p_reg   <= m_reg;
+  end
+
+// Output accumulation result
+assign presubmult_out = p_reg;
+
+endmodule // presubmult
diff --git a/tests/xilinx_ug901/presubmult.ys b/tests/xilinx_ug901/presubmult.ys
new file mode 100644
index 000000000..831458dec
--- /dev/null
+++ b/tests/xilinx_ug901/presubmult.ys
@@ -0,0 +1,23 @@
+read_verilog presubmult.v
+hierarchy -top presubmult
+proc
+flatten
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+
+cd presubmult
+#Vivado synthesizes 1 DSP48E1. (When SIZEIN = 8)
+stat
+select -assert-count 1 t:BUFG
+select -assert-count 51 t:FDRE
+select -assert-count 75 t:LUT2
+select -assert-count 10 t:LUT3
+select -assert-count 24 t:LUT4
+select -assert-count 15 t:LUT5
+select -assert-count 136 t:LUT6
+select -assert-count 24 t:MUXCY
+select -assert-count 46 t:MUXF7
+select -assert-count 14 t:MUXF8
+select -assert-count 26 t:XORCY
+
+select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
diff --git a/tests/xilinx_ug901/ram_simple_dual_one_clock.v b/tests/xilinx_ug901/ram_simple_dual_one_clock.v
new file mode 100644
index 000000000..3390e2da5
--- /dev/null
+++ b/tests/xilinx_ug901/ram_simple_dual_one_clock.v
@@ -0,0 +1,25 @@
+// Simple Dual-Port Block RAM with One Clock
+// File: simple_dual_one_clock.v
+
+module simple_dual_one_clock (clk,ena,enb,wea,addra,addrb,dia,dob);
+
+input clk,ena,enb,wea;
+input [9:0] addra,addrb;
+input [15:0] dia;
+output [15:0] dob;
+reg [15:0] ram [1023:0];
+reg [15:0] doa,dob;
+
+always @(posedge clk) begin 
+ if (ena) begin
+    if (wea)
+        ram[addra] <= dia;
+ end
+end
+
+always @(posedge clk) begin 
+  if (enb)
+    dob <= ram[addrb];
+end
+
+endmodule
\ No newline at end of file
diff --git a/tests/xilinx_ug901/ram_simple_dual_one_clock.ys b/tests/xilinx_ug901/ram_simple_dual_one_clock.ys
new file mode 100644
index 000000000..c1bde951e
--- /dev/null
+++ b/tests/xilinx_ug901/ram_simple_dual_one_clock.ys
@@ -0,0 +1,20 @@
+read_verilog ram_simple_dual_one_clock.v
+hierarchy -top simple_dual_one_clock
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+memory
+opt -full
+
+# TODO
+#equiv_opt -run prove: -assert null
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+design -load postopt
+cd simple_dual_one_clock
+#Vivado synthesizes 1 RAMB18E1.
+select -assert-count 1 t:BUFG
+select -assert-count 1 t:LUT2
+select -assert-count 1 t:RAMB18E1
+
+select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
diff --git a/tests/xilinx_ug901/ram_simple_dual_two_clocks.v b/tests/xilinx_ug901/ram_simple_dual_two_clocks.v
new file mode 100644
index 000000000..1113b928e
--- /dev/null
+++ b/tests/xilinx_ug901/ram_simple_dual_two_clocks.v
@@ -0,0 +1,30 @@
+// Simple Dual-Port Block RAM with Two Clocks
+// File: simple_dual_two_clocks.v
+
+module simple_dual_two_clocks (clka,clkb,ena,enb,wea,addra,addrb,dia,dob);
+
+input clka,clkb,ena,enb,wea;
+input [9:0] addra,addrb;
+input [15:0] dia;
+output [15:0] dob;
+reg [15:0] ram [1023:0];
+reg [15:0] dob;
+
+always @(posedge clka) 
+begin 
+  if (ena)
+    begin
+      if (wea)
+        ram[addra] <= dia;
+    end
+end
+
+always @(posedge clkb) 
+begin
+  if (enb)
+    begin
+      dob <= ram[addrb];
+    end
+end
+
+endmodule
diff --git a/tests/xilinx_ug901/ram_simple_dual_two_clocks.ys b/tests/xilinx_ug901/ram_simple_dual_two_clocks.ys
new file mode 100644
index 000000000..db0d789e9
--- /dev/null
+++ b/tests/xilinx_ug901/ram_simple_dual_two_clocks.ys
@@ -0,0 +1,20 @@
+read_verilog ram_simple_dual_two_clocks.v
+hierarchy -top simple_dual_two_clocks
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+memory
+opt -full
+
+# TODO
+#equiv_opt -run prove: -assert null
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+design -load postopt
+cd simple_dual_two_clocks
+#Vivado synthesizes 1 RAMB18E1.
+select -assert-count 2 t:BUFG
+select -assert-count 1 t:LUT2
+select -assert-count 1 t:RAMB18E1
+
+select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
diff --git a/tests/xilinx_ug901/rams_dist.v b/tests/xilinx_ug901/rams_dist.v
new file mode 100644
index 000000000..405283b69
--- /dev/null
+++ b/tests/xilinx_ug901/rams_dist.v
@@ -0,0 +1,24 @@
+// Dual-Port RAM with Asynchronous Read (Distributed RAM)
+// File: rams_dist.v
+
+module rams_dist (clk, we, a, dpra, di, spo, dpo);
+
+input clk;
+input we;
+input [5:0] a;
+input [5:0] dpra;
+input [15:0] di;
+output [15:0] spo;
+output [15:0] dpo;
+reg [15:0] ram [63:0];
+
+always @(posedge clk) 
+begin 
+ if (we)
+   ram[a] <= di;
+end
+
+assign spo = ram[a];
+assign dpo = ram[dpra];
+
+endmodule
diff --git a/tests/xilinx_ug901/rams_dist.ys b/tests/xilinx_ug901/rams_dist.ys
new file mode 100644
index 000000000..0aa1a8309
--- /dev/null
+++ b/tests/xilinx_ug901/rams_dist.ys
@@ -0,0 +1,21 @@
+read_verilog rams_dist.v
+hierarchy -top rams_dist
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+memory
+opt -full
+
+# TODO
+#equiv_opt -run prove: -assert null
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+
+design -load postopt
+cd rams_dist
+stat
+#Vivado synthesizes 32 RAM64X1D.
+select -assert-count 1 t:BUFG
+select -assert-count 32 t:RAM64X1D
+
+select -assert-none t:BUFG t:RAM64X1D %% t:* %D
diff --git a/tests/xilinx_ug901/rams_init_file.data b/tests/xilinx_ug901/rams_init_file.data
new file mode 100644
index 000000000..f14f0b324
--- /dev/null
+++ b/tests/xilinx_ug901/rams_init_file.data
@@ -0,0 +1,64 @@
+00001110110000011001111011000110
+00101011001011010101001000100011
+01110100010100011000011100001111
+01000001010000100101001110010100
+00001001101001111111101000101011
+00101101001011111110101010100111
+11101111000100111000111101101101
+10001111010010011001000011101111
+00000001100011100011110010011111
+11011111001110101011111001001010
+11100111010100111110110011001010
+11000100001001101100111100101001
+10001011100101011111111111100001
+11110101110110010000010110111010
+01001011000000111001010110101110
+11100001111111001010111010011110
+01101111011010010100001101110001
+01010100011011111000011000100100
+11110000111101101111001100001011
+10101101001111010100100100011100
+01011100001010111111101110101110
+01011101000100100111010010110101
+11110111000100000101011101101101
+11100111110001111010101100001101
+01110100000011101111111000011111
+00010011110101111000111001011101
+01101110001111100011010101101111
+10111100000000010011101011011011
+11000001001101001101111100010000
+00011111110010110110011111010101
+01100100100000011100100101110000
+10001000000100111011001010001111
+11001000100011101001010001100001
+10000000100111010011100111100011
+11011111010010100010101010000111
+10000000110111101000111110111011
+10110011010111101111000110011001
+00010111100001001010110111011100
+10011100101110101111011010110011
+01010011101101010001110110011010
+01111011011100010101000101000001
+10001000000110010110111001101010
+11101000001101010000111001010110
+11100011111100000111110101110101
+01001010000000001111111101101111
+00100011000011001000000010001111
+10011000111010110001001011100100
+11111111111011110101000101000111
+11000011000101000011100110100000
+01101101001011111010100011101001
+10000111101100101001110011010111
+11010110100100101110110010100100
+01001111111001101101011111001011
+11011001001101110110000100110111
+10110110110111100101110011100110
+10011100111001000010111111010110
+00000000001011011111001010110010
+10100110011010000010001000011011
+11001010111111001001110001110101
+00100001100010000111000101001000
+00111100101111110001101101111010
+11000010001010000000010100100001
+11000001000110001101000101001110
+10010011010100010001100100100111
diff --git a/tests/xilinx_ug901/rams_init_file.v b/tests/xilinx_ug901/rams_init_file.v
new file mode 100644
index 000000000..046779af9
--- /dev/null
+++ b/tests/xilinx_ug901/rams_init_file.v
@@ -0,0 +1,24 @@
+// Initializing Block RAM from external data file
+// Binary data
+// File: rams_init_file.v 
+
+module rams_init_file (clk, we, addr, din, dout);
+input clk;
+input we;
+input [5:0] addr;
+input [31:0] din;
+output [31:0] dout;
+
+reg [31:0] ram [0:63];
+reg [31:0] dout;
+
+initial begin
+$readmemb("rams_init_file.data",ram);
+end
+
+always @(posedge clk)
+begin
+  if (we)
+     ram[addr] <= din;
+  dout <= ram[addr];
+end endmodule
diff --git a/tests/xilinx_ug901/rams_init_file.ys b/tests/xilinx_ug901/rams_init_file.ys
new file mode 100644
index 000000000..d22a0f52c
--- /dev/null
+++ b/tests/xilinx_ug901/rams_init_file.ys
@@ -0,0 +1,22 @@
+read_verilog rams_init_file.v
+hierarchy -top rams_init_file
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+memory
+opt -full
+
+# TODO
+#equiv_opt -run prove: -assert null
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+
+design -load postopt
+cd rams_init_file
+stat
+#Vivado synthesizes 1 RAMB18E1.
+select -assert-count 1 t:BUFG
+select -assert-count 32 t:FDRE
+select -assert-count 32 t:RAM64X1D
+
+select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D
diff --git a/tests/xilinx_ug901/rams_pipeline.v b/tests/xilinx_ug901/rams_pipeline.v
new file mode 100644
index 000000000..e86d417f5
--- /dev/null
+++ b/tests/xilinx_ug901/rams_pipeline.v
@@ -0,0 +1,42 @@
+// Block RAM with Optional Output Registers
+// File: rams_pipeline
+
+module rams_pipeline (clk1, clk2, we, en1, en2, addr1, addr2, di, res1, res2);
+input clk1;
+input clk2;
+input we, en1, en2;
+input [9:0] addr1;
+input [9:0] addr2;
+input [15:0] di;
+output [15:0] res1;
+output [15:0] res2;
+reg [15:0] res1;
+reg [15:0] res2;
+reg [15:0] RAM [1023:0];
+reg [15:0] do1;
+reg [15:0] do2;
+
+always @(posedge clk1)
+begin
+    if (we == 1'b1)
+        RAM[addr1] <= di;
+    do1 <= RAM[addr1];
+end
+
+always @(posedge clk2)
+begin
+    do2 <= RAM[addr2];
+end
+
+always @(posedge clk1)
+begin
+    if (en1 == 1'b1)
+        res1 <= do1;
+end
+
+always @(posedge clk2)
+begin
+    if (en2 == 1'b1)
+        res2 <= do2;
+end 
+endmodule
diff --git a/tests/xilinx_ug901/rams_pipeline.ys b/tests/xilinx_ug901/rams_pipeline.ys
new file mode 100644
index 000000000..7fd7c76e4
--- /dev/null
+++ b/tests/xilinx_ug901/rams_pipeline.ys
@@ -0,0 +1,22 @@
+read_verilog rams_pipeline.v
+hierarchy -top rams_pipeline
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+memory
+opt -full
+
+# TODO
+#equiv_opt -run prove: -assert null
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+
+design -load postopt
+cd rams_pipeline
+stat
+#Vivado synthesizes 1 RAMB18E1.
+select -assert-count 2 t:BUFG
+select -assert-count 32 t:FDRE
+select -assert-count 2 t:RAMB18E1
+
+select -assert-none t:BUFG t:FDRE t:RAMB18E1 %% t:* %D
diff --git a/tests/xilinx_ug901/rams_sp_nc.v b/tests/xilinx_ug901/rams_sp_nc.v
new file mode 100644
index 000000000..08abc0d2c
--- /dev/null
+++ b/tests/xilinx_ug901/rams_sp_nc.v
@@ -0,0 +1,26 @@
+// Single-Port Block RAM No-Change Mode
+// File: rams_sp_nc.v
+
+module rams_sp_nc (clk, we, en, addr, di, dout);
+
+input clk; 
+input we; 
+input en;
+input [9:0] addr; 
+input [15:0] di; 
+output [15:0] dout;
+
+reg [15:0] RAM [1023:0];
+reg [15:0] dout;
+
+always @(posedge clk)
+begin
+  if (en)
+  begin
+    if (we)
+      RAM[addr] <= di;
+    else
+      dout <= RAM[addr];
+  end
+end
+endmodule
diff --git a/tests/xilinx_ug901/rams_sp_nc.ys b/tests/xilinx_ug901/rams_sp_nc.ys
new file mode 100644
index 000000000..9b7d6386f
--- /dev/null
+++ b/tests/xilinx_ug901/rams_sp_nc.ys
@@ -0,0 +1,22 @@
+read_verilog rams_sp_nc.v
+hierarchy -top rams_sp_nc
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+memory
+opt -full
+
+# TODO
+#equiv_opt -run prove: -assert null
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+
+design -load postopt
+cd rams_sp_nc
+stat
+#Vivado synthesizes 1 RAMB18E1.
+select -assert-count 1 t:BUFG
+select -assert-count 2 t:LUT2
+select -assert-count 1 t:RAMB18E1
+
+select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
diff --git a/tests/xilinx_ug901/rams_sp_rf.v b/tests/xilinx_ug901/rams_sp_rf.v
new file mode 100644
index 000000000..5e0adf88b
--- /dev/null
+++ b/tests/xilinx_ug901/rams_sp_rf.v
@@ -0,0 +1,26 @@
+// Single-Port Block RAM Read-First Mode
+// rams_sp_rf.v
+module rams_sp_rf (clk, en, we, addr, di, dout);
+
+input clk; 
+input we; 
+input en;
+input [9:0] addr; 
+input [15:0] di; 
+output [15:0] dout;
+
+reg [15:0] RAM [1023:0];
+reg [15:0] dout;
+
+always @(posedge clk)
+begin
+  if (en)
+    begin
+      if (we)
+        RAM[addr]<=di;
+      dout <= RAM[addr];
+    end
+end
+
+endmodule
+
diff --git a/tests/xilinx_ug901/rams_sp_rf.ys b/tests/xilinx_ug901/rams_sp_rf.ys
new file mode 100644
index 000000000..56f345c63
--- /dev/null
+++ b/tests/xilinx_ug901/rams_sp_rf.ys
@@ -0,0 +1,22 @@
+read_verilog rams_sp_rf.v
+hierarchy -top rams_sp_rf
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+memory
+opt -full
+
+# TODO
+#equiv_opt -run prove: -assert null
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+
+design -load postopt
+cd rams_sp_rf
+stat
+#Vivado synthesizes 1 RAMB18E1.
+select -assert-count 1 t:BUFG
+select -assert-count 1 t:LUT2
+select -assert-count 1 t:RAMB18E1
+
+select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
diff --git a/tests/xilinx_ug901/rams_sp_rf_rst.v b/tests/xilinx_ug901/rams_sp_rf_rst.v
new file mode 100644
index 000000000..cb8d50c4c
--- /dev/null
+++ b/tests/xilinx_ug901/rams_sp_rf_rst.v
@@ -0,0 +1,29 @@
+// Block RAM with Resettable Data Output
+// File: rams_sp_rf_rst.v
+
+module rams_sp_rf_rst (clk, en, we, rst, addr, di, dout);
+input clk; 
+input en; 
+input we; 
+input rst;
+input [9:0] addr; 
+input [15:0] di; 
+output [15:0] dout;
+
+reg [15:0] ram [1023:0];
+reg [15:0] dout;
+
+always @(posedge clk)
+begin
+  if (en) //optional enable
+    begin
+      if (we) //write enable
+        ram[addr] <= di;
+      if (rst) //optional reset
+        dout <= 0;
+      else
+        dout <= ram[addr];
+    end
+end
+
+endmodule
diff --git a/tests/xilinx_ug901/rams_sp_rf_rst.ys b/tests/xilinx_ug901/rams_sp_rf_rst.ys
new file mode 100644
index 000000000..57e4df9f5
--- /dev/null
+++ b/tests/xilinx_ug901/rams_sp_rf_rst.ys
@@ -0,0 +1,28 @@
+read_verilog rams_sp_rf_rst.v
+hierarchy -top rams_sp_rf_rst
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+memory
+opt -full
+
+# TODO
+#equiv_opt -run prove: -assert null
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+
+design -load postopt
+cd rams_sp_rf_rst
+stat
+#Vivado synthesizes 1 RAMB18E1.
+
+select -assert-count 1 t:BUFG
+select -assert-count 16 t:FDRE
+select -assert-count 5 t:LUT2
+select -assert-count 4 t:LUT3
+select -assert-count 13 t:LUT4
+select -assert-count 23 t:LUT5
+select -assert-count 32 t:LUT6
+select -assert-count 128 t:RAM128X1D
+
+select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:RAM128X1D %% t:* %D
diff --git a/tests/xilinx_ug901/rams_sp_rom.v b/tests/xilinx_ug901/rams_sp_rom.v
new file mode 100644
index 000000000..b6e05f6c8
--- /dev/null
+++ b/tests/xilinx_ug901/rams_sp_rom.v
@@ -0,0 +1,46 @@
+// Initializing Block RAM (Single-Port Block RAM)
+// File: rams_sp_rom 
+module rams_sp_rom (clk, we, addr, di, dout);
+input clk;
+input we;
+input [5:0] addr;
+input [19:0] di;
+output [19:0] dout;
+
+reg [19:0] ram [63:0];
+reg [19:0] dout;
+
+initial 
+begin
+  ram[63] = 20'h0200A; ram[62] = 20'h00300; ram[61] = 20'h08101;
+  ram[60] = 20'h04000; ram[59] = 20'h08601; ram[58] = 20'h0233A;
+  ram[57] = 20'h00300; ram[56] = 20'h08602; ram[55] = 20'h02310;
+  ram[54] = 20'h0203B; ram[53] = 20'h08300; ram[52] = 20'h04002;
+  ram[51] = 20'h08201; ram[50] = 20'h00500; ram[49] = 20'h04001;
+  ram[48] = 20'h02500; ram[47] = 20'h00340; ram[46] = 20'h00241;
+  ram[45] = 20'h04002; ram[44] = 20'h08300; ram[43] = 20'h08201;
+  ram[42] = 20'h00500; ram[41] = 20'h08101; ram[40] = 20'h00602;
+  ram[39] = 20'h04003; ram[38] = 20'h0241E; ram[37] = 20'h00301;
+  ram[36] = 20'h00102; ram[35] = 20'h02122; ram[34] = 20'h02021;
+  ram[33] = 20'h00301; ram[32] = 20'h00102; ram[31] = 20'h02222;
+  ram[30] = 20'h04001; ram[29] = 20'h00342; ram[28] = 20'h0232B; 
+  ram[27] = 20'h00900; ram[26] = 20'h00302; ram[25] = 20'h00102; 
+  ram[24] = 20'h04002; ram[23] = 20'h00900; ram[22] = 20'h08201; 
+  ram[21] = 20'h02023; ram[20] = 20'h00303; ram[19] = 20'h02433; 
+  ram[18] = 20'h00301; ram[17] = 20'h04004; ram[16] = 20'h00301; 
+  ram[15] = 20'h00102; ram[14] = 20'h02137; ram[13] = 20'h02036; 
+  ram[12] = 20'h00301; ram[11] = 20'h00102; ram[10] = 20'h02237; 
+  ram[9]  = 20'h04004; ram[8]  = 20'h00304; ram[7] = 20'h04040; 
+  ram[6]  = 20'h02500; ram[5]  = 20'h02500; ram[4] = 20'h02500; 
+  ram[3]  = 20'h0030D; ram[2]  = 20'h02341; ram[1] = 20'h08201; 
+  ram[0]  = 20'h0400D;
+end
+ 
+always @(posedge clk)
+begin
+  if (we)
+    ram[addr] <= di;
+  dout <= ram[addr];
+end 
+
+endmodule
diff --git a/tests/xilinx_ug901/rams_sp_rom.ys b/tests/xilinx_ug901/rams_sp_rom.ys
new file mode 100644
index 000000000..bb8680df0
--- /dev/null
+++ b/tests/xilinx_ug901/rams_sp_rom.ys
@@ -0,0 +1,22 @@
+read_verilog rams_sp_rom.v
+hierarchy -top rams_sp_rom
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+memory
+opt -full
+
+# TODO
+#equiv_opt -run prove: -assert null
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+
+design -load postopt
+cd rams_sp_rom
+stat
+#Vivado synthesizes 1 RAMB18E1.
+select -assert-count 1 t:BUFG
+select -assert-count 20 t:RAM64X1D
+select -assert-count 20 t:FDRE
+
+select -assert-none t:BUFG t:RAM64X1D t:FDRE %% t:* %D
diff --git a/tests/xilinx_ug901/rams_sp_rom_1.v b/tests/xilinx_ug901/rams_sp_rom_1.v
new file mode 100644
index 000000000..b3b8e89fe
--- /dev/null
+++ b/tests/xilinx_ug901/rams_sp_rom_1.v
@@ -0,0 +1,53 @@
+// ROMs Using Block RAM Resources.
+// File: rams_sp_rom_1.v
+//
+module rams_sp_rom_1 (clk, en, addr, dout);
+input clk;
+input en;
+input [5:0] addr;
+output  [19:0] dout;
+
+(*rom_style = "block" *) reg [19:0] data;
+
+always @(posedge clk) 
+begin 
+  if (en)
+    case(addr)
+      6'b000000: data <= 20'h0200A; 6'b100000: data <= 20'h02222;
+      6'b000001: data <= 20'h00300; 6'b100001: data <= 20'h04001;
+      6'b000010: data <= 20'h08101; 6'b100010: data <= 20'h00342;
+      6'b000011: data <= 20'h04000; 6'b100011: data <= 20'h0232B;
+      6'b000100: data <= 20'h08601; 6'b100100: data <= 20'h00900;
+      6'b000101: data <= 20'h0233A; 6'b100101: data <= 20'h00302;
+      6'b000110: data <= 20'h00300; 6'b100110: data <= 20'h00102;
+      6'b000111: data <= 20'h08602; 6'b100111: data <= 20'h04002;
+      6'b001000: data <= 20'h02310; 6'b101000: data <= 20'h00900;
+      6'b001001: data <= 20'h0203B; 6'b101001: data <= 20'h08201;
+      6'b001010: data <= 20'h08300; 6'b101010: data <= 20'h02023;
+      6'b001011: data <= 20'h04002; 6'b101011: data <= 20'h00303;
+      6'b001100: data <= 20'h08201; 6'b101100: data <= 20'h02433;
+      6'b001101: data <= 20'h00500; 6'b101101: data <= 20'h00301;
+      6'b001110: data <= 20'h04001; 6'b101110: data <= 20'h04004;
+      6'b001111: data <= 20'h02500; 6'b101111: data <= 20'h00301;
+      6'b010000: data <= 20'h00340; 6'b110000: data <= 20'h00102;
+      6'b010001: data <= 20'h00241; 6'b110001: data <= 20'h02137;
+      6'b010010: data <= 20'h04002; 6'b110010: data <= 20'h02036;
+      6'b010011: data <= 20'h08300; 6'b110011: data <= 20'h00301;
+      6'b010100: data <= 20'h08201; 6'b110100: data <= 20'h00102;
+      6'b010101: data <= 20'h00500; 6'b110101: data <= 20'h02237;
+      6'b010110: data <= 20'h08101; 6'b110110: data <= 20'h04004;
+      6'b010111: data <= 20'h00602; 6'b110111: data <= 20'h00304;
+      6'b011000: data <= 20'h04003; 6'b111000: data <= 20'h04040;
+      6'b011001: data <= 20'h0241E; 6'b111001: data <= 20'h02500;
+      6'b011010: data <= 20'h00301; 6'b111010: data <= 20'h02500;
+      6'b011011: data <= 20'h00102; 6'b111011: data <= 20'h02500;
+      6'b011100: data <= 20'h02122; 6'b111100: data <= 20'h0030D;
+      6'b011101: data <= 20'h02021; 6'b111101: data <= 20'h02341;
+      6'b011110: data <= 20'h00301; 6'b111110: data <= 20'h08201;
+      6'b011111: data <= 20'h00102; 6'b111111: data <= 20'h0400D;
+    endcase
+end 
+
+assign dout = data;
+
+endmodule
diff --git a/tests/xilinx_ug901/rams_sp_rom_1.ys b/tests/xilinx_ug901/rams_sp_rom_1.ys
new file mode 100644
index 000000000..4285df1f8
--- /dev/null
+++ b/tests/xilinx_ug901/rams_sp_rom_1.ys
@@ -0,0 +1,22 @@
+read_verilog rams_sp_rom_1.v
+hierarchy -top rams_sp_rom_1
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+memory
+opt -full
+
+# TODO
+#equiv_opt -run prove: -assert null
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+
+design -load postopt
+cd rams_sp_rom_1
+stat
+#Vivado synthesizes 1 RAMB18E1.
+select -assert-count 1 t:BUFG
+select -assert-count 14 t:LUT6
+select -assert-count 14 t:FDRE
+
+select -assert-none t:BUFG t:LUT6 t:FDRE %% t:* %D
diff --git a/tests/xilinx_ug901/rams_sp_wf.v b/tests/xilinx_ug901/rams_sp_wf.v
new file mode 100644
index 000000000..55ed6bd54
--- /dev/null
+++ b/tests/xilinx_ug901/rams_sp_wf.v
@@ -0,0 +1,26 @@
+// Single-Port Block RAM Write-First Mode (recommended template)
+// File: rams_sp_wf.v
+module rams_sp_wf (clk, we, en, addr, di, dout);
+input clk; 
+input we; 
+input en;
+input [9:0] addr; 
+input [15:0] di; 
+output [15:0] dout;
+reg [15:0] RAM [1023:0];
+reg [15:0] dout;
+
+always @(posedge clk)
+begin
+  if (en)
+  begin
+    if (we)
+      begin
+        RAM[addr] <= di;
+        dout <= di;
+      end
+   else
+    dout <= RAM[addr];
+  end
+end
+endmodule
diff --git a/tests/xilinx_ug901/rams_sp_wf.ys b/tests/xilinx_ug901/rams_sp_wf.ys
new file mode 100644
index 000000000..4d9a9cfea
--- /dev/null
+++ b/tests/xilinx_ug901/rams_sp_wf.ys
@@ -0,0 +1,26 @@
+read_verilog rams_sp_wf.v
+hierarchy -top rams_sp_wf
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+memory
+opt -full
+
+# TODO
+#equiv_opt -run prove: -assert null
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+
+design -load postopt
+cd rams_sp_wf
+stat
+#Vivado synthesizes 1 RAMB18E1.
+
+select -assert-count 1 t:BUFG
+select -assert-count 16 t:FDRE
+select -assert-count 44 t:LUT5
+select -assert-count 38 t:LUT6
+select -assert-count 10 t:MUXF7
+select -assert-count 128 t:RAM128X1D
+
+select -assert-none t:BUFG t:LUT2 t:FDRE t:LUT5 t:LUT6 t:MUXF7 t:RAM128X1D %% t:* %D
diff --git a/tests/xilinx_ug901/rams_tdp_rf_rf.v b/tests/xilinx_ug901/rams_tdp_rf_rf.v
new file mode 100644
index 000000000..63899226f
--- /dev/null
+++ b/tests/xilinx_ug901/rams_tdp_rf_rf.v
@@ -0,0 +1,33 @@
+// Dual-Port Block RAM with Two Write Ports
+// File: rams_tdp_rf_rf.v
+
+module rams_tdp_rf_rf (clka,clkb,ena,enb,wea,web,addra,addrb,dia,dib,doa,dob);
+
+input clka,clkb,ena,enb,wea,web;
+input [9:0] addra,addrb;
+input [15:0] dia,dib;
+output [15:0] doa,dob;
+reg [15:0] ram [1023:0];
+reg [15:0] doa,dob;
+
+always @(posedge clka)
+begin 
+  if (ena)
+    begin
+      if (wea)
+        ram[addra] <= dia;
+      doa <= ram[addra];
+    end
+end
+
+always @(posedge clkb) 
+begin 
+  if (enb)
+    begin
+      if (web)
+        ram[addrb] <= dib;
+      dob <= ram[addrb];
+    end
+end
+
+endmodule
diff --git a/tests/xilinx_ug901/rams_tdp_rf_rf.ys b/tests/xilinx_ug901/rams_tdp_rf_rf.ys
new file mode 100644
index 000000000..20cf4fdcc
--- /dev/null
+++ b/tests/xilinx_ug901/rams_tdp_rf_rf.ys
@@ -0,0 +1,21 @@
+read_verilog rams_tdp_rf_rf.v
+hierarchy -top rams_tdp_rf_rf
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+memory
+opt -full
+
+# TODO
+#equiv_opt -run prove: -assert null
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+
+design -load postopt
+cd rams_tdp_rf_rf
+stat
+#Vivado synthesizes 1 RAMB18E1.
+select -assert-count 1 t:$mem
+select -assert-count 2 t:LUT2
+
+select -assert-none t:$mem t:LUT2 %% t:* %D
diff --git a/tests/xilinx_ug901/registers_1.v b/tests/xilinx_ug901/registers_1.v
new file mode 100644
index 000000000..beea6e666
--- /dev/null
+++ b/tests/xilinx_ug901/registers_1.v
@@ -0,0 +1,25 @@
+// 8-bit Register with
+// Rising-edge Clock
+// Active-high Synchronous Clear
+// Active-high Clock Enable
+// File: registers_1.v
+
+module registers_1(d_in,ce,clk,clr,dout);
+input [7:0] d_in;
+input ce;
+input clk;
+input clr;
+output [7:0] dout;
+reg [7:0] d_reg;
+
+always @ (posedge clk)
+begin
+ if(clr)
+  d_reg <= 8'b0;
+ else if(ce)
+  d_reg <= d_in;
+end
+
+assign dout = d_reg;
+endmodule
+
diff --git a/tests/xilinx_ug901/registers_1.ys b/tests/xilinx_ug901/registers_1.ys
new file mode 100644
index 000000000..39ca894a2
--- /dev/null
+++ b/tests/xilinx_ug901/registers_1.ys
@@ -0,0 +1,12 @@
+read_verilog registers_1.v
+hierarchy -top registers_1
+proc
+flatten
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd registers_1 # Constrain all select calls below inside the top module
+#Vivado synthesizes 1 BUFG, 8 FDRE.
+select -assert-count 1 t:BUFG
+select -assert-count 8 t:FDRE
+select -assert-count 9 t:LUT2
+select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D
diff --git a/tests/xilinx_ug901/run-test.sh b/tests/xilinx_ug901/run-test.sh
new file mode 100755
index 000000000..ea56b70f0
--- /dev/null
+++ b/tests/xilinx_ug901/run-test.sh
@@ -0,0 +1,20 @@
+#!/usr/bin/env bash
+set -e
+{
+echo "all::"
+for x in *.ys; do
+	echo "all:: run-$x"
+	echo "run-$x:"
+	echo "	@echo 'Running $x..'"
+	echo "	@../../yosys -ql ${x%.ys}.log $x"
+done
+for s in *.sh; do
+	if [ "$s" != "run-test.sh" ]; then
+		echo "all:: run-$s"
+		echo "run-$s:"
+		echo "	@echo 'Running $s..'"
+		echo "	@bash $s"
+	fi
+done
+} > run-test.mk
+exec ${MAKE:-make} -f run-test.mk
diff --git a/tests/xilinx_ug901/sfir_shifter.v b/tests/xilinx_ug901/sfir_shifter.v
new file mode 100644
index 000000000..a8b144bcd
--- /dev/null
+++ b/tests/xilinx_ug901/sfir_shifter.v
@@ -0,0 +1,19 @@
+//sfir_shifter.v
+(* dont_touch = "yes" *)
+module sfir_shifter #(parameter dsize = 16, nbtap = 4)
+                     (input clk,input [dsize-1:0] datain, output [dsize-1:0] dataout);
+
+   (* srl_style = "srl_register" *) reg [dsize-1:0] tmp [0:2*nbtap-1];
+   integer i;
+
+   always @(posedge clk)
+     begin
+        tmp[0] <= datain;
+        for (i=0; i<=2*nbtap-2; i=i+1)
+          tmp[i+1] <= tmp[i];
+     end
+
+   assign dataout = tmp[2*nbtap-1];
+
+endmodule
+// sfir_shifter
diff --git a/tests/xilinx_ug901/sfir_shifter.ys b/tests/xilinx_ug901/sfir_shifter.ys
new file mode 100644
index 000000000..b9fbeb8cb
--- /dev/null
+++ b/tests/xilinx_ug901/sfir_shifter.ys
@@ -0,0 +1,16 @@
+read_verilog sfir_shifter.v
+hierarchy -top sfir_shifter
+proc
+flatten
+#ERROR: Found 32 unproven $equiv cells in 'equiv_status -assert'.
+#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+
+cd sfir_shifter
+#Vivado synthesizes 32 FDRE, 16 SRL16E.
+stat
+select -assert-count 1 t:BUFG
+select -assert-count 16 t:SRL16E
+
+select -assert-none t:BUFG t:SRL16E %% t:* %D
diff --git a/tests/xilinx_ug901/shift_registers_0.v b/tests/xilinx_ug901/shift_registers_0.v
new file mode 100644
index 000000000..77a3ec893
--- /dev/null
+++ b/tests/xilinx_ug901/shift_registers_0.v
@@ -0,0 +1,22 @@
+//  8-bit Shift Register
+//  Rising edge clock
+//  Active high clock enable
+//  Concatenation-based template
+//  File: shift_registers_0.v
+
+module shift_registers_0 (clk, clken, SI, SO);
+parameter WIDTH = 32; 
+input clk, clken, SI; 
+output SO;
+
+reg [WIDTH-1:0] shreg;
+
+always @(posedge clk)
+  begin
+    if (clken)
+      shreg = {shreg[WIDTH-2:0], SI};
+  end
+
+assign SO = shreg[WIDTH-1];
+
+endmodule
diff --git a/tests/xilinx_ug901/shift_registers_0.ys b/tests/xilinx_ug901/shift_registers_0.ys
new file mode 100644
index 000000000..ae7d23a7f
--- /dev/null
+++ b/tests/xilinx_ug901/shift_registers_0.ys
@@ -0,0 +1,13 @@
+read_verilog shift_registers_0.v
+hierarchy -top shift_registers_0
+proc
+flatten
+#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd shift_registers_0 # Constrain all select calls below inside the top module
+#Vivado synthesizes 1 BUFG, 2 FDRE, 3 SRLC32E.
+select -assert-count 1 t:BUFG
+select -assert-count 1 t:SRLC32E
+select -assert-none t:BUFG t:SRLC32E %% t:* %D
diff --git a/tests/xilinx_ug901/shift_registers_1.v b/tests/xilinx_ug901/shift_registers_1.v
new file mode 100644
index 000000000..d50820e7b
--- /dev/null
+++ b/tests/xilinx_ug901/shift_registers_1.v
@@ -0,0 +1,24 @@
+// 32-bit Shift Register
+// Rising edge clock
+// Active high clock enable
+// For-loop based template
+// File: shift_registers_1.v
+
+module shift_registers_1 (clk, clken, SI, SO);
+parameter WIDTH = 32; 
+input clk, clken, SI; 
+output SO;
+reg [WIDTH-1:0] shreg;
+
+integer i;
+always @(posedge clk)
+begin
+  if (clken)
+    begin
+      for (i = 0; i < WIDTH-1; i = i+1)
+        shreg[i+1] <= shreg[i];
+      shreg[0] <= SI; 
+    end
+end
+assign SO = shreg[WIDTH-1];
+endmodule
diff --git a/tests/xilinx_ug901/shift_registers_1.ys b/tests/xilinx_ug901/shift_registers_1.ys
new file mode 100644
index 000000000..fb935c446
--- /dev/null
+++ b/tests/xilinx_ug901/shift_registers_1.ys
@@ -0,0 +1,14 @@
+read_verilog shift_registers_1.v
+hierarchy -top shift_registers_1
+proc
+flatten
+
+#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd shift_registers_1 # Constrain all select calls below inside the top module
+#Vivado synthesizes 1 BUFG, 2 FDRE, 3 SRLC32E.
+select -assert-count 1 t:BUFG
+select -assert-count 1 t:SRLC32E
+select -assert-none t:BUFG t:SRLC32E %% t:* %D
diff --git a/tests/xilinx_ug901/squarediffmacc.v b/tests/xilinx_ug901/squarediffmacc.v
new file mode 100644
index 000000000..6535b24c4
--- /dev/null
+++ b/tests/xilinx_ug901/squarediffmacc.v
@@ -0,0 +1,52 @@
+// This module performs subtraction of two inputs, squaring on the diff
+// and then accumulation
+// This can be implemented in 1 DSP Block (Ultrascale architecture)
+// File : squarediffmacc.v
+module squarediffmacc  # (
+						//Default parameters were changed because of slow test
+                          //parameter SIZEIN = 16,
+                                    //SIZEOUT = 40
+						  parameter SIZEIN = 8,
+                          SIZEOUT = 20
+                         )
+                        (
+                         input clk,
+                         input ce,
+                         input sload,
+                         input signed [SIZEIN-1:0]   a,
+                         input signed [SIZEIN-1:0]   b,
+                         output signed [SIZEOUT+1:0] accum_out
+                        );
+
+// Declare registers for intermediate values
+reg signed [SIZEIN-1:0]  a_reg, b_reg;
+reg signed [SIZEIN:0]  diff_reg;
+reg                       sload_reg;
+reg signed [2*SIZEIN+1:0] m_reg;
+reg signed [SIZEOUT-1:0]  adder_out, old_result;
+
+  always @(sload_reg or adder_out)
+  if (sload_reg)
+    old_result <= 0;
+  else
+    // 'sload' is now and opens the accumulation loop.
+    // The accumulator takes the next multiplier output
+    // in the same cycle.
+    old_result <= adder_out;
+
+  always @(posedge clk)
+  if (ce)
+  begin
+    a_reg     <= a;
+    b_reg     <= b;
+    diff_reg  <= a_reg - b_reg;
+    m_reg  <= diff_reg * diff_reg;
+    sload_reg <= sload;
+    // Store accumulation result into a register
+    adder_out <= old_result + m_reg;
+  end
+
+  // Output accumulation result
+  assign accum_out = adder_out;
+
+endmodule // squarediffmacc
diff --git a/tests/xilinx_ug901/squarediffmacc.ys b/tests/xilinx_ug901/squarediffmacc.ys
new file mode 100644
index 000000000..92474bea3
--- /dev/null
+++ b/tests/xilinx_ug901/squarediffmacc.ys
@@ -0,0 +1,23 @@
+read_verilog squarediffmacc.v
+hierarchy -top squarediffmacc
+proc
+flatten
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+
+cd squarediffmacc
+#Vivado synthesizes 1 DSP48E1, 33 FDRE, 16 LUT.
+stat
+select -assert-count 1 t:BUFG
+select -assert-count 64 t:FDRE
+select -assert-count 78 t:LUT2
+select -assert-count 7 t:LUT3
+select -assert-count 11 t:LUT4
+select -assert-count 8 t:LUT5
+select -assert-count 125 t:LUT6
+select -assert-count 44 t:MUXCY
+select -assert-count 50 t:MUXF7
+select -assert-count 17 t:MUXF8
+select -assert-count 47 t:XORCY
+
+select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
diff --git a/tests/xilinx_ug901/squarediffmult.v b/tests/xilinx_ug901/squarediffmult.v
new file mode 100644
index 000000000..0f41b67bc
--- /dev/null
+++ b/tests/xilinx_ug901/squarediffmult.v
@@ -0,0 +1,42 @@
+// Squarer support for DSP block (DSP48E2) with 
+// pre-adder configured
+// as subtractor
+// File: squarediffmult.v
+
+module squarediffmult # (parameter SIZEIN = 16)
+                        (
+                          input clk, ce, rst,
+                          input  signed [SIZEIN-1:0]   a, b,
+                          output signed [2*SIZEIN+1:0] square_out
+                        );
+
+   // Declare registers for intermediate values
+reg signed [SIZEIN-1:0]   a_reg, b_reg;
+reg signed [SIZEIN:0]     diff_reg;
+reg signed [2*SIZEIN+1:0] m_reg, p_reg;
+
+always @(posedge clk)
+begin
+ if (rst)
+  begin
+   a_reg    <= 0;
+   b_reg    <= 0;
+   diff_reg <= 0;   
+   m_reg    <= 0;
+   p_reg    <= 0;
+  end
+ else
+  if (ce)
+  begin
+    a_reg     <= a;
+    b_reg     <= b;
+    diff_reg <= a_reg - b_reg;
+    m_reg  <= diff_reg * diff_reg;
+    p_reg  <= m_reg;     
+ end
+end
+
+// Output result
+assign square_out = p_reg;
+   
+endmodule // squarediffmult
diff --git a/tests/xilinx_ug901/squarediffmult.ys b/tests/xilinx_ug901/squarediffmult.ys
new file mode 100644
index 000000000..3468e5bb4
--- /dev/null
+++ b/tests/xilinx_ug901/squarediffmult.ys
@@ -0,0 +1,30 @@
+read_verilog squarediffmult.v
+hierarchy -top squarediffmult
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+memory
+opt -full
+
+# TODO
+#equiv_opt -run prove: -assert null
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+
+design -load postopt
+cd squarediffmult
+stat
+#Vivado synthesizes 16 FDRE, 1 DSP48E1.
+select -assert-count 1 t:BUFG
+select -assert-count 117 t:FDRE
+select -assert-count 223 t:LUT2
+select -assert-count 50 t:LUT3
+select -assert-count 38 t:LUT4
+select -assert-count 56 t:LUT5
+select -assert-count 372 t:LUT6
+select -assert-count 49 t:MUXCY
+select -assert-count 99 t:MUXF7
+select -assert-count 26 t:MUXF8
+select -assert-count 51 t:XORCY
+
+select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
diff --git a/tests/xilinx_ug901/top_mux.v b/tests/xilinx_ug901/top_mux.v
new file mode 100644
index 000000000..c23c7491c
--- /dev/null
+++ b/tests/xilinx_ug901/top_mux.v
@@ -0,0 +1,18 @@
+// Multiplexer using case statement 
+module mux4 (sel, a, b, c, d, outmux);
+input [1:0] sel;
+input [1:0] a, b, c, d;
+output [1:0] outmux;
+reg [1:0] outmux;
+
+always @ *
+   begin 
+	   case(sel)
+		  2'b00 : outmux = a;
+      2'b01 : outmux = b;
+      2'b10 : outmux = c;
+      2'b11 : outmux = d;
+     endcase
+   end 
+endmodule
+
diff --git a/tests/xilinx_ug901/top_mux.ys b/tests/xilinx_ug901/top_mux.ys
new file mode 100644
index 000000000..0245f3bbc
--- /dev/null
+++ b/tests/xilinx_ug901/top_mux.ys
@@ -0,0 +1,13 @@
+read_verilog top_mux.v
+hierarchy -top mux4
+proc
+flatten
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+
+cd mux4
+#Vivado synthesizes 2 LUT.
+stat
+select -assert-count 2 t:LUT6
+
+select -assert-none t:LUT6 %% t:* %D
diff --git a/tests/xilinx_ug901/tristates_1.v b/tests/xilinx_ug901/tristates_1.v
new file mode 100644
index 000000000..0038a9989
--- /dev/null
+++ b/tests/xilinx_ug901/tristates_1.v
@@ -0,0 +1,17 @@
+// Tristate Description Using Combinatorial Always Block
+// File: tristates_1.v
+//
+module tristates_1 (T, I, O);
+input  T, I;
+output O;
+reg    O;
+
+always @(T or I)
+begin
+  if (~T)
+    O = I;
+  else
+   O = 1'bZ;
+end
+
+endmodule
diff --git a/tests/xilinx_ug901/tristates_1.ys b/tests/xilinx_ug901/tristates_1.ys
new file mode 100644
index 000000000..7c13dc227
--- /dev/null
+++ b/tests/xilinx_ug901/tristates_1.ys
@@ -0,0 +1,13 @@
+read_verilog tristates_1.v
+hierarchy -top tristates_1
+proc
+tribuf
+flatten
+synth
+equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd tristates_1 # Constrain all select calls below inside the top module
+#Vivado synthesizes 3 IBUF, 1 OBUFT.
+select -assert-count 1 t:LUT1
+select -assert-count 1 t:$_TBUF_
+select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D
diff --git a/tests/xilinx_ug901/tristates_2.v b/tests/xilinx_ug901/tristates_2.v
new file mode 100644
index 000000000..0c70a1257
--- /dev/null
+++ b/tests/xilinx_ug901/tristates_2.v
@@ -0,0 +1,10 @@
+// Tristate Description Using Concurrent Assignment
+// File: tristates_2.v
+//
+module tristates_2 (T, I, O);
+input  T, I;
+output O;
+
+assign O = (~T) ? I: 1'bZ;
+
+endmodule
diff --git a/tests/xilinx_ug901/tristates_2.ys b/tests/xilinx_ug901/tristates_2.ys
new file mode 100644
index 000000000..ba2e1d855
--- /dev/null
+++ b/tests/xilinx_ug901/tristates_2.ys
@@ -0,0 +1,13 @@
+read_verilog tristates_2.v
+hierarchy -top tristates_2
+proc
+tribuf
+flatten
+synth
+equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd tristates_2 # Constrain all select calls below inside the top module
+#Vivado synthesizes 3 IBUF, 1 OBUFT.
+select -assert-count 1 t:LUT1
+select -assert-count 1 t:$_TBUF_
+select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D
diff --git a/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.v b/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.v
new file mode 100644
index 000000000..f5e843dc9
--- /dev/null
+++ b/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.v
@@ -0,0 +1,78 @@
+//  Xilinx UltraRAM Single Port No Change Mode.  This code implements
+//  a parameterizable UltraRAM block in No Change mode. The behavior of this RAM is
+//  when data is written, the output of RAM is unchanged. Only when write is
+//  inactive data corresponding to the address is presented on the output port.
+//
+module xilinx_ultraram_single_port_no_change #(
+//Default parameters were changed because of slow test
+  //parameter AWIDTH = 12,  // Address Width
+  //parameter DWIDTH = 72,  // Data Width
+  //parameter NBPIPE = 3    // Number of pipeline Registers
+  parameter AWIDTH = 8,  // Address Width
+  parameter DWIDTH = 8,  // Data Width
+  parameter NBPIPE = 3    // Number of pipeline Registers
+ ) (
+    input clk,                    // Clock
+    input rst,                    // Reset
+    input we,                     // Write Enable
+    input regce,                  // Output Register Enable
+    input mem_en,                 // Memory Enable
+    input [DWIDTH-1:0] din,       // Data Input
+    input [AWIDTH-1:0] addr,      // Address Input
+    output reg [DWIDTH-1:0] dout  // Data Output
+   );
+
+(* ram_style = "ultra" *)
+reg [DWIDTH-1:0] mem[(1<<AWIDTH)-1:0];        // Memory Declaration
+reg [DWIDTH-1:0] memreg;
+reg [DWIDTH-1:0] mem_pipe_reg[NBPIPE-1:0];    // Pipelines for memory
+reg mem_en_pipe_reg[NBPIPE:0];                // Pipelines for memory enable
+
+integer          i;
+
+// RAM : Read has one latency, Write has one latency as well.
+always @ (posedge clk)
+begin
+ if(mem_en)
+  begin
+  if(we)
+    mem[addr] <= din;
+  else
+   memreg <= mem[addr];
+  end
+end
+// The enable of the RAM goes through a pipeline to produce a
+// series of pipelined enable signals required to control the data
+// pipeline.
+always @ (posedge clk)
+begin
+mem_en_pipe_reg[0] <= mem_en;
+ for (i=0; i<NBPIPE; i=i+1)
+  mem_en_pipe_reg[i+1] <= mem_en_pipe_reg[i];
+end
+
+// RAM output data goes through a pipeline.
+always @ (posedge clk)
+begin
+ if (mem_en_pipe_reg[0])
+  mem_pipe_reg[0] <= memreg;
+end
+
+always @ (posedge clk)
+begin
+ for (i = 0; i < NBPIPE-1; i = i+1)
+  if (mem_en_pipe_reg[i+1])
+    mem_pipe_reg[i+1] <= mem_pipe_reg[i];
+end
+
+// Final output register gives user the option to add a reset and
+// an additional enable signal just for the data ouptut
+always @ (posedge clk)
+begin
+ if (rst)
+  dout <= 0;
+ else if (mem_en_pipe_reg[NBPIPE] && regce)
+  dout <= mem_pipe_reg[NBPIPE-1];
+end
+endmodule
+
diff --git a/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.ys b/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.ys
new file mode 100644
index 000000000..df3126e67
--- /dev/null
+++ b/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.ys
@@ -0,0 +1,25 @@
+read_verilog xilinx_ultraram_single_port_no_change.v
+hierarchy -top xilinx_ultraram_single_port_no_change
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+memory
+opt -full
+
+# TODO
+#equiv_opt -run prove: -assert null
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+
+design -load postopt
+cd xilinx_ultraram_single_port_no_change
+stat
+#Vivado synthesizes 1 RAMB36E1, 28 FDRE.
+select -assert-count 1 t:BUFG
+select -assert-count 53 t:FDRE
+select -assert-count 1 t:LUT1
+select -assert-count 9 t:LUT2
+select -assert-count 11 t:LUT3
+select -assert-count 16 t:RAM128X1D
+
+select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D
diff --git a/tests/xilinx_ug901/xilinx_ultraram_single_port_read_first.v b/tests/xilinx_ug901/xilinx_ultraram_single_port_read_first.v
new file mode 100644
index 000000000..d36c38fe1
--- /dev/null
+++ b/tests/xilinx_ug901/xilinx_ultraram_single_port_read_first.v
@@ -0,0 +1,78 @@
+//  Xilinx UltraRAM Single Port Read First Mode.  This code implements
+//  a parameterizable UltraRAM block in read first mode. The behavior of this RAM is
+//  when data is written, the old memory contents at the write address are
+//  presented on the output port.
+//
+module xilinx_ultraram_single_port_read_first #(
+
+//Default parameters were changed because of slow test
+  //parameter AWIDTH = 12,  // Address Width
+  //parameter DWIDTH = 72,  // Data Width
+  //parameter NBPIPE = 3    // Number of pipeline Registers
+  parameter AWIDTH = 8,  // Address Width
+  parameter DWIDTH = 8,  // Data Width
+  parameter NBPIPE = 3    // Number of pipeline Registers
+ ) (
+    input clk,                    // Clock
+    input rst,                    // Reset
+    input we,                     // Write Enable
+    input regce,                  // Output Register Enable
+    input mem_en,                 // Memory Enable
+    input [DWIDTH-1:0] din,       // Data Input
+    input [AWIDTH-1:0] addr,      // Address Input
+    output reg [DWIDTH-1:0] dout  // Data Output
+   );
+
+(* ram_style = "ultra" *)
+reg [DWIDTH-1:0] mem[(1<<AWIDTH)-1:0];        // Memory Declaration
+reg [DWIDTH-1:0] memreg;
+reg [DWIDTH-1:0] mem_pipe_reg[NBPIPE-1:0];    // Pipelines for memory
+reg mem_en_pipe_reg[NBPIPE:0];                // Pipelines for memory enable
+
+integer          i;
+
+// RAM : Both READ and WRITE have a latency of one
+always @ (posedge clk)
+begin
+ if(mem_en)
+  begin
+   if(we)
+    mem[addr] <= din;
+   memreg <= mem[addr];
+  end
+end
+
+// The enable of the RAM goes through a pipeline to produce a
+// series of pipelined enable signals required to control the data
+// pipeline.
+always @ (posedge clk)
+begin
+ mem_en_pipe_reg[0] <= mem_en;
+ for (i=0; i<NBPIPE; i=i+1)
+   mem_en_pipe_reg[i+1] <= mem_en_pipe_reg[i];
+end
+
+// RAM output data goes through a pipeline.
+always @ (posedge clk)
+begin
+ if (mem_en_pipe_reg[0])
+  mem_pipe_reg[0] <= memreg;
+end
+
+always @ (posedge clk)
+begin
+ for (i = 0; i < NBPIPE-1; i = i+1)
+  if (mem_en_pipe_reg[i+1])
+   mem_pipe_reg[i+1] <= mem_pipe_reg[i];
+end
+
+// Final output register gives user the option to add a reset and
+// an additional enable signal just for the data ouptut
+always @ (posedge clk)
+begin
+ if (rst)
+   dout <= 0;
+ else if (mem_en_pipe_reg[NBPIPE] && regce)
+   dout <= mem_pipe_reg[NBPIPE-1];
+end
+endmodule
diff --git a/tests/xilinx_ug901/xilinx_ultraram_single_port_read_first.ys b/tests/xilinx_ug901/xilinx_ultraram_single_port_read_first.ys
new file mode 100644
index 000000000..4907d042d
--- /dev/null
+++ b/tests/xilinx_ug901/xilinx_ultraram_single_port_read_first.ys
@@ -0,0 +1,24 @@
+read_verilog xilinx_ultraram_single_port_read_first.v
+hierarchy -top xilinx_ultraram_single_port_read_first
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+memory
+opt -full
+
+# TODO
+#equiv_opt -run prove: -assert null
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+
+design -load postopt
+cd xilinx_ultraram_single_port_read_first
+#Vivado synthesizes 1 RAMB18E1, 28 FDRE.
+select -assert-count 1 t:BUFG
+select -assert-count 53 t:FDRE
+select -assert-count 1 t:LUT1
+select -assert-count 8 t:LUT2
+select -assert-count 11 t:LUT3
+select -assert-count 16 t:RAM128X1D
+
+select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D
diff --git a/tests/xilinx_ug901/xilinx_ultraram_single_port_write_first.v b/tests/xilinx_ug901/xilinx_ultraram_single_port_write_first.v
new file mode 100644
index 000000000..7985d3d4a
--- /dev/null
+++ b/tests/xilinx_ug901/xilinx_ultraram_single_port_write_first.v
@@ -0,0 +1,82 @@
+//  Xilinx UltraRAM Single Port Write First Mode.  This code implements
+//  a parameterizable UltraRAM block in write first mode. The behavior of this RAM is
+//  when data is written, the new memory contents at the write address are
+//  presented on the output port.
+//
+module xilinx_ultraram_single_port_write_first #(
+
+//Default parameters were changed because of slow test
+  //parameter AWIDTH = 12,  // Address Width
+  //parameter DWIDTH = 72,  // Data Width
+  //parameter NBPIPE = 3    // Number of pipeline Registers
+  parameter AWIDTH = 8,  // Address Width
+  parameter DWIDTH = 8,  // Data Width
+  parameter NBPIPE = 3    // Number of pipeline Registers
+ ) (
+    input clk,                    // Clock
+    input rst,                    // Reset
+    input we,                     // Write Enable
+    input regce,                  // Output Register Enable
+    input mem_en,                 // Memory Enable
+    input [DWIDTH-1:0] din,       // Data Input
+    input [AWIDTH-1:0] addr,      // Address Input
+    output reg [DWIDTH-1:0] dout  // Data Output
+   );
+
+(* ram_style = "ultra" *)
+reg [DWIDTH-1:0] mem[(1<<AWIDTH)-1:0];        // Memory Declaration
+reg [DWIDTH-1:0] memreg;
+reg [DWIDTH-1:0] mem_pipe_reg[NBPIPE-1:0];    // Pipelines for memory
+reg mem_en_pipe_reg[NBPIPE:0];                // Pipelines for memory enable
+
+integer          i;
+
+// RAM : Both READ and WRITE have a latency of one
+always @ (posedge clk)
+begin
+ if(mem_en)
+  begin
+    if(we)
+    begin
+      mem[addr] <= din;
+     memreg <= din;
+   end
+    else
+     memreg <= mem[addr];
+  end
+end
+
+// The enable of the RAM goes through a pipeline to produce a
+// series of pipelined enable signals required to control the data
+// pipeline.
+always @ (posedge clk)
+begin
+ mem_en_pipe_reg[0] <= mem_en;
+ for (i=0; i<NBPIPE; i=i+1)
+   mem_en_pipe_reg[i+1] <= mem_en_pipe_reg[i];
+end
+
+// RAM output data goes through a pipeline.
+always @ (posedge clk)
+begin
+ if (mem_en_pipe_reg[0])
+  mem_pipe_reg[0] <= memreg;
+end
+
+always @ (posedge clk)
+begin
+  for (i = 0; i < NBPIPE-1; i = i+1)
+   if (mem_en_pipe_reg[i+1])
+     mem_pipe_reg[i+1] <= mem_pipe_reg[i];
+end
+
+// Final output register gives user the option to add a reset and
+// an additional enable signal just for the data ouptut
+always @ (posedge clk)
+begin
+ if (rst)
+  dout <= 0;
+ else if (mem_en_pipe_reg[NBPIPE] && regce)
+  dout <= mem_pipe_reg[NBPIPE-1];
+end
+endmodule
diff --git a/tests/xilinx_ug901/xilinx_ultraram_single_port_write_first.ys b/tests/xilinx_ug901/xilinx_ultraram_single_port_write_first.ys
new file mode 100644
index 000000000..9ca6b4d89
--- /dev/null
+++ b/tests/xilinx_ug901/xilinx_ultraram_single_port_write_first.ys
@@ -0,0 +1,24 @@
+read_verilog xilinx_ultraram_single_port_write_first.v
+hierarchy -top xilinx_ultraram_single_port_write_first
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+memory
+opt -full
+
+# TODO
+#equiv_opt -run prove: -assert null
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
+
+design -load postopt
+cd xilinx_ultraram_single_port_write_first
+#Vivado synthesizes 1 RAMB18E1, 28 FDRE.
+select -assert-count 1 t:BUFG
+select -assert-count 44 t:FDRE
+select -assert-count 8 t:LUT5
+select -assert-count 8 t:LUT2
+select -assert-count 3 t:LUT3
+select -assert-count 16 t:RAM128X1D
+
+select -assert-none t:BUFG t:FDRE t:LUT5 t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D
-- 
cgit v1.2.3


From ca7a58bcc8df71425de47fe2684062739fa8d7d1 Mon Sep 17 00:00:00 2001
From: SergeyDegtyar <sndegtyar@gmail.com>
Date: Mon, 9 Sep 2019 08:49:29 +0300
Subject: Add comments for unproven cells.

---
 tests/xilinx_ug901/dynamic_shift_registers_1.ys | 2 +-
 tests/xilinx_ug901/shift_registers_0.ys         | 1 +
 tests/xilinx_ug901/shift_registers_1.ys         | 2 +-
 3 files changed, 3 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/xilinx_ug901/dynamic_shift_registers_1.ys b/tests/xilinx_ug901/dynamic_shift_registers_1.ys
index 994e12a3e..f70c84f2f 100644
--- a/tests/xilinx_ug901/dynamic_shift_registers_1.ys
+++ b/tests/xilinx_ug901/dynamic_shift_registers_1.ys
@@ -2,7 +2,7 @@ read_verilog dynamic_shift_registers_1.v
 hierarchy -top dynamic_shift_register_1
 proc
 flatten
-
+#ERROR: Found 1 unproven $equiv cells in 'equiv_status -assert'.
 #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 
diff --git a/tests/xilinx_ug901/shift_registers_0.ys b/tests/xilinx_ug901/shift_registers_0.ys
index ae7d23a7f..89da1d7cc 100644
--- a/tests/xilinx_ug901/shift_registers_0.ys
+++ b/tests/xilinx_ug901/shift_registers_0.ys
@@ -2,6 +2,7 @@ read_verilog shift_registers_0.v
 hierarchy -top shift_registers_0
 proc
 flatten
+#ERROR: Found 2 unproven $equiv cells in 'equiv_status -assert'.
 #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 
diff --git a/tests/xilinx_ug901/shift_registers_1.ys b/tests/xilinx_ug901/shift_registers_1.ys
index fb935c446..b53b6cb25 100644
--- a/tests/xilinx_ug901/shift_registers_1.ys
+++ b/tests/xilinx_ug901/shift_registers_1.ys
@@ -2,7 +2,7 @@ read_verilog shift_registers_1.v
 hierarchy -top shift_registers_1
 proc
 flatten
-
+#ERROR: Found 2 unproven $equiv cells in 'equiv_status -assert'.
 #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 
-- 
cgit v1.2.3


From 757c476f625bef871f9a4388d4d19bf8c3bc400b Mon Sep 17 00:00:00 2001
From: SergeyDegtyar <sndegtyar@gmail.com>
Date: Tue, 10 Sep 2019 08:08:03 +0300
Subject: Add smoke tests to tests/xilinx

---
 tests/xilinx/add_sub.v   |  13 ++++++
 tests/xilinx/add_sub.ys  |  10 +++++
 tests/xilinx/adffs.v     |  91 ++++++++++++++++++++++++++++++++++++++++++
 tests/xilinx/adffs.ys    |  14 +++++++
 tests/xilinx/alu.v       |  19 +++++++++
 tests/xilinx/alu.ys      |  21 ++++++++++
 tests/xilinx/counter.v   |  17 ++++++++
 tests/xilinx/counter.ys  |  14 +++++++
 tests/xilinx/dffs.v      |  37 ++++++++++++++++++
 tests/xilinx/dffs.ys     |  10 +++++
 tests/xilinx/div_mod.v   |  13 ++++++
 tests/xilinx/div_mod.ys  |  17 ++++++++
 tests/xilinx/fsm.v       |  73 ++++++++++++++++++++++++++++++++++
 tests/xilinx/fsm.ys      |  14 +++++++
 tests/xilinx/latches.v   |   6 +--
 tests/xilinx/latches.ys  |  17 +++++---
 tests/xilinx/logic.v     |  18 +++++++++
 tests/xilinx/logic.ys    |  10 +++++
 tests/xilinx/memory.v    |  21 ++++++++++
 tests/xilinx/memory.ys   |  17 ++++++++
 tests/xilinx/mul.v       |  11 ++++++
 tests/xilinx/mul.ys      |  15 +++++++
 tests/xilinx/mux.v       | 100 +++++++++++++++++++++++++++++++++++++++++++++++
 tests/xilinx/mux.ys      |  10 +++++
 tests/xilinx/run-test.sh |   2 +-
 tests/xilinx/shifter.v   |  22 +++++++++++
 tests/xilinx/shifter.ys  |  11 ++++++
 tests/xilinx/tribuf.v    |  29 ++++++++++++++
 tests/xilinx/tribuf.ys   |  11 ++++++
 29 files changed, 654 insertions(+), 9 deletions(-)
 create mode 100644 tests/xilinx/add_sub.v
 create mode 100644 tests/xilinx/add_sub.ys
 create mode 100644 tests/xilinx/adffs.v
 create mode 100644 tests/xilinx/adffs.ys
 create mode 100644 tests/xilinx/alu.v
 create mode 100644 tests/xilinx/alu.ys
 create mode 100644 tests/xilinx/counter.v
 create mode 100644 tests/xilinx/counter.ys
 create mode 100644 tests/xilinx/dffs.v
 create mode 100644 tests/xilinx/dffs.ys
 create mode 100644 tests/xilinx/div_mod.v
 create mode 100644 tests/xilinx/div_mod.ys
 create mode 100644 tests/xilinx/fsm.v
 create mode 100644 tests/xilinx/fsm.ys
 create mode 100644 tests/xilinx/logic.v
 create mode 100644 tests/xilinx/logic.ys
 create mode 100644 tests/xilinx/memory.v
 create mode 100644 tests/xilinx/memory.ys
 create mode 100644 tests/xilinx/mul.v
 create mode 100644 tests/xilinx/mul.ys
 create mode 100644 tests/xilinx/mux.v
 create mode 100644 tests/xilinx/mux.ys
 create mode 100644 tests/xilinx/shifter.v
 create mode 100644 tests/xilinx/shifter.ys
 create mode 100644 tests/xilinx/tribuf.v
 create mode 100644 tests/xilinx/tribuf.ys

(limited to 'tests')

diff --git a/tests/xilinx/add_sub.v b/tests/xilinx/add_sub.v
new file mode 100644
index 000000000..177c32e30
--- /dev/null
+++ b/tests/xilinx/add_sub.v
@@ -0,0 +1,13 @@
+module top
+(
+ input [3:0] x,
+ input [3:0] y,
+
+ output [3:0] A,
+ output [3:0] B
+ );
+
+assign A =  x + y;
+assign B =  x - y;
+
+endmodule
diff --git a/tests/xilinx/add_sub.ys b/tests/xilinx/add_sub.ys
new file mode 100644
index 000000000..821341f20
--- /dev/null
+++ b/tests/xilinx/add_sub.ys
@@ -0,0 +1,10 @@
+read_verilog add_sub.v
+hierarchy -top top
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 14 t:LUT2
+select -assert-count 6 t:MUXCY
+select -assert-count 8 t:XORCY
+select -assert-none t:LUT2 t:MUXCY t:XORCY %% t:* %D
+
diff --git a/tests/xilinx/adffs.v b/tests/xilinx/adffs.v
new file mode 100644
index 000000000..93c8bf52c
--- /dev/null
+++ b/tests/xilinx/adffs.v
@@ -0,0 +1,91 @@
+module adff
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+			q <= 1'b0;
+		else
+            q <= d;
+endmodule
+
+module adffn
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+			q <= 1'b0;
+		else
+            q <= d;
+endmodule
+
+module dffsr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge pre, posedge clr )
+		if ( clr )
+			q <= 1'b0;
+		else if ( pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module ndffnsnr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk, negedge pre, negedge clr )
+		if ( !clr )
+			q <= 1'b0;
+		else if ( !pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2,b3
+);
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+
+ndffnsnr u_ndffnsnr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b1 )
+    );
+
+adff u_adff (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b2 )
+    );
+
+adffn u_adffn (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b3 )
+    );
+
+endmodule
diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys
new file mode 100644
index 000000000..96d8e176f
--- /dev/null
+++ b/tests/xilinx/adffs.ys
@@ -0,0 +1,14 @@
+read_verilog adffs.v
+proc
+async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock
+flatten
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:BUFG
+select -assert-count 3 t:FDRE
+select -assert-count 1 t:FDRE_1
+select -assert-count 4 t:LUT2
+select -assert-count 4 t:LUT3
+select -assert-none t:BUFG t:FDRE t:FDRE_1 t:LUT2 t:LUT3 %% t:* %D
diff --git a/tests/xilinx/alu.v b/tests/xilinx/alu.v
new file mode 100644
index 000000000..f82cc2e21
--- /dev/null
+++ b/tests/xilinx/alu.v
@@ -0,0 +1,19 @@
+module top (
+	input clock,
+	input [31:0] dinA, dinB,
+	input [2:0] opcode,
+	output reg [31:0] dout
+);
+	always @(posedge clock) begin
+		case (opcode)
+		0: dout <= dinA + dinB;
+		1: dout <= dinA - dinB;
+		2: dout <= dinA >> dinB;
+		3: dout <= $signed(dinA) >>> dinB;
+		4: dout <= dinA << dinB;
+		5: dout <= dinA & dinB;
+		6: dout <= dinA | dinB;
+		7: dout <= dinA ^ dinB;
+		endcase
+	end
+endmodule
diff --git a/tests/xilinx/alu.ys b/tests/xilinx/alu.ys
new file mode 100644
index 000000000..f85f03928
--- /dev/null
+++ b/tests/xilinx/alu.ys
@@ -0,0 +1,21 @@
+read_verilog alu.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+
+select -assert-count 1 t:BUFG
+select -assert-count 32 t:LUT1
+select -assert-count 142 t:LUT2
+select -assert-count 55  t:LUT3
+select -assert-count 70  t:LUT4
+select -assert-count 46  t:LUT5
+select -assert-count 625 t:LUT6
+select -assert-count 62 t:MUXCY
+select -assert-count 265  t:MUXF7
+select -assert-count 79  t:MUXF8
+select -assert-count 64 t:XORCY
+select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
diff --git a/tests/xilinx/counter.v b/tests/xilinx/counter.v
new file mode 100644
index 000000000..52852f8ac
--- /dev/null
+++ b/tests/xilinx/counter.v
@@ -0,0 +1,17 @@
+module top    (
+out,
+clk,
+reset
+);
+    output [7:0] out;
+    input clk, reset;
+    reg [7:0] out;
+
+    always @(posedge clk, posedge reset)
+		if (reset) begin
+			out <= 8'b0 ;
+		end else
+			out <= out + 1;
+
+
+endmodule
diff --git a/tests/xilinx/counter.ys b/tests/xilinx/counter.ys
new file mode 100644
index 000000000..b602b74d7
--- /dev/null
+++ b/tests/xilinx/counter.ys
@@ -0,0 +1,14 @@
+read_verilog counter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:BUFG
+select -assert-count 8 t:FDCE
+select -assert-count 1 t:LUT1
+select -assert-count 7 t:MUXCY
+select -assert-count 8 t:XORCY
+select -assert-none t:BUFG t:FDCE t:LUT1 t:MUXCY t:XORCY %% t:* %D
diff --git a/tests/xilinx/dffs.v b/tests/xilinx/dffs.v
new file mode 100644
index 000000000..d97840c43
--- /dev/null
+++ b/tests/xilinx/dffs.v
@@ -0,0 +1,37 @@
+module dff
+    ( input d, clk, output reg q );
+	always @( posedge clk )
+            q <= d;
+endmodule
+
+module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk )
+		if ( en )
+			q <= d;
+endmodule
+
+module top (
+input clk,
+input en,
+input a,
+output b,b1,
+);
+
+dff u_dff (
+        .clk (clk ),
+        .d (a ),
+        .q (b )
+    );
+
+dffe u_ndffe (
+        .clk (clk ),
+        .en (en),
+        .d (a ),
+        .q (b1 )
+    );
+
+endmodule
diff --git a/tests/xilinx/dffs.ys b/tests/xilinx/dffs.ys
new file mode 100644
index 000000000..6a98994c0
--- /dev/null
+++ b/tests/xilinx/dffs.ys
@@ -0,0 +1,10 @@
+read_verilog dffs.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:BUFG
+select -assert-count 2 t:FDRE
+select -assert-none t:BUFG t:FDRE %% t:* %D
diff --git a/tests/xilinx/div_mod.v b/tests/xilinx/div_mod.v
new file mode 100644
index 000000000..64a36707d
--- /dev/null
+++ b/tests/xilinx/div_mod.v
@@ -0,0 +1,13 @@
+module top
+(
+ input [3:0] x,
+ input [3:0] y,
+
+ output [3:0] A,
+ output [3:0] B
+ );
+
+assign A =  x % y;
+assign B =  x / y;
+
+endmodule
diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys
new file mode 100644
index 000000000..cc00b1a27
--- /dev/null
+++ b/tests/xilinx/div_mod.ys
@@ -0,0 +1,17 @@
+read_verilog div_mod.v
+hierarchy -top top
+flatten
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 12 t:LUT1
+select -assert-count 21 t:LUT2
+select -assert-count 13 t:LUT4
+select -assert-count 6  t:LUT5
+select -assert-count 80 t:LUT6
+select -assert-count 65 t:MUXCY
+select -assert-count 36 t:MUXF7
+select -assert-count 9  t:MUXF8
+select -assert-count 28 t:XORCY
+select -assert-none t:LUT1 t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
diff --git a/tests/xilinx/fsm.v b/tests/xilinx/fsm.v
new file mode 100644
index 000000000..0605bd102
--- /dev/null
+++ b/tests/xilinx/fsm.v
@@ -0,0 +1,73 @@
+ module fsm (
+ clock,
+ reset,
+ req_0,
+ req_1,
+ gnt_0,
+ gnt_1
+ );
+ input   clock,reset,req_0,req_1;
+ output  gnt_0,gnt_1;
+ wire    clock,reset,req_0,req_1;
+ reg     gnt_0,gnt_1;
+
+ parameter SIZE = 3           ;
+ parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
+
+ reg [SIZE-1:0] state;
+ reg [SIZE-1:0] next_state;
+
+ always @ (posedge clock)
+ begin : FSM
+ if (reset == 1'b1) begin
+   state <=  #1  IDLE;
+   gnt_0 <= 0;
+   gnt_1 <= 0;
+ end else
+  case(state)
+    IDLE : if (req_0 == 1'b1) begin
+                 state <=  #1  GNT0;
+                 gnt_0 <= 1;
+               end else if (req_1 == 1'b1) begin
+                 gnt_1 <= 1;
+                 state <=  #1  GNT0;
+               end else begin
+                 state <=  #1  IDLE;
+               end
+    GNT0 : if (req_0 == 1'b1) begin
+                 state <=  #1  GNT0;
+               end else begin
+                 gnt_0 <= 0;
+                 state <=  #1  IDLE;
+               end
+    GNT1 : if (req_1 == 1'b1) begin
+                 state <=  #1  GNT2;
+				 gnt_1 <= req_0;
+               end
+    GNT2 : if (req_0 == 1'b1) begin
+                 state <=  #1  GNT1;
+				 gnt_1 <= req_1;
+               end
+    default : state <=  #1  IDLE;
+ endcase
+ end
+
+ endmodule
+
+ module top (
+input clk,
+input rst,
+input a,
+input b,
+output g0,
+output g1
+);
+
+fsm u_fsm ( .clock(clk),
+            .reset(rst),
+            .req_0(a),
+            .req_1(b),
+            .gnt_0(g0),
+            .gnt_1(g1));
+
+endmodule
diff --git a/tests/xilinx/fsm.ys b/tests/xilinx/fsm.ys
new file mode 100644
index 000000000..3b73891c2
--- /dev/null
+++ b/tests/xilinx/fsm.ys
@@ -0,0 +1,14 @@
+read_verilog fsm.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:BUFG
+select -assert-count 5 t:FDRE
+select -assert-count 1 t:LUT3
+select -assert-count 2 t:LUT4
+select -assert-count 4 t:LUT6
+select -assert-none t:BUFG t:FDRE t:LUT3 t:LUT4 t:LUT6 %% t:* %D
diff --git a/tests/xilinx/latches.v b/tests/xilinx/latches.v
index 83bad7f35..9dc43e4c2 100644
--- a/tests/xilinx/latches.v
+++ b/tests/xilinx/latches.v
@@ -1,19 +1,19 @@
 module latchp
-    ( input d, en, output reg q );
+    ( input d, clk, en, output reg q );
 	always @*
 		if ( en )
 			q <= d;
 endmodule
 
 module latchn
-    ( input d, en, output reg q );
+    ( input d, clk, en, output reg q );
 	always @*
 		if ( !en )
 			q <= d;
 endmodule
 
 module latchsr
-    ( input d, en, clr, pre, output reg q );
+    ( input d, clk, en, clr, pre, output reg q );
 	always @*
 		if ( clr )
 			q <= 1'b0;
diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys
index bd1dffd21..9ab562bcf 100644
--- a/tests/xilinx/latches.ys
+++ b/tests/xilinx/latches.ys
@@ -1,13 +1,20 @@
 read_verilog latches.v
+design -save read
 
 proc
+async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock
 flatten
-equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+synth_xilinx
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+
+design -load read
 
-design -load preopt
 synth_xilinx
-cd top
+#cd top
+
 select -assert-count 1 t:LUT1
 select -assert-count 2 t:LUT3
-select -assert-count 3 t:LDCE
-select -assert-none t:LUT1 t:LUT3 t:LDCE %% t:* %D
+select -assert-count 3 t:$_DLATCH_P_
+#ERROR: Assertion failed: selection is not empty: t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D
+#select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D
diff --git a/tests/xilinx/logic.v b/tests/xilinx/logic.v
new file mode 100644
index 000000000..e5343cae0
--- /dev/null
+++ b/tests/xilinx/logic.v
@@ -0,0 +1,18 @@
+module top
+(
+ input [0:7] in,
+ output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
+ );
+
+   assign     B1 =  in[0] & in[1];
+   assign     B2 =  in[0] | in[1];
+   assign     B3 =  in[0] ~& in[1];
+   assign     B4 =  in[0] ~| in[1];
+   assign     B5 =  in[0] ^ in[1];
+   assign     B6 =  in[0] ~^ in[1];
+   assign     B7 =  ~in[0];
+   assign     B8 =  in[0];
+   assign     B9 =  in[0:1] && in [2:3];
+   assign     B10 =  in[0:1] || in [2:3];
+
+endmodule
diff --git a/tests/xilinx/logic.ys b/tests/xilinx/logic.ys
new file mode 100644
index 000000000..e138ae6a3
--- /dev/null
+++ b/tests/xilinx/logic.ys
@@ -0,0 +1,10 @@
+read_verilog logic.v
+hierarchy -top top
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:LUT1
+select -assert-count 6 t:LUT2
+select -assert-count 2 t:LUT4
+select -assert-none t:LUT1 t:LUT2 t:LUT4 %% t:* %D
diff --git a/tests/xilinx/memory.v b/tests/xilinx/memory.v
new file mode 100644
index 000000000..cb7753f7b
--- /dev/null
+++ b/tests/xilinx/memory.v
@@ -0,0 +1,21 @@
+module top
+(
+	input [7:0] data_a,
+	input [6:1] addr_a,
+	input we_a, clk,
+	output reg [7:0] q_a
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	// Port A
+	always @ (posedge clk)
+	begin
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		q_a <= ram[addr_a];
+	end
+endmodule
diff --git a/tests/xilinx/memory.ys b/tests/xilinx/memory.ys
new file mode 100644
index 000000000..5402513a2
--- /dev/null
+++ b/tests/xilinx/memory.ys
@@ -0,0 +1,17 @@
+read_verilog memory.v
+hierarchy -top top
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+memory
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
+
+design -load postopt
+cd top
+select -assert-count 1 t:BUFG
+select -assert-count 8 t:FDRE
+select -assert-count 8 t:RAM64X1D
+select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D
diff --git a/tests/xilinx/mul.v b/tests/xilinx/mul.v
new file mode 100644
index 000000000..d5b48b1d7
--- /dev/null
+++ b/tests/xilinx/mul.v
@@ -0,0 +1,11 @@
+module top
+(
+ input [5:0] x,
+ input [5:0] y,
+
+ output [11:0] A,
+ );
+
+assign A =  x * y;
+
+endmodule
diff --git a/tests/xilinx/mul.ys b/tests/xilinx/mul.ys
new file mode 100644
index 000000000..ec30c9c2c
--- /dev/null
+++ b/tests/xilinx/mul.ys
@@ -0,0 +1,15 @@
+read_verilog mul.v
+hierarchy -top top
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 12 t:LUT2
+select -assert-count 1  t:LUT3
+select -assert-count 6  t:LUT4
+select -assert-count 1  t:LUT5
+select -assert-count 33 t:LUT6
+select -assert-count 11 t:MUXCY
+select -assert-count 1  t:MUXF7
+select -assert-count 12 t:XORCY
+select -assert-none t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:XORCY %% t:* %D
diff --git a/tests/xilinx/mux.v b/tests/xilinx/mux.v
new file mode 100644
index 000000000..0814b733e
--- /dev/null
+++ b/tests/xilinx/mux.v
@@ -0,0 +1,100 @@
+module mux2 (S,A,B,Y);
+    input S;
+    input A,B;
+    output reg Y;
+
+    always @(*)
+		Y = (S)? B : A;
+endmodule
+
+module mux4 ( S, D, Y );
+
+input[1:0] S;
+input[3:0] D;
+output Y;
+
+reg Y;
+wire[1:0] S;
+wire[3:0] D;
+
+always @*
+begin
+    case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+   endcase
+end
+
+endmodule
+
+module mux8 ( S, D, Y );
+
+input[2:0] S;
+input[7:0] D;
+output Y;
+
+reg Y;
+wire[2:0] S;
+wire[7:0] D;
+
+always @*
+begin
+   case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+       4 : Y = D[4];
+       5 : Y = D[5];
+       6 : Y = D[6];
+       7 : Y = D[7];
+   endcase
+end
+
+endmodule
+
+module mux16 (D, S, Y);
+ 	input  [15:0] D;
+ 	input  [3:0] S;
+ 	output Y;
+
+assign Y = D[S];
+
+endmodule
+
+
+module top (
+input [3:0] S,
+input [15:0] D,
+output M2,M4,M8,M16
+);
+
+mux2 u_mux2 (
+        .S (S[0]),
+        .A (D[0]),
+        .B (D[1]),
+        .Y (M2)
+    );
+
+
+mux4 u_mux4 (
+        .S (S[1:0]),
+        .D (D[3:0]),
+        .Y (M4)
+    );
+
+mux8 u_mux8 (
+        .S (S[2:0]),
+        .D (D[7:0]),
+        .Y (M8)
+    );
+
+mux16 u_mux16 (
+        .S (S[3:0]),
+        .D (D[15:0]),
+        .Y (M16)
+    );
+
+endmodule
diff --git a/tests/xilinx/mux.ys b/tests/xilinx/mux.ys
new file mode 100644
index 000000000..6ecee58f5
--- /dev/null
+++ b/tests/xilinx/mux.ys
@@ -0,0 +1,10 @@
+read_verilog mux.v
+proc
+flatten
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 2  t:LUT3
+select -assert-count 5  t:LUT6
+select -assert-none t:LUT3 t:LUT6 %% t:* %D
diff --git a/tests/xilinx/run-test.sh b/tests/xilinx/run-test.sh
index ea56b70f0..2c72ca3a9 100755
--- a/tests/xilinx/run-test.sh
+++ b/tests/xilinx/run-test.sh
@@ -6,7 +6,7 @@ for x in *.ys; do
 	echo "all:: run-$x"
 	echo "run-$x:"
 	echo "	@echo 'Running $x..'"
-	echo "	@../../yosys -ql ${x%.ys}.log $x"
+	echo "	@../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'"
 done
 for s in *.sh; do
 	if [ "$s" != "run-test.sh" ]; then
diff --git a/tests/xilinx/shifter.v b/tests/xilinx/shifter.v
new file mode 100644
index 000000000..c55632552
--- /dev/null
+++ b/tests/xilinx/shifter.v
@@ -0,0 +1,22 @@
+module top    (
+out,
+clk,
+in
+);
+    output [7:0] out;
+    input signed clk, in;
+    reg signed [7:0] out = 0;
+
+    always @(posedge clk)
+	begin
+`ifndef BUG
+		out    <= out >> 1;
+		out[7] <= in;
+`else
+
+		out    <= out << 1;
+		out[7] <= in;
+`endif
+	end
+
+endmodule
diff --git a/tests/xilinx/shifter.ys b/tests/xilinx/shifter.ys
new file mode 100644
index 000000000..84e16f41e
--- /dev/null
+++ b/tests/xilinx/shifter.ys
@@ -0,0 +1,11 @@
+read_verilog shifter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:BUFG
+select -assert-count 8 t:FDRE
+select -assert-none t:BUFG t:FDRE %% t:* %D
diff --git a/tests/xilinx/tribuf.v b/tests/xilinx/tribuf.v
new file mode 100644
index 000000000..3fa6eb6c6
--- /dev/null
+++ b/tests/xilinx/tribuf.v
@@ -0,0 +1,29 @@
+module tristate (en, i, o);
+    input en;
+    input i;
+    output reg o;
+`ifndef BUG 
+    
+    always @(en or i)
+		o <= (en)? i : 1'bZ;
+`else
+	
+    always @(en or i)
+		o <= (en)? ~i : 1'bZ;
+`endif
+endmodule
+
+
+module top (
+input en,
+input a,
+output b
+);
+
+tristate u_tri (
+        .en (en ),
+        .i (a ),
+        .o (b )
+    );
+
+endmodule
diff --git a/tests/xilinx/tribuf.ys b/tests/xilinx/tribuf.ys
new file mode 100644
index 000000000..fc7ed37ef
--- /dev/null
+++ b/tests/xilinx/tribuf.ys
@@ -0,0 +1,11 @@
+read_verilog tribuf.v
+hierarchy -top top
+proc
+tribuf
+flatten
+synth
+equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:$_TBUF_
+select -assert-none t:$_TBUF_ %% t:* %D
-- 
cgit v1.2.3


From 6331fa5b022b9e16f9392d9604a545f86dc13385 Mon Sep 17 00:00:00 2001
From: SergeyDegtyar <sndegtyar@gmail.com>
Date: Tue, 10 Sep 2019 08:11:56 +0300
Subject: Remove xilinx_ug901 tests (will be moved to yosys-tests)

---
 tests/xilinx_ug901/asym_ram_sdp_read_wider.v       |  74 -------------
 tests/xilinx_ug901/asym_ram_sdp_read_wider.ys      |  22 ----
 tests/xilinx_ug901/asym_ram_sdp_write_wider.v      |  75 -------------
 tests/xilinx_ug901/asym_ram_sdp_write_wider.ys     |  31 ------
 tests/xilinx_ug901/asym_ram_tdp_read_first.v       |  85 --------------
 tests/xilinx_ug901/asym_ram_tdp_read_first.ys      |  21 ----
 tests/xilinx_ug901/asym_ram_tdp_write_first.v      |  92 ----------------
 tests/xilinx_ug901/asym_ram_tdp_write_first.ys     |  29 -----
 tests/xilinx_ug901/black_box_1.v                   |  19 ----
 tests/xilinx_ug901/black_box_1.ys                  |  15 ---
 tests/xilinx_ug901/bytewrite_ram_1b.v              |  42 -------
 tests/xilinx_ug901/bytewrite_ram_1b.ys             |  22 ----
 tests/xilinx_ug901/bytewrite_tdp_ram_nc.v          |  78 -------------
 tests/xilinx_ug901/bytewrite_tdp_ram_nc.ys         |  22 ----
 tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.v  |  71 ------------
 tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.ys |  21 ----
 tests/xilinx_ug901/bytewrite_tdp_ram_rf.v          |  61 -----------
 tests/xilinx_ug901/bytewrite_tdp_ram_rf.ys         |  21 ----
 tests/xilinx_ug901/bytewrite_tdp_ram_wf.v          |  68 ------------
 tests/xilinx_ug901/bytewrite_tdp_ram_wf.ys         |  23 ----
 tests/xilinx_ug901/cmacc.v                         | 122 ---------------------
 tests/xilinx_ug901/cmacc.ys                        |  25 -----
 tests/xilinx_ug901/cmult.v                         |  71 ------------
 tests/xilinx_ug901/cmult.ys                        |  31 ------
 tests/xilinx_ug901/dynamic_shift_registers_1.v     |  21 ----
 tests/xilinx_ug901/dynamic_shift_registers_1.ys    |  15 ---
 tests/xilinx_ug901/dynpreaddmultadd.v              |  47 --------
 tests/xilinx_ug901/dynpreaddmultadd.ys             |  31 ------
 tests/xilinx_ug901/fsm_1.v                         |  42 -------
 tests/xilinx_ug901/fsm_1.ys                        |  16 ---
 tests/xilinx_ug901/latches.v                       |  17 ---
 tests/xilinx_ug901/latches.ys                      |  10 --
 tests/xilinx_ug901/macc.v                          |  47 --------
 tests/xilinx_ug901/macc.ys                         |  23 ----
 tests/xilinx_ug901/mult_unsigned.v                 |  33 ------
 tests/xilinx_ug901/mult_unsigned.ys                |  29 -----
 tests/xilinx_ug901/presubmult.v                    |  43 --------
 tests/xilinx_ug901/presubmult.ys                   |  23 ----
 tests/xilinx_ug901/ram_simple_dual_one_clock.v     |  25 -----
 tests/xilinx_ug901/ram_simple_dual_one_clock.ys    |  20 ----
 tests/xilinx_ug901/ram_simple_dual_two_clocks.v    |  30 -----
 tests/xilinx_ug901/ram_simple_dual_two_clocks.ys   |  20 ----
 tests/xilinx_ug901/rams_dist.v                     |  24 ----
 tests/xilinx_ug901/rams_dist.ys                    |  21 ----
 tests/xilinx_ug901/rams_init_file.data             |  64 -----------
 tests/xilinx_ug901/rams_init_file.v                |  24 ----
 tests/xilinx_ug901/rams_init_file.ys               |  22 ----
 tests/xilinx_ug901/rams_pipeline.v                 |  42 -------
 tests/xilinx_ug901/rams_pipeline.ys                |  22 ----
 tests/xilinx_ug901/rams_sp_nc.v                    |  26 -----
 tests/xilinx_ug901/rams_sp_nc.ys                   |  22 ----
 tests/xilinx_ug901/rams_sp_rf.v                    |  26 -----
 tests/xilinx_ug901/rams_sp_rf.ys                   |  22 ----
 tests/xilinx_ug901/rams_sp_rf_rst.v                |  29 -----
 tests/xilinx_ug901/rams_sp_rf_rst.ys               |  28 -----
 tests/xilinx_ug901/rams_sp_rom.v                   |  46 --------
 tests/xilinx_ug901/rams_sp_rom.ys                  |  22 ----
 tests/xilinx_ug901/rams_sp_rom_1.v                 |  53 ---------
 tests/xilinx_ug901/rams_sp_rom_1.ys                |  22 ----
 tests/xilinx_ug901/rams_sp_wf.v                    |  26 -----
 tests/xilinx_ug901/rams_sp_wf.ys                   |  26 -----
 tests/xilinx_ug901/rams_tdp_rf_rf.v                |  33 ------
 tests/xilinx_ug901/rams_tdp_rf_rf.ys               |  21 ----
 tests/xilinx_ug901/registers_1.v                   |  25 -----
 tests/xilinx_ug901/registers_1.ys                  |  12 --
 tests/xilinx_ug901/run-test.sh                     |  20 ----
 tests/xilinx_ug901/sfir_shifter.v                  |  19 ----
 tests/xilinx_ug901/sfir_shifter.ys                 |  16 ---
 tests/xilinx_ug901/shift_registers_0.v             |  22 ----
 tests/xilinx_ug901/shift_registers_0.ys            |  14 ---
 tests/xilinx_ug901/shift_registers_1.v             |  24 ----
 tests/xilinx_ug901/shift_registers_1.ys            |  14 ---
 tests/xilinx_ug901/squarediffmacc.v                |  52 ---------
 tests/xilinx_ug901/squarediffmacc.ys               |  23 ----
 tests/xilinx_ug901/squarediffmult.v                |  42 -------
 tests/xilinx_ug901/squarediffmult.ys               |  30 -----
 tests/xilinx_ug901/top_mux.v                       |  18 ---
 tests/xilinx_ug901/top_mux.ys                      |  13 ---
 tests/xilinx_ug901/tristates_1.v                   |  17 ---
 tests/xilinx_ug901/tristates_1.ys                  |  13 ---
 tests/xilinx_ug901/tristates_2.v                   |  10 --
 tests/xilinx_ug901/tristates_2.ys                  |  13 ---
 .../xilinx_ultraram_single_port_no_change.v        |  78 -------------
 .../xilinx_ultraram_single_port_no_change.ys       |  25 -----
 .../xilinx_ultraram_single_port_read_first.v       |  78 -------------
 .../xilinx_ultraram_single_port_read_first.ys      |  24 ----
 .../xilinx_ultraram_single_port_write_first.v      |  82 --------------
 .../xilinx_ultraram_single_port_write_first.ys     |  24 ----
 88 files changed, 2962 deletions(-)
 delete mode 100644 tests/xilinx_ug901/asym_ram_sdp_read_wider.v
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(limited to 'tests')

diff --git a/tests/xilinx_ug901/asym_ram_sdp_read_wider.v b/tests/xilinx_ug901/asym_ram_sdp_read_wider.v
deleted file mode 100644
index 0716dffdc..000000000
--- a/tests/xilinx_ug901/asym_ram_sdp_read_wider.v
+++ /dev/null
@@ -1,74 +0,0 @@
-// Asymmetric port RAM
-// Read Wider than Write. Read Statement in loop
-//asym_ram_sdp_read_wider.v
-
-module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA, doB);
-parameter WIDTHA = 4;
-parameter SIZEA = 1024;
-parameter ADDRWIDTHA = 10;
-
-parameter WIDTHB = 16;
-parameter SIZEB = 256;
-parameter ADDRWIDTHB = 8;
-input clkA;
-input clkB;
-input weA;
-input enaA, enaB;
-input [ADDRWIDTHA-1:0] addrA;
-input [ADDRWIDTHB-1:0] addrB;
-input [WIDTHA-1:0] diA;
-output [WIDTHB-1:0] doB;
-`define max(a,b) {(a) > (b) ? (a) : (b)}
-`define min(a,b) {(a) < (b) ? (a) : (b)}
-
-function integer log2;
-input integer value;
-reg [31:0] shifted;
-integer res;
-begin
- if (value < 2)
-  log2 = value;
- else
- begin
-  shifted = value-1;
-  for (res=0; shifted>0; res=res+1)
-   shifted = shifted>>1;
-  log2 = res;
- end
-end
-endfunction
-
-localparam maxSIZE = `max(SIZEA, SIZEB);
-localparam maxWIDTH = `max(WIDTHA, WIDTHB);
-localparam minWIDTH = `min(WIDTHA, WIDTHB);
-
-localparam RATIO = maxWIDTH / minWIDTH;
-localparam log2RATIO = log2(RATIO);
-
-reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
-reg [WIDTHB-1:0] readB;
-
-always @(posedge clkA)
-begin
- if (enaA) begin 
-  if (weA)
-   RAM[addrA] <= diA;
- end  
-end
-
-
-always @(posedge clkB)
-begin : ramread
- integer i;
- reg [log2RATIO-1:0] lsbaddr;
- if (enaB) begin
-  for (i = 0; i < RATIO; i = i+1) begin 
-   lsbaddr = i;
-   readB[(i+1)*minWIDTH-1 -: minWIDTH] <= RAM[{addrB, lsbaddr}];
-  end
- end
-end
-assign doB = readB;
-
-endmodule
-
diff --git a/tests/xilinx_ug901/asym_ram_sdp_read_wider.ys b/tests/xilinx_ug901/asym_ram_sdp_read_wider.ys
deleted file mode 100644
index c63157cdf..000000000
--- a/tests/xilinx_ug901/asym_ram_sdp_read_wider.ys
+++ /dev/null
@@ -1,22 +0,0 @@
-read_verilog asym_ram_sdp_read_wider.v
-hierarchy -top asym_ram_sdp_read_wider
-proc
-memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-memory
-opt -full
-
-# TODO
-#equiv_opt -run prove: -assert null
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
-
-design -load postopt
-cd asym_ram_sdp_read_wider
-stat
-#Vivado synthesizes 1 RAMB18E1.
-select -assert-count 2 t:BUFG
-select -assert-count 1 t:LUT2
-select -assert-count 4 t:RAMB18E1
-
-select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
diff --git a/tests/xilinx_ug901/asym_ram_sdp_write_wider.v b/tests/xilinx_ug901/asym_ram_sdp_write_wider.v
deleted file mode 100644
index 22d12d2ce..000000000
--- a/tests/xilinx_ug901/asym_ram_sdp_write_wider.v
+++ /dev/null
@@ -1,75 +0,0 @@
-// Asymmetric port RAM
-// Write wider than Read. Write Statement in a loop.
-// asym_ram_sdp_write_wider.v
-
-module asym_ram_sdp_write_wider (clkA, clkB, weA, enaA, enaB, addrA, addrB, diA, doB);
-parameter WIDTHB = 4;
-//Default parameters were changed because of slow test
-//parameter SIZEB = 1024;
-//parameter ADDRWIDTHB = 10;
-parameter SIZEB = 256;
-parameter ADDRWIDTHB = 8;
-
-//parameter WIDTHA = 16;
-parameter WIDTHA = 8;
-parameter SIZEA = 256;
-parameter ADDRWIDTHA = 8;
-input clkA;
-input clkB;
-input weA;
-input enaA, enaB;
-input [ADDRWIDTHA-1:0] addrA;
-input [ADDRWIDTHB-1:0] addrB;
-input [WIDTHA-1:0] diA;
-output [WIDTHB-1:0] doB;
-`define max(a,b) {(a) > (b) ? (a) : (b)}
-`define min(a,b) {(a) < (b) ? (a) : (b)}
-
-function integer log2;
-input integer value;
-reg [31:0] shifted;
-integer res;
-begin
- if (value < 2)
-  log2 = value;
- else
- begin
-  shifted = value-1;
-  for (res=0; shifted>0; res=res+1)
-   shifted = shifted>>1;
-  log2 = res;
- end
-end
-endfunction
-
-localparam maxSIZE = `max(SIZEA, SIZEB);
-localparam maxWIDTH = `max(WIDTHA, WIDTHB);
-localparam minWIDTH = `min(WIDTHA, WIDTHB);
-
-localparam RATIO = maxWIDTH / minWIDTH;
-localparam log2RATIO = log2(RATIO);
-
-reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
-reg [WIDTHB-1:0] readB;
-
-always @(posedge clkB) begin
- if (enaB) begin
-  readB <= RAM[addrB];
- end
-end
-assign doB = readB;
-
-always @(posedge clkA)
-begin : ramwrite
- integer i;
- reg [log2RATIO-1:0] lsbaddr;
- for (i=0; i< RATIO; i= i+ 1) begin : write1
-  lsbaddr = i;
-  if (enaA) begin
-   if (weA)
-    RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH];
-  end
- end
-end
-
-endmodule
diff --git a/tests/xilinx_ug901/asym_ram_sdp_write_wider.ys b/tests/xilinx_ug901/asym_ram_sdp_write_wider.ys
deleted file mode 100644
index 229d98df6..000000000
--- a/tests/xilinx_ug901/asym_ram_sdp_write_wider.ys
+++ /dev/null
@@ -1,31 +0,0 @@
-read_verilog asym_ram_sdp_write_wider.v
-hierarchy -top asym_ram_sdp_write_wider
-proc
-memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-memory
-opt -full
-
-# TODO
-#equiv_opt -run prove: -assert null
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
-
-design -load postopt
-cd asym_ram_sdp_write_wider
-stat
-#Vivado synthesizes 1 RAMB18E1.
-select -assert-count 2 t:BUFG
-select -assert-count 1028 t:FDRE
-select -assert-count 170 t:LUT2
-select -assert-count 6 t:LUT3
-select -assert-count 518 t:LUT4
-select -assert-count 10 t:LUT5
-select -assert-count 484 t:LUT6
-select -assert-count 157 t:MUXF7
-select -assert-count 3 t:MUXF8
-
-#RRAM128X1D will be synthesized in case when the parameter WIDTHA=4
-#select -assert-count 8 t:RAM128X1D
-
-select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D
diff --git a/tests/xilinx_ug901/asym_ram_tdp_read_first.v b/tests/xilinx_ug901/asym_ram_tdp_read_first.v
deleted file mode 100644
index 2b807a382..000000000
--- a/tests/xilinx_ug901/asym_ram_tdp_read_first.v
+++ /dev/null
@@ -1,85 +0,0 @@
-// Asymetric RAM - TDP  
-// READ_FIRST MODE.
-// asym_ram_tdp_read_first.v
-
-
-module asym_ram_tdp_read_first (clkA, clkB, enaA, weA, enaB, weB, addrA, addrB, diA, doA, diB, doB);
-parameter WIDTHB = 4;
-parameter SIZEB = 1024;
-parameter ADDRWIDTHB = 10;
-parameter WIDTHA = 16;
-parameter SIZEA = 256;
-parameter ADDRWIDTHA = 8;
-input clkA;
-input clkB;
-input weA, weB;
-input enaA, enaB;
-
-input [ADDRWIDTHA-1:0] addrA;
-input [ADDRWIDTHB-1:0] addrB;
-input [WIDTHA-1:0] diA;
-input [WIDTHB-1:0] diB;
-
-output [WIDTHA-1:0] doA;
-output [WIDTHB-1:0] doB;
-
-`define max(a,b) {(a) > (b) ? (a) : (b)}
-`define min(a,b) {(a) < (b) ? (a) : (b)}
-
-function integer log2;
-input integer value;
-reg [31:0] shifted;
-integer res;
-begin
- if (value < 2)
-  log2 = value;
- else
- begin
-  shifted = value-1;
-  for (res=0; shifted>0; res=res+1)
-   shifted = shifted>>1;
-  log2 = res;
- end
-end
-endfunction
-
-localparam maxSIZE = `max(SIZEA, SIZEB);
-localparam maxWIDTH = `max(WIDTHA, WIDTHB);
-localparam minWIDTH = `min(WIDTHA, WIDTHB);
-
-localparam RATIO = maxWIDTH / minWIDTH;
-localparam log2RATIO = log2(RATIO);
-
-reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
-reg [WIDTHA-1:0] readA;
-reg [WIDTHB-1:0] readB;
-
-always @(posedge clkB)
-begin
- if (enaB) begin
-  readB <= RAM[addrB] ;
-  if (weB)
-   RAM[addrB] <= diB;
- end  
-end
-
-
-always @(posedge clkA)
-begin : portA
- integer i;
- reg [log2RATIO-1:0] lsbaddr ;
-  for (i=0; i< RATIO; i= i+ 1) begin 
-   lsbaddr = i;
-  if (enaA) begin
-   readA[(i+1)*minWIDTH -1 -: minWIDTH] <= RAM[{addrA, lsbaddr}];
-
-   if (weA)
-    RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH];
-  end
- end
-end
-
-assign doA = readA;
-assign doB = readB;
-
-endmodule
diff --git a/tests/xilinx_ug901/asym_ram_tdp_read_first.ys b/tests/xilinx_ug901/asym_ram_tdp_read_first.ys
deleted file mode 100644
index 5f96b800c..000000000
--- a/tests/xilinx_ug901/asym_ram_tdp_read_first.ys
+++ /dev/null
@@ -1,21 +0,0 @@
-read_verilog asym_ram_tdp_read_first.v
-hierarchy -top asym_ram_tdp_read_first
-proc
-memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-memory
-opt -full
-
-# TODO
-#equiv_opt -run prove: -assert null
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
-
-design -load postopt
-cd asym_ram_tdp_read_first
-stat
-#Vivado synthesizes 1 RAMB18E1.
-select -assert-count 1 t:$mem
-select -assert-count 2 t:LUT2
-
-select -assert-none t:$mem t:LUT2 %% t:* %D
diff --git a/tests/xilinx_ug901/asym_ram_tdp_write_first.v b/tests/xilinx_ug901/asym_ram_tdp_write_first.v
deleted file mode 100644
index 90187ea26..000000000
--- a/tests/xilinx_ug901/asym_ram_tdp_write_first.v
+++ /dev/null
@@ -1,92 +0,0 @@
-// Asymmetric port RAM - TDP
-// WRITE_FIRST MODE.
-// asym_ram_tdp_write_first.v
-
-
-module asym_ram_tdp_write_first (clkA, clkB, enaA, weA, enaB, weB, addrA, addrB, diA, doA, diB, doB);
-parameter WIDTHB = 4;
-//Default parameters were changed because of slow test
-//parameter SIZEB = 1024;
-//parameter ADDRWIDTHB = 10;
-parameter SIZEB = 32;
-parameter ADDRWIDTHB = 8;
-
-//parameter WIDTHA = 16;
-parameter WIDTHA = 4;
-//parameter SIZEA = 256;
-parameter SIZEA = 32;
-parameter ADDRWIDTHA = 8;
-input clkA;
-input clkB;
-input weA, weB;
-input enaA, enaB;
-
-input [ADDRWIDTHA-1:0] addrA;
-input [ADDRWIDTHB-1:0] addrB;
-input [WIDTHA-1:0] diA;
-input [WIDTHB-1:0] diB;
-
-output [WIDTHA-1:0] doA;
-output [WIDTHB-1:0] doB;
-
-`define max(a,b) {(a) > (b) ? (a) : (b)}
-`define min(a,b) {(a) < (b) ? (a) : (b)}
-
-function integer log2;
-input integer value;
-reg [31:0] shifted;
-integer res;
-begin
- if (value < 2)
-  log2 = value;
- else
- begin
-  shifted = value-1;
-  for (res=0; shifted>0; res=res+1)
-   shifted = shifted>>1;
-  log2 = res;
- end
-end
-endfunction
-
-localparam maxSIZE = `max(SIZEA, SIZEB);
-localparam maxWIDTH = `max(WIDTHA, WIDTHB);
-localparam minWIDTH = `min(WIDTHA, WIDTHB);
-
-localparam RATIO = maxWIDTH / minWIDTH;
-localparam log2RATIO = log2(RATIO);
-
-reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
-reg [WIDTHA-1:0] readA;
-reg [WIDTHB-1:0] readB;
-
-always @(posedge clkB)
-begin
- if (enaB) begin
-  if (weB)
-   RAM[addrB] = diB;
-  readB = RAM[addrB] ;
- end
-end
-
-
-always @(posedge clkA)
-begin : portA
- integer i;
- reg [log2RATIO-1:0] lsbaddr ;
-  for (i=0; i< RATIO; i= i+ 1) begin
-   lsbaddr = i;
-   if (enaA) begin
-
-   if (weA)
-    RAM[{addrA, lsbaddr}] = diA[(i+1)*minWIDTH-1 -: minWIDTH];
-
-   readA[(i+1)*minWIDTH -1 -: minWIDTH] = RAM[{addrA, lsbaddr}];
-  end
- end
-end
-
-assign doA = readA;
-assign doB = readB;
-
-endmodule
diff --git a/tests/xilinx_ug901/asym_ram_tdp_write_first.ys b/tests/xilinx_ug901/asym_ram_tdp_write_first.ys
deleted file mode 100644
index bbe3cc849..000000000
--- a/tests/xilinx_ug901/asym_ram_tdp_write_first.ys
+++ /dev/null
@@ -1,29 +0,0 @@
-read_verilog asym_ram_tdp_write_first.v
-hierarchy -top asym_ram_tdp_write_first
-proc
-memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-memory
-opt -full
-
-# TODO
-#equiv_opt -run prove: -assert null
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
-
-design -load postopt
-cd asym_ram_tdp_write_first
-stat
-#Vivado synthesizes 1 RAMB18E1.
-select -assert-count 2 t:BUFG
-select -assert-count 200 t:FDRE
-select -assert-count 10 t:LUT2
-select -assert-count 44 t:LUT3
-select -assert-count 81 t:LUT4
-select -assert-count 104 t:LUT5
-select -assert-count 560 t:LUT6
-select -assert-count 261 t:MUXF7
-select -assert-count 127 t:MUXF8
-
-
-select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D
diff --git a/tests/xilinx_ug901/black_box_1.v b/tests/xilinx_ug901/black_box_1.v
deleted file mode 100644
index 40caa1b10..000000000
--- a/tests/xilinx_ug901/black_box_1.v
+++ /dev/null
@@ -1,19 +0,0 @@
-// Black Box
-// black_box_1.v
-// 
-(* black_box *) module black_box1 (in1, in2, dout);
-input in1, in2;
-output dout;
-endmodule
-
-module black_box_1 (DI_1, DI_2, DOUT);
-input DI_1, DI_2;
-output DOUT;
-
-black_box1 U1 (
-                .in1(DI_1),
-                .in2(DI_2),
-                .dout(DOUT)
-              );
-
-endmodule
diff --git a/tests/xilinx_ug901/black_box_1.ys b/tests/xilinx_ug901/black_box_1.ys
deleted file mode 100644
index acf0b5761..000000000
--- a/tests/xilinx_ug901/black_box_1.ys
+++ /dev/null
@@ -1,15 +0,0 @@
-read_verilog black_box_1.v
-hierarchy -top black_box_1
-proc
-tribuf
-flatten
-synth
-#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd black_box_1 # Constrain all select calls below inside the top module
-#Vivado synthesizes 1 black box.
-#stat
-#select -assert-count 0 t:LUT1
-#select -assert-count 1 t:$_TBUF_
-#select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D
diff --git a/tests/xilinx_ug901/bytewrite_ram_1b.v b/tests/xilinx_ug901/bytewrite_ram_1b.v
deleted file mode 100644
index 46d86c297..000000000
--- a/tests/xilinx_ug901/bytewrite_ram_1b.v
+++ /dev/null
@@ -1,42 +0,0 @@
-// Single-Port BRAM with Byte-wide Write Enable
-// Read-First mode
-// Single-process description
-// Compact description of the write with a generate-for 
-//   statement
-// Column width and number of columns easily configurable
-//
-// bytewrite_ram_1b.v
-//
-
-module bytewrite_ram_1b (clk, we, addr, di, do);
-
-parameter SIZE = 1024; 
-parameter ADDR_WIDTH = 10; 
-parameter COL_WIDTH = 8; 
-parameter NB_COL = 4;
-
-input clk;
-input [NB_COL-1:0] we;
-input [ADDR_WIDTH-1:0] addr;
-input [NB_COL*COL_WIDTH-1:0] di;
-output reg [NB_COL*COL_WIDTH-1:0] do;
-
-reg [NB_COL*COL_WIDTH-1:0] RAM [SIZE-1:0];
-
-always @(posedge clk)
-begin
-    do <= RAM[addr];
-end
-
-generate genvar i;
-for (i = 0; i < NB_COL; i = i+1)
-begin
-always @(posedge clk)
-begin
-    if (we[i])
-        RAM[addr][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= di[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
-    end 
-end
-endgenerate
-
-endmodule
diff --git a/tests/xilinx_ug901/bytewrite_ram_1b.ys b/tests/xilinx_ug901/bytewrite_ram_1b.ys
deleted file mode 100644
index 4f0967801..000000000
--- a/tests/xilinx_ug901/bytewrite_ram_1b.ys
+++ /dev/null
@@ -1,22 +0,0 @@
-read_verilog bytewrite_ram_1b.v
-hierarchy -top bytewrite_ram_1b
-proc
-memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-memory
-opt -full
-
-# TODO
-#equiv_opt -run prove: -assert null
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
-
-design -load postopt
-cd bytewrite_ram_1b
-stat
-#Vivado synthesizes 1 RAMB36E1.
-select -assert-count 1 t:BUFG
-select -assert-count 32 t:LUT2
-select -assert-count 8 t:RAMB36E1
-
-select -assert-none t:BUFG t:LUT2 t:RAMB36E1 %% t:* %D
diff --git a/tests/xilinx_ug901/bytewrite_tdp_ram_nc.v b/tests/xilinx_ug901/bytewrite_tdp_ram_nc.v
deleted file mode 100644
index 1093b0838..000000000
--- a/tests/xilinx_ug901/bytewrite_tdp_ram_nc.v
+++ /dev/null
@@ -1,78 +0,0 @@
-//
-// True-Dual-Port BRAM with Byte-wide Write Enable
-//      No-Change mode
-//
-// bytewrite_tdp_ram_nc.v
-//
-// ByteWide Write Enable, - NO_CHANGE mode template - Vivado recomended
-module bytewrite_tdp_ram_nc
-  #(
-    //---------------------------------------------------------------
-    parameter   NUM_COL                 =   4,
-    parameter   COL_WIDTH               =   8,
-    parameter   ADDR_WIDTH              =  10, // Addr  Width in bits : 2**ADDR_WIDTH = RAM Depth
-    parameter   DATA_WIDTH              =  NUM_COL*COL_WIDTH  // Data  Width in bits
-    //---------------------------------------------------------------
-    ) (
-       input clkA,
-       input enaA, 
-       input [NUM_COL-1:0] weA,
-       input [ADDR_WIDTH-1:0] addrA,
-       input [DATA_WIDTH-1:0] dinA,
-       output reg [DATA_WIDTH-1:0] doutA,
-       
-       input clkB,
-       input enaB,
-       input [NUM_COL-1:0] weB,
-       input [ADDR_WIDTH-1:0] addrB,
-       input [DATA_WIDTH-1:0] dinB,
-       output reg [DATA_WIDTH-1:0] doutB
-       );
-
-   
-   // Core Memory  
-   reg [DATA_WIDTH-1:0]            ram_block [(2**ADDR_WIDTH)-1:0];
-   
-   // Port-A Operation
-   generate
-      genvar                       i;
-      for(i=0;i<NUM_COL;i=i+1) begin
-         always @ (posedge clkA) begin
-            if(enaA) begin
-               if(weA[i]) begin
-                  ram_block[addrA][i*COL_WIDTH +: COL_WIDTH] <= dinA[i*COL_WIDTH +: COL_WIDTH];
-               end
-            end
-         end
-      end
-   endgenerate
-   
-   always @ (posedge clkA) begin
-      if(enaA) begin
-         if (~|weA)
-           doutA <= ram_block[addrA];
-      end
-   end
-   
-   
-   // Port-B Operation:
-   generate
-      for(i=0;i<NUM_COL;i=i+1) begin
-         always @ (posedge clkB) begin
-            if(enaB) begin
-               if(weB[i]) begin
-                  ram_block[addrB][i*COL_WIDTH +: COL_WIDTH] <= dinB[i*COL_WIDTH +: COL_WIDTH];
-               end
-            end
-         end
-      end
-   endgenerate
-   
-   always @ (posedge clkB) begin
-      if(enaB) begin
-         if (~|weB)
-           doutB <= ram_block[addrB];
-      end
-   end
-   
-endmodule // bytewrite_tdp_ram_nc
diff --git a/tests/xilinx_ug901/bytewrite_tdp_ram_nc.ys b/tests/xilinx_ug901/bytewrite_tdp_ram_nc.ys
deleted file mode 100644
index b6818e322..000000000
--- a/tests/xilinx_ug901/bytewrite_tdp_ram_nc.ys
+++ /dev/null
@@ -1,22 +0,0 @@
-read_verilog bytewrite_tdp_ram_nc.v
-hierarchy -top bytewrite_tdp_ram_nc
-proc
-memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-memory
-opt -full
-
-# TODO
-#equiv_opt -run prove: -assert null
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
-
-design -load postopt
-cd bytewrite_tdp_ram_nc
-stat
-#Vivado synthesizes 1 RAMB36E1.
-select -assert-count 1 t:$mem
-select -assert-count 8 t:LUT2
-select -assert-count 64 t:LUT3
-select -assert-count 2 t:LUT5
-select -assert-none t:LUT2 t:LUT3 t:LUT5 t:$mem %% t:* %D
diff --git a/tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.v b/tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.v
deleted file mode 100644
index 349aa2aec..000000000
--- a/tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.v
+++ /dev/null
@@ -1,71 +0,0 @@
-// ByteWide Write Enable, - Alternate READ_FIRST mode template - Vivado recomended
-// bytewrite_tdp_ram_readfirst2.v
-module bytewrite_tdp_ram_readfirst2
-  #(
-    //-------------------------------------------------------------------------
-    parameter   NUM_COL                 =   4,
-    parameter   COL_WIDTH               =   8,
-    parameter   ADDR_WIDTH              =  10, // Addr  Width in bits : 2**ADDR_WIDTH = RAM Depth
-    parameter   DATA_WIDTH              =  NUM_COL*COL_WIDTH  // Data  Width in bits
-    //-------------------------------------------------------------------------
-    ) (
-       input clkA,
-       input enaA, 
-       input [NUM_COL-1:0] weA,
-       input [ADDR_WIDTH-1:0] addrA,
-       input [DATA_WIDTH-1:0] dinA,
-       output reg [DATA_WIDTH-1:0] doutA,
-       
-       input clkB,
-       input enaB,
-       input [NUM_COL-1:0] weB,
-       input [ADDR_WIDTH-1:0] addrB,
-       input [DATA_WIDTH-1:0] dinB,
-       output reg [DATA_WIDTH-1:0] doutB
-       );
-   
-   
-   // Core Memory  
-   reg [DATA_WIDTH-1:0]            ram_block [(2**ADDR_WIDTH)-1:0];
-   
-   // Port-A Operation
-   generate
-      genvar                       i;
-      for(i=0;i<NUM_COL;i=i+1) begin
-         always @ (posedge clkA) begin
-            if(enaA) begin
-               if(weA[i]) begin
-                  ram_block[addrA][i*COL_WIDTH +: COL_WIDTH] <= dinA[i*COL_WIDTH +: COL_WIDTH];
-               end
-            end
-         end
-      end
-   endgenerate
-   
-   always @ (posedge clkA) begin
-      if(enaA) begin
-         doutA <= ram_block[addrA];
-      end
-   end
-   
-   
-   // Port-B Operation:
-   generate
-      for(i=0;i<NUM_COL;i=i+1) begin
-         always @ (posedge clkB) begin
-            if(enaB) begin
-               if(weB[i]) begin
-                  ram_block[addrB][i*COL_WIDTH +: COL_WIDTH] <= dinB[i*COL_WIDTH +: COL_WIDTH];
-               end
-            end
-         end
-      end
-   endgenerate
-   
-   always @ (posedge clkB) begin
-      if(enaB) begin
-         doutB <= ram_block[addrB];
-      end
-   end
-
-endmodule // bytewrite_tdp_ram_readfirst2
diff --git a/tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.ys b/tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.ys
deleted file mode 100644
index 3273d0d43..000000000
--- a/tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.ys
+++ /dev/null
@@ -1,21 +0,0 @@
-read_verilog bytewrite_tdp_ram_readfirst2.v
-hierarchy -top bytewrite_tdp_ram_readfirst2
-proc
-memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-memory
-opt -full
-
-# TODO
-#equiv_opt -run prove: -assert null
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
-
-design -load postopt
-cd bytewrite_tdp_ram_readfirst2
-stat
-#Vivado synthesizes 1 RAMB36E1.
-select -assert-count 1 t:$mem
-select -assert-count 8 t:LUT2
-select -assert-count 64 t:LUT3
-select -assert-none t:LUT2 t:LUT3 t:$mem %% t:* %D
diff --git a/tests/xilinx_ug901/bytewrite_tdp_ram_rf.v b/tests/xilinx_ug901/bytewrite_tdp_ram_rf.v
deleted file mode 100644
index 72dad9d8f..000000000
--- a/tests/xilinx_ug901/bytewrite_tdp_ram_rf.v
+++ /dev/null
@@ -1,61 +0,0 @@
-// True-Dual-Port BRAM with Byte-wide Write Enable
-//      Read-First mode 
-// bytewrite_tdp_ram_rf.v
-//
-
-module bytewrite_tdp_ram_rf
- #(
-//--------------------------------------------------------------------------
-parameter   NUM_COL             =   4,
-parameter   COL_WIDTH           =   8,
-parameter   ADDR_WIDTH          =  10, 
-// Addr  Width in bits : 2 *ADDR_WIDTH = RAM Depth
-parameter   DATA_WIDTH      =  NUM_COL*COL_WIDTH  // Data  Width in bits
-    //----------------------------------------------------------------------
-  ) (
-     input clkA,
-     input enaA, 
-     input [NUM_COL-1:0] weA,
-     input [ADDR_WIDTH-1:0] addrA,
-     input [DATA_WIDTH-1:0] dinA,
-     output reg [DATA_WIDTH-1:0] doutA,
-
-     input clkB,
-     input enaB,
-     input [NUM_COL-1:0] weB,
-     input [ADDR_WIDTH-1:0] addrB,
-     input [DATA_WIDTH-1:0] dinB,
-     output reg [DATA_WIDTH-1:0] doutB
-     );
-
-
-   // Core Memory  
-   reg [DATA_WIDTH-1:0]   ram_block [(2**ADDR_WIDTH)-1:0];
-
-   integer                i;
-   // Port-A Operation
-   always @ (posedge clkA) begin
-      if(enaA) begin
-         for(i=0;i<NUM_COL;i=i+1) begin
-            if(weA[i]) begin
-               ram_block[addrA][i*COL_WIDTH +: COL_WIDTH] <= dinA[i*COL_WIDTH +: COL_WIDTH];
-            end
-         end
-         doutA <= ram_block[addrA];  
-      end
-   end
-
-   // Port-B Operation:
-   always @ (posedge clkB) begin
-      if(enaB) begin
-         for(i=0;i<NUM_COL;i=i+1) begin
-            if(weB[i]) begin
-               ram_block[addrB][i*COL_WIDTH +: COL_WIDTH] <= dinB[i*COL_WIDTH +: COL_WIDTH];
-            end
-         end     
-         
-         doutB <= ram_block[addrB];  
-      end
-   end
-
-endmodule // bytewrite_tdp_ram_rf
diff --git a/tests/xilinx_ug901/bytewrite_tdp_ram_rf.ys b/tests/xilinx_ug901/bytewrite_tdp_ram_rf.ys
deleted file mode 100644
index 2a34d9abe..000000000
--- a/tests/xilinx_ug901/bytewrite_tdp_ram_rf.ys
+++ /dev/null
@@ -1,21 +0,0 @@
-read_verilog bytewrite_tdp_ram_rf.v
-hierarchy -top bytewrite_tdp_ram_rf
-proc
-memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-memory
-opt -full
-
-# TODO
-#equiv_opt -run prove: -assert null
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
-
-design -load postopt
-cd bytewrite_tdp_ram_rf
-stat
-#Vivado synthesizes 1 RAMB36E1.
-select -assert-count 1 t:$mem
-select -assert-count 8 t:LUT2
-select -assert-count 64 t:LUT3
-select -assert-none t:LUT2 t:LUT3 t:$mem %% t:* %D
diff --git a/tests/xilinx_ug901/bytewrite_tdp_ram_wf.v b/tests/xilinx_ug901/bytewrite_tdp_ram_wf.v
deleted file mode 100644
index d39565e52..000000000
--- a/tests/xilinx_ug901/bytewrite_tdp_ram_wf.v
+++ /dev/null
@@ -1,68 +0,0 @@
-// True-Dual-Port BRAM with Byte-wide Write Enable
-//      Write-First mode
-// File: HDL_Coding_Techniques/rams/bytewrite_tdp_ram_wf.v
-//
-// ByteWide Write Enable, - WRITE_FIRST mode template - Vivado recomended
-module bytewrite_tdp_ram_wf
-  #(
-    //----------------------------------------------------------------------
-parameter   NUM_COL         =   4,
-parameter   COL_WIDTH       =   8,
-parameter   ADDR_WIDTH      =  10, 
-// Addr  Width in bits : 2**ADDR_WIDTH = RAM Depth
-parameter   DATA_WIDTH      =  NUM_COL*COL_WIDTH  // Data  Width in bits
-    //----------------------------------------------------------------------
-    ) (
-       input clkA,
-       input enaA, 
-       input [NUM_COL-1:0] weA,
-       input [ADDR_WIDTH-1:0] addrA,
-       input [DATA_WIDTH-1:0] dinA,
-       output reg [DATA_WIDTH-1:0] doutA,
-       
-       input clkB,
-       input enaB,
-       input [NUM_COL-1:0] weB,
-       input [ADDR_WIDTH-1:0] addrB,
-       input [DATA_WIDTH-1:0] dinB,
-       output reg [DATA_WIDTH-1:0] doutB
-       );
-   
-   
-   // Core Memory  
-   reg [DATA_WIDTH-1:0]            ram_block [(2**ADDR_WIDTH)-1:0];
-   
-   // Port-A Operation
-   generate
-      genvar                       i;
-      for(i=0;i<NUM_COL;i=i+1) begin
-         always @ (posedge clkA) begin
-            if(enaA) begin
-               if(weA[i]) begin
-                  ram_block[addrA][i*COL_WIDTH +: COL_WIDTH] <= dinA[i*COL_WIDTH +: COL_WIDTH];
-                  doutA[i*COL_WIDTH +: COL_WIDTH]  <= dinA[i*COL_WIDTH +: COL_WIDTH] ;
-               end else begin
-                  doutA[i*COL_WIDTH +: COL_WIDTH]  <= ram_block[addrA][i*COL_WIDTH +: COL_WIDTH] ;
-               end
-            end
-         end
-      end
-   endgenerate
-   
-   // Port-B Operation:
-   generate
-      for(i=0;i<NUM_COL;i=i+1) begin
-         always @ (posedge clkB) begin
-            if(enaB) begin
-               if(weB[i]) begin
-                  ram_block[addrB][i*COL_WIDTH +: COL_WIDTH] <= dinB[i*COL_WIDTH +: COL_WIDTH];
-                  doutB[i*COL_WIDTH +: COL_WIDTH]  <= dinB[i*COL_WIDTH +: COL_WIDTH] ;
-               end else begin 
-                  doutB[i*COL_WIDTH +: COL_WIDTH]  <= ram_block[addrB][i*COL_WIDTH +: COL_WIDTH] ;
-               end
-            end     
-         end
-      end
-   endgenerate
-   
-endmodule // bytewrite_tdp_ram_wf
diff --git a/tests/xilinx_ug901/bytewrite_tdp_ram_wf.ys b/tests/xilinx_ug901/bytewrite_tdp_ram_wf.ys
deleted file mode 100644
index b681d0c2b..000000000
--- a/tests/xilinx_ug901/bytewrite_tdp_ram_wf.ys
+++ /dev/null
@@ -1,23 +0,0 @@
-read_verilog bytewrite_tdp_ram_wf.v
-hierarchy -top bytewrite_tdp_ram_wf
-proc
-memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-memory
-opt -full
-
-# TODO
-#equiv_opt -run prove: -assert null
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
-
-design -load postopt
-cd bytewrite_tdp_ram_wf
-stat
-#Vivado synthesizes 1 RAMB36E1.
-select -assert-count 1 t:$mem
-select -assert-count 2 t:BUFG
-select -assert-count 64 t:FDRE
-select -assert-count 8 t:LUT2
-select -assert-count 128 t:LUT3
-select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:$mem %% t:* %D
diff --git a/tests/xilinx_ug901/cmacc.v b/tests/xilinx_ug901/cmacc.v
deleted file mode 100644
index 038402daf..000000000
--- a/tests/xilinx_ug901/cmacc.v
+++ /dev/null
@@ -1,122 +0,0 @@
-// Complex Multiplier with accumulation (pr+i.pi) = (ar+i.ai)*(br+i.bi)
-// File: cmacc.v
-// The RTL below describes a complex multiplier with accumulation
-// which can be packed into 3 DSP blocks (Ultrascale architecture)
-//Default parameters were changed because of slow test
-//module cmacc # (parameter AWIDTH = 16, BWIDTH = 18, SIZEOUT = 40)
-module cmacc # (parameter AWIDTH = 4, BWIDTH = 5, SIZEOUT = 9)
-  (
-   input clk,
-   input sload,
-   input signed [AWIDTH-1:0] ar,
-   input signed [AWIDTH-1:0] ai,
-  input signed [BWIDTH-1:0]   br,
-  input signed [BWIDTH-1:0]   bi,
-  output signed [SIZEOUT-1:0] pr,
-  output signed [SIZEOUT-1:0] pi);
-
-  reg signed [AWIDTH-1:0]  ai_d, ai_dd, ai_ddd, ai_dddd;
-  reg signed [AWIDTH-1:0] ar_d, ar_dd, ar_ddd, ar_dddd;
-  reg signed [BWIDTH-1:0] bi_d, bi_dd, bi_ddd, br_d, br_dd, br_ddd;
-  reg signed [AWIDTH:0] addcommon;
-  reg signed [BWIDTH:0] addr, addi;
-  reg signed [AWIDTH+BWIDTH:0] mult0, multr, multi;
-  reg signed [SIZEOUT-1:0] pr_int, pi_int, old_result_real, old_result_im;
-  reg signed [AWIDTH+BWIDTH:0] common, commonr1, commonr2;
-
-  reg sload_reg;
-
- `ifdef SIM
-  initial
-  begin
-    ai_d = 0;
-    ai_dd = 0;
-    ai_ddd = 0;
-    ai_dddd = 0;
-    ar_d = 0;
-    ar_dd = 0;
-    ar_ddd = 0;
-    ar_dddd = 0;
-    bi_d = 0;
-    bi_dd = 0;
-    bi_ddd = 0;
-    br_d = 0;
-    br_dd = 0;
-    br_ddd = 0;
-  end
- `endif
-
-  always @(posedge clk)
-  begin
-    ar_d      <= ar;
-    ar_dd     <= ar_d;
-    ai_d      <= ai;
-    ai_dd     <= ai_d;
-    br_d      <= br;
-    br_dd     <= br_d;
-    br_ddd    <= br_dd;
-    bi_d      <= bi;
-    bi_dd     <= bi_d;
-    bi_ddd    <= bi_dd;
-    sload_reg <= sload;
-  end
-
-  // Common factor (ar ai) x bi, shared for the calculations of the real and imaginary final products
-  //
-  always @(posedge clk)
-  begin
-    addcommon <= ar_d - ai_d;
-    mult0     <= addcommon * bi_dd;
-    common    <= mult0;
-  end
-
-  // Accumulation loop (combinatorial) for *Real*
-  //
-  always @(sload_reg or pr_int)
-  if (sload_reg)
-  old_result_real <= 0;
-  else
-  // 'sload' is now and opens the accumulation loop.
-  // The accumulator takes the next multiplier output
-  // in the same cycle.
-  old_result_real <= pr_int;
-
-  // Real product
-  //
-  always @(posedge clk)
-  begin
-    ar_ddd   <= ar_dd;
-    ar_dddd  <= ar_ddd;
-    addr     <= br_ddd - bi_ddd;
-    multr    <= addr * ar_dddd;
-    commonr1 <= common;
-    pr_int   <= multr + commonr1 + old_result_real;
-  end
-
-  // Accumulation loop (combinatorial) for *Imaginary*
-  //
-  always @(sload_reg or pi_int)
-  if (sload_reg)
-  old_result_im <= 0;
-  else
-  // 'sload' is now and opens the accumulation loop.
-  // The accumulator takes the next multiplier output
-  // in the same cycle.
-  old_result_im <= pi_int;
-
-  // Imaginary product
-  //
-  always @(posedge clk)
-  begin
-    ai_ddd   <= ai_dd;
-    ai_dddd  <= ai_ddd;
-    addi     <= br_ddd + bi_ddd;
-    multi    <= addi * ai_dddd;
-    commonr2 <= common;
-    pi_int   <= multi + commonr2 + old_result_im;
-  end
-
-  assign pr = pr_int;
-  assign pi = pi_int;
-
-endmodule // cmacc
diff --git a/tests/xilinx_ug901/cmacc.ys b/tests/xilinx_ug901/cmacc.ys
deleted file mode 100644
index c1ac931c8..000000000
--- a/tests/xilinx_ug901/cmacc.ys
+++ /dev/null
@@ -1,25 +0,0 @@
-read_verilog cmacc.v
-hierarchy -top cmacc
-proc
-flatten
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-
-cd cmacc
-#Vivado synthesizes 5 DSP48E1, 32 FDRE, 18 LUT.
-stat
-select -assert-count 1 t:BUFG
-select -assert-count 77 t:FDRE
-select -assert-count 5 t:LUT1
-select -assert-count 46 t:LUT2
-select -assert-count 25 t:LUT3
-select -assert-count 8 t:LUT4
-select -assert-count 16 t:LUT5
-select -assert-count 85 t:LUT6
-select -assert-count 54 t:MUXCY
-select -assert-count 8 t:MUXF7
-select -assert-count 2 t:MUXF8
-select -assert-count 22 t:SRL16E
-select -assert-count 62 t:XORCY
-
-select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:SRL16E t:XORCY %% t:* %D
diff --git a/tests/xilinx_ug901/cmult.v b/tests/xilinx_ug901/cmult.v
deleted file mode 100644
index d5d85a28c..000000000
--- a/tests/xilinx_ug901/cmult.v
+++ /dev/null
@@ -1,71 +0,0 @@
-//
-// Complex Multiplier (pr+i.pi) = (ar+i.ai)*(br+i.bi)
-// file: cmult.v
-
-module cmult # (parameter AWIDTH = 16, BWIDTH = 18)
-   (
-    input clk,
-    input signed [AWIDTH-1:0]      ar, ai,
-    input signed [BWIDTH-1:0]      br, bi,
-    output signed [AWIDTH+BWIDTH:0] pr, pi
-   );
-
-reg signed [AWIDTH-1:0] ai_d, ai_dd, ai_ddd, ai_dddd   ; 
-reg signed [AWIDTH-1:0] ar_d, ar_dd, ar_ddd, ar_dddd   ; 
-reg signed [BWIDTH-1:0] bi_d, bi_dd, bi_ddd, br_d, br_dd, br_ddd ; 
-reg signed [AWIDTH:0]  addcommon     ; 
-reg signed [BWIDTH:0]  addr, addi     ; 
-reg signed [AWIDTH+BWIDTH:0] mult0, multr, multi, pr_int, pi_int  ; 
-reg signed [AWIDTH+BWIDTH:0] common, commonr1, commonr2   ; 
-  
-always @(posedge clk)
- begin
-  ar_d   <= ar;
-  ar_dd  <= ar_d;
-  ai_d   <= ai;
-  ai_dd  <= ai_d;
-  br_d   <= br;
-  br_dd  <= br_d;
-  br_ddd <= br_dd;
-  bi_d   <= bi;
-  bi_dd  <= bi_d;
-  bi_ddd <= bi_dd;
- end
- 
-// Common factor (ar ai) x bi, shared for the calculations of the real and imaginary final products
-// 
-always @(posedge clk)
- begin
-  addcommon <= ar_d - ai_d;
-  mult0     <= addcommon * bi_dd;
-  common    <= mult0;
- end
-
-// Real product
-//
-always @(posedge clk)
- begin
-   ar_ddd   <= ar_dd;
-   ar_dddd  <= ar_ddd;
-   addr     <= br_ddd - bi_ddd;
-   multr    <= addr * ar_dddd;
-   commonr1 <= common;
-   pr_int   <= multr + commonr1;
- end
-
-// Imaginary product
-//
-always @(posedge clk)
- begin
-  ai_ddd   <= ai_dd;
-  ai_dddd  <= ai_ddd;
-  addi     <= br_ddd + bi_ddd;
-  multi    <= addi * ai_dddd;
-  commonr2 <= common;
-  pi_int   <= multi + commonr2;
- end
-
-assign pr = pr_int;
-assign pi = pi_int;
-   
-endmodule // cmult
diff --git a/tests/xilinx_ug901/cmult.ys b/tests/xilinx_ug901/cmult.ys
deleted file mode 100644
index 605f00983..000000000
--- a/tests/xilinx_ug901/cmult.ys
+++ /dev/null
@@ -1,31 +0,0 @@
-read_verilog cmult.v
-hierarchy -top cmult
-proc
-memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-memory
-opt -full
-
-# TODO
-#equiv_opt -run prove: -assert null
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
-
-design -load postopt
-cd cmult
-#Vivado synthesizes 3 DSP48E1, 68 FDRE.
-select -assert-count 1 t:BUFG
-select -assert-count 281 t:FDRE
-select -assert-count 18 t:LUT1
-select -assert-count 467 t:LUT2
-select -assert-count 187 t:LUT3
-select -assert-count 98 t:LUT4
-select -assert-count 165 t:LUT5
-select -assert-count 1596 t:LUT6
-select -assert-count 222 t:MUXCY
-select -assert-count 393 t:MUXF7
-select -assert-count 121 t:MUXF8
-select -assert-count 85 t:SRL16E
-select -assert-count 230 t:XORCY
-
-select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:SRL16E t:XORCY %% t:* %D
diff --git a/tests/xilinx_ug901/dynamic_shift_registers_1.v b/tests/xilinx_ug901/dynamic_shift_registers_1.v
deleted file mode 100644
index b69c022cd..000000000
--- a/tests/xilinx_ug901/dynamic_shift_registers_1.v
+++ /dev/null
@@ -1,21 +0,0 @@
-// 32-bit dynamic shift register.
-// Download: 
-// File: dynamic_shift_registers_1.v
-
-module dynamic_shift_register_1 (CLK, CE, SEL, SI, DO);
-parameter SELWIDTH = 5;
-input CLK, CE, SI;
-input [SELWIDTH-1:0] SEL;
-output DO;
-
-localparam DATAWIDTH = 2**SELWIDTH;
-reg [DATAWIDTH-1:0] data;
-
-assign DO = data[SEL];
-
-always @(posedge CLK)
- begin
-  if (CE == 1'b1)
-    data <= {data[DATAWIDTH-2:0], SI};
-  end 
-endmodule
diff --git a/tests/xilinx_ug901/dynamic_shift_registers_1.ys b/tests/xilinx_ug901/dynamic_shift_registers_1.ys
deleted file mode 100644
index f70c84f2f..000000000
--- a/tests/xilinx_ug901/dynamic_shift_registers_1.ys
+++ /dev/null
@@ -1,15 +0,0 @@
-read_verilog dynamic_shift_registers_1.v
-hierarchy -top dynamic_shift_register_1
-proc
-flatten
-#ERROR: Found 1 unproven $equiv cells in 'equiv_status -assert'.
-#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd dynamic_shift_register_1 # Constrain all select calls below inside the top module
-#Vivado synthesizes 1 BUFG, 3 SRLC32E.
-stat
-select -assert-count 1 t:BUFG
-select -assert-count 1 t:SRLC32E
-select -assert-none t:BUFG t:SRLC32E %% t:* %D
diff --git a/tests/xilinx_ug901/dynpreaddmultadd.v b/tests/xilinx_ug901/dynpreaddmultadd.v
deleted file mode 100644
index e3bb3a86c..000000000
--- a/tests/xilinx_ug901/dynpreaddmultadd.v
+++ /dev/null
@@ -1,47 +0,0 @@
-// Pre-add/subtract select with Dynamic control
-// dynpreaddmultadd.v
-//Default parameters were changed because of slow test.
-//module dynpreaddmultadd  # (parameter SIZEIN = 16)
-module dynpreaddmultadd  # (parameter SIZEIN = 8)
-        (
-          input clk, ce, rst, subadd,
-          input  signed [SIZEIN-1:0] a, b, c, d,
-          output signed [2*SIZEIN:0] dynpreaddmultadd_out
-        );
-
-// Declare registers for intermediate values
-reg signed [SIZEIN-1:0] a_reg, b_reg, c_reg;
-reg signed [SIZEIN:0]   add_reg;
-reg signed [2*SIZEIN:0] d_reg, m_reg, p_reg;
-
-always @(posedge clk)
-begin
- if (rst)
-  begin
-   a_reg   <= 0;
-   b_reg   <= 0;
-   c_reg   <= 0;
-   d_reg   <= 0;
-   add_reg <= 0;
-   m_reg   <= 0;
-   p_reg   <= 0;
-  end
- else if (ce)
-  begin
-   a_reg   <= a;
-   b_reg   <= b;
-   c_reg   <= c;
-   d_reg   <= d;
-   if (subadd)
-    add_reg <= a_reg - b_reg;
-   else
-    add_reg <= a_reg + b_reg;
-   m_reg   <= add_reg * c_reg;
-   p_reg   <= m_reg + d_reg;
-  end
-end
-
-// Output accumulation result
-assign dynpreaddmultadd_out = p_reg;
-
-endmodule // dynpreaddmultadd
diff --git a/tests/xilinx_ug901/dynpreaddmultadd.ys b/tests/xilinx_ug901/dynpreaddmultadd.ys
deleted file mode 100644
index f74128dae..000000000
--- a/tests/xilinx_ug901/dynpreaddmultadd.ys
+++ /dev/null
@@ -1,31 +0,0 @@
-read_verilog dynpreaddmultadd.v
-hierarchy -top dynpreaddmultadd
-proc
-memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-memory
-opt -full
-
-# TODO
-#equiv_opt -run prove: -assert null
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
-
-design -load postopt
-cd dynpreaddmultadd
-
-#Vivado synthesizes 1 DSP48E1.
-select -assert-count 1 t:BUFG
-select -assert-count 75 t:FDRE
-select -assert-count 8 t:LUT1
-select -assert-count 131 t:LUT2
-select -assert-count 19 t:LUT3
-select -assert-count 26 t:LUT4
-select -assert-count 12 t:LUT5
-select -assert-count 142 t:LUT6
-select -assert-count 48 t:MUXCY
-select -assert-count 50 t:MUXF7
-select -assert-count 15 t:MUXF8
-select -assert-count 52 t:XORCY
-
-select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
diff --git a/tests/xilinx_ug901/fsm_1.v b/tests/xilinx_ug901/fsm_1.v
deleted file mode 100644
index ee3571d0d..000000000
--- a/tests/xilinx_ug901/fsm_1.v
+++ /dev/null
@@ -1,42 +0,0 @@
-// State Machine with single sequential block
-//fsm_1.v
-module fsm_1(clk,reset,flag,sm_out);
-input clk,reset,flag;
-output reg sm_out;
-
-parameter s1 = 3'b000;
-parameter s2 = 3'b001;
-parameter s3 = 3'b010;
-parameter s4 = 3'b011;
-parameter s5 = 3'b111;
-
-reg [2:0] state;
-
-always@(posedge clk)
-  begin
-    if(reset)
-      begin
-        state <= s1;
-        sm_out  <= 1'b1;
-      end
-  else
-    begin
-     case(state)
-       s1: if(flag) 
-            begin 
-              state <= s2; 
-              sm_out <= 1'b1; 
-            end
-           else
-            begin
-              state <= s3;
-              sm_out <= 1'b0;
-            end
-       s2: begin state <= s4; sm_out <= 1'b0; end
-       s3: begin state <= s4; sm_out <= 1'b0; end
-       s4: begin state <= s5; sm_out <= 1'b1; end
-       s5: begin state <= s1; sm_out <= 1'b1; end
-     endcase
-    end
- end
-endmodule
diff --git a/tests/xilinx_ug901/fsm_1.ys b/tests/xilinx_ug901/fsm_1.ys
deleted file mode 100644
index 192966163..000000000
--- a/tests/xilinx_ug901/fsm_1.ys
+++ /dev/null
@@ -1,16 +0,0 @@
-read_verilog fsm_1.v
-hierarchy -top fsm_1
-proc
-flatten
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd fsm_1 # Constrain all select calls below inside the top module
-#Vivado synthesizes 2 LUT5, 2 LUT4, 1 LUT3, 4 FDRE.
-stat
-select -assert-count 1 t:BUFG
-select -assert-count 4 t:FDRE
-select -assert-count 2 t:LUT4
-select -assert-count 2 t:LUT5
-select -assert-count 1 t:LUT6
-
-select -assert-none t:BUFG t:FDRE t:LUT4 t:LUT5 t:LUT6 %% t:* %D
diff --git a/tests/xilinx_ug901/latches.v b/tests/xilinx_ug901/latches.v
deleted file mode 100644
index 09d0f9f73..000000000
--- a/tests/xilinx_ug901/latches.v
+++ /dev/null
@@ -1,17 +0,0 @@
-// Latch with Positive Gate and Asynchronous Reset
-// File: latches.v
-module latches (
-                input G,
-                input D,
-                input CLR,
-                output reg Q
-               );
-always @ *
-begin
- if(CLR)
-  Q = 0;
- else if(G)
-  Q = D;
-end
-
-endmodule               
diff --git a/tests/xilinx_ug901/latches.ys b/tests/xilinx_ug901/latches.ys
deleted file mode 100644
index be4a8de94..000000000
--- a/tests/xilinx_ug901/latches.ys
+++ /dev/null
@@ -1,10 +0,0 @@
-read_verilog latches.v
-proc
-hierarchy -top latches
-flatten
-synth_xilinx
-#Vivado synthesizes 1 BUFG, 8 LDCE.
-select -assert-count 2 t:LUT2
-select -assert-count 1 t:$_DLATCH_P_
-#ERROR: Assertion failed: selection is not empty: t:LUT2 t:$_DLATCH_P_ %% t:* %D
-#select -assert-none t:LUT2 t:$_DLATCH_P_ %% t:* %D
diff --git a/tests/xilinx_ug901/macc.v b/tests/xilinx_ug901/macc.v
deleted file mode 100644
index 9db8ea2c9..000000000
--- a/tests/xilinx_ug901/macc.v
+++ /dev/null
@@ -1,47 +0,0 @@
-// Signed 40-bit streaming accumulator with 16-bit inputs
-// File: macc.v
-//
-module macc  # (
-				//Default parameters were changed because of slow test
-               // parameter SIZEIN = 16, SIZEOUT = 40
-               // parameter SIZEIN = 12, SIZEOUT = 30
-                parameter SIZEIN = 8, SIZEOUT = 20
-               )
-               (
-                input clk, ce, sload,
-                input signed  [SIZEIN-1:0]  a, b,
-                output signed [SIZEOUT-1:0] accum_out
-               );
-
-   // Declare registers for intermediate values
-reg signed [SIZEIN-1:0]  a_reg, b_reg;
-reg                      sload_reg;
-reg signed [2*SIZEIN:0]  mult_reg;
-reg signed [SIZEOUT-1:0] adder_out, old_result;
-
-always @(adder_out or sload_reg)
-begin
-  if (sload_reg)
-    old_result <= 0;
-  else
-   // 'sload' is now active (=low) and opens the accumulation loop.
-   // The accumulator takes the next multiplier output in
-   // the same cycle.
-    old_result <= adder_out;
-end
-
-always @(posedge clk)
- if (ce)
-   begin
-      a_reg <= a;
-      b_reg <= b;
-      mult_reg <= a_reg * b_reg;
-      sload_reg <= sload;
-      // Store accumulation result into a register
-      adder_out <= old_result + mult_reg;
-   end
-
-// Output accumulation result
-assign accum_out = adder_out;
-
-endmodule // macc
diff --git a/tests/xilinx_ug901/macc.ys b/tests/xilinx_ug901/macc.ys
deleted file mode 100644
index 5a78a352c..000000000
--- a/tests/xilinx_ug901/macc.ys
+++ /dev/null
@@ -1,23 +0,0 @@
-read_verilog macc.v
-hierarchy -top macc
-proc
-flatten
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-
-cd macc
-#Vivado synthesizes 1 DSP48E1, 1 FDRE. (When SIZEIN = 12, SIZEOUT = 30)
-stat
-select -assert-count 1 t:BUFG
-select -assert-count 53 t:FDRE
-select -assert-count 64 t:LUT2
-select -assert-count 10 t:LUT3
-select -assert-count 22 t:LUT4
-select -assert-count 14 t:LUT5
-select -assert-count 123 t:LUT6
-select -assert-count 34 t:MUXCY
-select -assert-count 41 t:MUXF7
-select -assert-count 14 t:MUXF8
-select -assert-count 36 t:XORCY
-
-select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
diff --git a/tests/xilinx_ug901/mult_unsigned.v b/tests/xilinx_ug901/mult_unsigned.v
deleted file mode 100644
index 466c16cf8..000000000
--- a/tests/xilinx_ug901/mult_unsigned.v
+++ /dev/null
@@ -1,33 +0,0 @@
-// Unsigned 16x24-bit Multiplier
-// 1 latency stage on operands
-// 3 latency stage after the multiplication
-// File: multipliers2.v
-//
-module mult_unsigned (clk, A, B, RES);
-//Default parameters were changed because of slow test
-//parameter WIDTHA = 16;
-//parameter WIDTHB = 24;
-parameter WIDTHA = 8;
-parameter WIDTHB = 12;
-input clk;
-input [WIDTHA-1:0] A;
-input [WIDTHB-1:0] B;
-output [WIDTHA+WIDTHB-1:0] RES;
-
-reg [WIDTHA-1:0] rA;
-reg [WIDTHB-1:0] rB;
-reg [WIDTHA+WIDTHB-1:0] M [3:0];
-
-integer i;
-always @(posedge clk)
- begin
-  rA <= A;
-  rB <= B;
-  M[0] <= rA * rB;
-  for (i = 0; i < 3; i = i+1)
-    M[i+1] <= M[i];
- end
-
-assign RES = M[3];
-
-endmodule
diff --git a/tests/xilinx_ug901/mult_unsigned.ys b/tests/xilinx_ug901/mult_unsigned.ys
deleted file mode 100644
index a929ca3ad..000000000
--- a/tests/xilinx_ug901/mult_unsigned.ys
+++ /dev/null
@@ -1,29 +0,0 @@
-read_verilog mult_unsigned.v
-hierarchy -top mult_unsigned
-proc
-memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-memory
-opt -full
-
-# TODO
-#equiv_opt -run prove: -assert null
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
-
-design -load postopt
-cd mult_unsigned
-
-#Vivado synthesizes 1 DSP48E1, 40 FDRE.
-select -assert-count 1 t:BUFG
-select -assert-count 20 t:FDRE
-select -assert-count 33 t:LUT2
-select -assert-count 1 t:LUT3
-select -assert-count 11 t:LUT4
-select -assert-count 4 t:LUT5
-select -assert-count 139 t:LUT6
-select -assert-count 19 t:MUXCY
-select -assert-count 35 t:MUXF7
-select -assert-count 20 t:SRL16E
-select -assert-count 20 t:XORCY
-select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:SRL16E t:XORCY %% t:* %D
diff --git a/tests/xilinx_ug901/presubmult.v b/tests/xilinx_ug901/presubmult.v
deleted file mode 100644
index 30e6133ff..000000000
--- a/tests/xilinx_ug901/presubmult.v
+++ /dev/null
@@ -1,43 +0,0 @@
-//
-// Pre-adder support in subtract mode for DSP block
-// File: presubmult.v
-
-module presubmult  # (//Default parameters were changed because of slow test
-					// parameter SIZEIN = 16
-                      parameter SIZEIN = 8
-                     )
-                     (
-                      input clk, ce, rst,
-                      input  signed [SIZEIN-1:0] a, b, c,
-                      output signed [2*SIZEIN:0] presubmult_out
-                     );
-
-// Declare registers for intermediate values
-reg signed [SIZEIN-1:0] a_reg, b_reg, c_reg;
-reg signed [SIZEIN:0]   add_reg;
-reg signed [2*SIZEIN:0] m_reg, p_reg;
-
-always @(posedge clk)
- if (rst)
-  begin
-     a_reg   <= 0;
-     b_reg   <= 0;
-     c_reg   <= 0;
-     add_reg <= 0;
-     m_reg   <= 0;
-     p_reg   <= 0;
-  end
- else if (ce)
-  begin
-     a_reg   <= a;
-     b_reg   <= b;
-     c_reg   <= c;
-     add_reg <= a - b;
-     m_reg   <= add_reg * c_reg;
-     p_reg   <= m_reg;
-  end
-
-// Output accumulation result
-assign presubmult_out = p_reg;
-
-endmodule // presubmult
diff --git a/tests/xilinx_ug901/presubmult.ys b/tests/xilinx_ug901/presubmult.ys
deleted file mode 100644
index 831458dec..000000000
--- a/tests/xilinx_ug901/presubmult.ys
+++ /dev/null
@@ -1,23 +0,0 @@
-read_verilog presubmult.v
-hierarchy -top presubmult
-proc
-flatten
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-
-cd presubmult
-#Vivado synthesizes 1 DSP48E1. (When SIZEIN = 8)
-stat
-select -assert-count 1 t:BUFG
-select -assert-count 51 t:FDRE
-select -assert-count 75 t:LUT2
-select -assert-count 10 t:LUT3
-select -assert-count 24 t:LUT4
-select -assert-count 15 t:LUT5
-select -assert-count 136 t:LUT6
-select -assert-count 24 t:MUXCY
-select -assert-count 46 t:MUXF7
-select -assert-count 14 t:MUXF8
-select -assert-count 26 t:XORCY
-
-select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
diff --git a/tests/xilinx_ug901/ram_simple_dual_one_clock.v b/tests/xilinx_ug901/ram_simple_dual_one_clock.v
deleted file mode 100644
index 3390e2da5..000000000
--- a/tests/xilinx_ug901/ram_simple_dual_one_clock.v
+++ /dev/null
@@ -1,25 +0,0 @@
-// Simple Dual-Port Block RAM with One Clock
-// File: simple_dual_one_clock.v
-
-module simple_dual_one_clock (clk,ena,enb,wea,addra,addrb,dia,dob);
-
-input clk,ena,enb,wea;
-input [9:0] addra,addrb;
-input [15:0] dia;
-output [15:0] dob;
-reg [15:0] ram [1023:0];
-reg [15:0] doa,dob;
-
-always @(posedge clk) begin 
- if (ena) begin
-    if (wea)
-        ram[addra] <= dia;
- end
-end
-
-always @(posedge clk) begin 
-  if (enb)
-    dob <= ram[addrb];
-end
-
-endmodule
\ No newline at end of file
diff --git a/tests/xilinx_ug901/ram_simple_dual_one_clock.ys b/tests/xilinx_ug901/ram_simple_dual_one_clock.ys
deleted file mode 100644
index c1bde951e..000000000
--- a/tests/xilinx_ug901/ram_simple_dual_one_clock.ys
+++ /dev/null
@@ -1,20 +0,0 @@
-read_verilog ram_simple_dual_one_clock.v
-hierarchy -top simple_dual_one_clock
-proc
-memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-memory
-opt -full
-
-# TODO
-#equiv_opt -run prove: -assert null
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
-design -load postopt
-cd simple_dual_one_clock
-#Vivado synthesizes 1 RAMB18E1.
-select -assert-count 1 t:BUFG
-select -assert-count 1 t:LUT2
-select -assert-count 1 t:RAMB18E1
-
-select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
diff --git a/tests/xilinx_ug901/ram_simple_dual_two_clocks.v b/tests/xilinx_ug901/ram_simple_dual_two_clocks.v
deleted file mode 100644
index 1113b928e..000000000
--- a/tests/xilinx_ug901/ram_simple_dual_two_clocks.v
+++ /dev/null
@@ -1,30 +0,0 @@
-// Simple Dual-Port Block RAM with Two Clocks
-// File: simple_dual_two_clocks.v
-
-module simple_dual_two_clocks (clka,clkb,ena,enb,wea,addra,addrb,dia,dob);
-
-input clka,clkb,ena,enb,wea;
-input [9:0] addra,addrb;
-input [15:0] dia;
-output [15:0] dob;
-reg [15:0] ram [1023:0];
-reg [15:0] dob;
-
-always @(posedge clka) 
-begin 
-  if (ena)
-    begin
-      if (wea)
-        ram[addra] <= dia;
-    end
-end
-
-always @(posedge clkb) 
-begin
-  if (enb)
-    begin
-      dob <= ram[addrb];
-    end
-end
-
-endmodule
diff --git a/tests/xilinx_ug901/ram_simple_dual_two_clocks.ys b/tests/xilinx_ug901/ram_simple_dual_two_clocks.ys
deleted file mode 100644
index db0d789e9..000000000
--- a/tests/xilinx_ug901/ram_simple_dual_two_clocks.ys
+++ /dev/null
@@ -1,20 +0,0 @@
-read_verilog ram_simple_dual_two_clocks.v
-hierarchy -top simple_dual_two_clocks
-proc
-memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-memory
-opt -full
-
-# TODO
-#equiv_opt -run prove: -assert null
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
-design -load postopt
-cd simple_dual_two_clocks
-#Vivado synthesizes 1 RAMB18E1.
-select -assert-count 2 t:BUFG
-select -assert-count 1 t:LUT2
-select -assert-count 1 t:RAMB18E1
-
-select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
diff --git a/tests/xilinx_ug901/rams_dist.v b/tests/xilinx_ug901/rams_dist.v
deleted file mode 100644
index 405283b69..000000000
--- a/tests/xilinx_ug901/rams_dist.v
+++ /dev/null
@@ -1,24 +0,0 @@
-// Dual-Port RAM with Asynchronous Read (Distributed RAM)
-// File: rams_dist.v
-
-module rams_dist (clk, we, a, dpra, di, spo, dpo);
-
-input clk;
-input we;
-input [5:0] a;
-input [5:0] dpra;
-input [15:0] di;
-output [15:0] spo;
-output [15:0] dpo;
-reg [15:0] ram [63:0];
-
-always @(posedge clk) 
-begin 
- if (we)
-   ram[a] <= di;
-end
-
-assign spo = ram[a];
-assign dpo = ram[dpra];
-
-endmodule
diff --git a/tests/xilinx_ug901/rams_dist.ys b/tests/xilinx_ug901/rams_dist.ys
deleted file mode 100644
index 0aa1a8309..000000000
--- a/tests/xilinx_ug901/rams_dist.ys
+++ /dev/null
@@ -1,21 +0,0 @@
-read_verilog rams_dist.v
-hierarchy -top rams_dist
-proc
-memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-memory
-opt -full
-
-# TODO
-#equiv_opt -run prove: -assert null
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
-
-design -load postopt
-cd rams_dist
-stat
-#Vivado synthesizes 32 RAM64X1D.
-select -assert-count 1 t:BUFG
-select -assert-count 32 t:RAM64X1D
-
-select -assert-none t:BUFG t:RAM64X1D %% t:* %D
diff --git a/tests/xilinx_ug901/rams_init_file.data b/tests/xilinx_ug901/rams_init_file.data
deleted file mode 100644
index f14f0b324..000000000
--- a/tests/xilinx_ug901/rams_init_file.data
+++ /dev/null
@@ -1,64 +0,0 @@
-00001110110000011001111011000110
-00101011001011010101001000100011
-01110100010100011000011100001111
-01000001010000100101001110010100
-00001001101001111111101000101011
-00101101001011111110101010100111
-11101111000100111000111101101101
-10001111010010011001000011101111
-00000001100011100011110010011111
-11011111001110101011111001001010
-11100111010100111110110011001010
-11000100001001101100111100101001
-10001011100101011111111111100001
-11110101110110010000010110111010
-01001011000000111001010110101110
-11100001111111001010111010011110
-01101111011010010100001101110001
-01010100011011111000011000100100
-11110000111101101111001100001011
-10101101001111010100100100011100
-01011100001010111111101110101110
-01011101000100100111010010110101
-11110111000100000101011101101101
-11100111110001111010101100001101
-01110100000011101111111000011111
-00010011110101111000111001011101
-01101110001111100011010101101111
-10111100000000010011101011011011
-11000001001101001101111100010000
-00011111110010110110011111010101
-01100100100000011100100101110000
-10001000000100111011001010001111
-11001000100011101001010001100001
-10000000100111010011100111100011
-11011111010010100010101010000111
-10000000110111101000111110111011
-10110011010111101111000110011001
-00010111100001001010110111011100
-10011100101110101111011010110011
-01010011101101010001110110011010
-01111011011100010101000101000001
-10001000000110010110111001101010
-11101000001101010000111001010110
-11100011111100000111110101110101
-01001010000000001111111101101111
-00100011000011001000000010001111
-10011000111010110001001011100100
-11111111111011110101000101000111
-11000011000101000011100110100000
-01101101001011111010100011101001
-10000111101100101001110011010111
-11010110100100101110110010100100
-01001111111001101101011111001011
-11011001001101110110000100110111
-10110110110111100101110011100110
-10011100111001000010111111010110
-00000000001011011111001010110010
-10100110011010000010001000011011
-11001010111111001001110001110101
-00100001100010000111000101001000
-00111100101111110001101101111010
-11000010001010000000010100100001
-11000001000110001101000101001110
-10010011010100010001100100100111
diff --git a/tests/xilinx_ug901/rams_init_file.v b/tests/xilinx_ug901/rams_init_file.v
deleted file mode 100644
index 046779af9..000000000
--- a/tests/xilinx_ug901/rams_init_file.v
+++ /dev/null
@@ -1,24 +0,0 @@
-// Initializing Block RAM from external data file
-// Binary data
-// File: rams_init_file.v 
-
-module rams_init_file (clk, we, addr, din, dout);
-input clk;
-input we;
-input [5:0] addr;
-input [31:0] din;
-output [31:0] dout;
-
-reg [31:0] ram [0:63];
-reg [31:0] dout;
-
-initial begin
-$readmemb("rams_init_file.data",ram);
-end
-
-always @(posedge clk)
-begin
-  if (we)
-     ram[addr] <= din;
-  dout <= ram[addr];
-end endmodule
diff --git a/tests/xilinx_ug901/rams_init_file.ys b/tests/xilinx_ug901/rams_init_file.ys
deleted file mode 100644
index d22a0f52c..000000000
--- a/tests/xilinx_ug901/rams_init_file.ys
+++ /dev/null
@@ -1,22 +0,0 @@
-read_verilog rams_init_file.v
-hierarchy -top rams_init_file
-proc
-memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-memory
-opt -full
-
-# TODO
-#equiv_opt -run prove: -assert null
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
-
-design -load postopt
-cd rams_init_file
-stat
-#Vivado synthesizes 1 RAMB18E1.
-select -assert-count 1 t:BUFG
-select -assert-count 32 t:FDRE
-select -assert-count 32 t:RAM64X1D
-
-select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D
diff --git a/tests/xilinx_ug901/rams_pipeline.v b/tests/xilinx_ug901/rams_pipeline.v
deleted file mode 100644
index e86d417f5..000000000
--- a/tests/xilinx_ug901/rams_pipeline.v
+++ /dev/null
@@ -1,42 +0,0 @@
-// Block RAM with Optional Output Registers
-// File: rams_pipeline
-
-module rams_pipeline (clk1, clk2, we, en1, en2, addr1, addr2, di, res1, res2);
-input clk1;
-input clk2;
-input we, en1, en2;
-input [9:0] addr1;
-input [9:0] addr2;
-input [15:0] di;
-output [15:0] res1;
-output [15:0] res2;
-reg [15:0] res1;
-reg [15:0] res2;
-reg [15:0] RAM [1023:0];
-reg [15:0] do1;
-reg [15:0] do2;
-
-always @(posedge clk1)
-begin
-    if (we == 1'b1)
-        RAM[addr1] <= di;
-    do1 <= RAM[addr1];
-end
-
-always @(posedge clk2)
-begin
-    do2 <= RAM[addr2];
-end
-
-always @(posedge clk1)
-begin
-    if (en1 == 1'b1)
-        res1 <= do1;
-end
-
-always @(posedge clk2)
-begin
-    if (en2 == 1'b1)
-        res2 <= do2;
-end 
-endmodule
diff --git a/tests/xilinx_ug901/rams_pipeline.ys b/tests/xilinx_ug901/rams_pipeline.ys
deleted file mode 100644
index 7fd7c76e4..000000000
--- a/tests/xilinx_ug901/rams_pipeline.ys
+++ /dev/null
@@ -1,22 +0,0 @@
-read_verilog rams_pipeline.v
-hierarchy -top rams_pipeline
-proc
-memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-memory
-opt -full
-
-# TODO
-#equiv_opt -run prove: -assert null
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
-
-design -load postopt
-cd rams_pipeline
-stat
-#Vivado synthesizes 1 RAMB18E1.
-select -assert-count 2 t:BUFG
-select -assert-count 32 t:FDRE
-select -assert-count 2 t:RAMB18E1
-
-select -assert-none t:BUFG t:FDRE t:RAMB18E1 %% t:* %D
diff --git a/tests/xilinx_ug901/rams_sp_nc.v b/tests/xilinx_ug901/rams_sp_nc.v
deleted file mode 100644
index 08abc0d2c..000000000
--- a/tests/xilinx_ug901/rams_sp_nc.v
+++ /dev/null
@@ -1,26 +0,0 @@
-// Single-Port Block RAM No-Change Mode
-// File: rams_sp_nc.v
-
-module rams_sp_nc (clk, we, en, addr, di, dout);
-
-input clk; 
-input we; 
-input en;
-input [9:0] addr; 
-input [15:0] di; 
-output [15:0] dout;
-
-reg [15:0] RAM [1023:0];
-reg [15:0] dout;
-
-always @(posedge clk)
-begin
-  if (en)
-  begin
-    if (we)
-      RAM[addr] <= di;
-    else
-      dout <= RAM[addr];
-  end
-end
-endmodule
diff --git a/tests/xilinx_ug901/rams_sp_nc.ys b/tests/xilinx_ug901/rams_sp_nc.ys
deleted file mode 100644
index 9b7d6386f..000000000
--- a/tests/xilinx_ug901/rams_sp_nc.ys
+++ /dev/null
@@ -1,22 +0,0 @@
-read_verilog rams_sp_nc.v
-hierarchy -top rams_sp_nc
-proc
-memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-memory
-opt -full
-
-# TODO
-#equiv_opt -run prove: -assert null
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
-
-design -load postopt
-cd rams_sp_nc
-stat
-#Vivado synthesizes 1 RAMB18E1.
-select -assert-count 1 t:BUFG
-select -assert-count 2 t:LUT2
-select -assert-count 1 t:RAMB18E1
-
-select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
diff --git a/tests/xilinx_ug901/rams_sp_rf.v b/tests/xilinx_ug901/rams_sp_rf.v
deleted file mode 100644
index 5e0adf88b..000000000
--- a/tests/xilinx_ug901/rams_sp_rf.v
+++ /dev/null
@@ -1,26 +0,0 @@
-// Single-Port Block RAM Read-First Mode
-// rams_sp_rf.v
-module rams_sp_rf (clk, en, we, addr, di, dout);
-
-input clk; 
-input we; 
-input en;
-input [9:0] addr; 
-input [15:0] di; 
-output [15:0] dout;
-
-reg [15:0] RAM [1023:0];
-reg [15:0] dout;
-
-always @(posedge clk)
-begin
-  if (en)
-    begin
-      if (we)
-        RAM[addr]<=di;
-      dout <= RAM[addr];
-    end
-end
-
-endmodule
-
diff --git a/tests/xilinx_ug901/rams_sp_rf.ys b/tests/xilinx_ug901/rams_sp_rf.ys
deleted file mode 100644
index 56f345c63..000000000
--- a/tests/xilinx_ug901/rams_sp_rf.ys
+++ /dev/null
@@ -1,22 +0,0 @@
-read_verilog rams_sp_rf.v
-hierarchy -top rams_sp_rf
-proc
-memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-memory
-opt -full
-
-# TODO
-#equiv_opt -run prove: -assert null
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
-
-design -load postopt
-cd rams_sp_rf
-stat
-#Vivado synthesizes 1 RAMB18E1.
-select -assert-count 1 t:BUFG
-select -assert-count 1 t:LUT2
-select -assert-count 1 t:RAMB18E1
-
-select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D
diff --git a/tests/xilinx_ug901/rams_sp_rf_rst.v b/tests/xilinx_ug901/rams_sp_rf_rst.v
deleted file mode 100644
index cb8d50c4c..000000000
--- a/tests/xilinx_ug901/rams_sp_rf_rst.v
+++ /dev/null
@@ -1,29 +0,0 @@
-// Block RAM with Resettable Data Output
-// File: rams_sp_rf_rst.v
-
-module rams_sp_rf_rst (clk, en, we, rst, addr, di, dout);
-input clk; 
-input en; 
-input we; 
-input rst;
-input [9:0] addr; 
-input [15:0] di; 
-output [15:0] dout;
-
-reg [15:0] ram [1023:0];
-reg [15:0] dout;
-
-always @(posedge clk)
-begin
-  if (en) //optional enable
-    begin
-      if (we) //write enable
-        ram[addr] <= di;
-      if (rst) //optional reset
-        dout <= 0;
-      else
-        dout <= ram[addr];
-    end
-end
-
-endmodule
diff --git a/tests/xilinx_ug901/rams_sp_rf_rst.ys b/tests/xilinx_ug901/rams_sp_rf_rst.ys
deleted file mode 100644
index 57e4df9f5..000000000
--- a/tests/xilinx_ug901/rams_sp_rf_rst.ys
+++ /dev/null
@@ -1,28 +0,0 @@
-read_verilog rams_sp_rf_rst.v
-hierarchy -top rams_sp_rf_rst
-proc
-memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-memory
-opt -full
-
-# TODO
-#equiv_opt -run prove: -assert null
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
-
-design -load postopt
-cd rams_sp_rf_rst
-stat
-#Vivado synthesizes 1 RAMB18E1.
-
-select -assert-count 1 t:BUFG
-select -assert-count 16 t:FDRE
-select -assert-count 5 t:LUT2
-select -assert-count 4 t:LUT3
-select -assert-count 13 t:LUT4
-select -assert-count 23 t:LUT5
-select -assert-count 32 t:LUT6
-select -assert-count 128 t:RAM128X1D
-
-select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:RAM128X1D %% t:* %D
diff --git a/tests/xilinx_ug901/rams_sp_rom.v b/tests/xilinx_ug901/rams_sp_rom.v
deleted file mode 100644
index b6e05f6c8..000000000
--- a/tests/xilinx_ug901/rams_sp_rom.v
+++ /dev/null
@@ -1,46 +0,0 @@
-// Initializing Block RAM (Single-Port Block RAM)
-// File: rams_sp_rom 
-module rams_sp_rom (clk, we, addr, di, dout);
-input clk;
-input we;
-input [5:0] addr;
-input [19:0] di;
-output [19:0] dout;
-
-reg [19:0] ram [63:0];
-reg [19:0] dout;
-
-initial 
-begin
-  ram[63] = 20'h0200A; ram[62] = 20'h00300; ram[61] = 20'h08101;
-  ram[60] = 20'h04000; ram[59] = 20'h08601; ram[58] = 20'h0233A;
-  ram[57] = 20'h00300; ram[56] = 20'h08602; ram[55] = 20'h02310;
-  ram[54] = 20'h0203B; ram[53] = 20'h08300; ram[52] = 20'h04002;
-  ram[51] = 20'h08201; ram[50] = 20'h00500; ram[49] = 20'h04001;
-  ram[48] = 20'h02500; ram[47] = 20'h00340; ram[46] = 20'h00241;
-  ram[45] = 20'h04002; ram[44] = 20'h08300; ram[43] = 20'h08201;
-  ram[42] = 20'h00500; ram[41] = 20'h08101; ram[40] = 20'h00602;
-  ram[39] = 20'h04003; ram[38] = 20'h0241E; ram[37] = 20'h00301;
-  ram[36] = 20'h00102; ram[35] = 20'h02122; ram[34] = 20'h02021;
-  ram[33] = 20'h00301; ram[32] = 20'h00102; ram[31] = 20'h02222;
-  ram[30] = 20'h04001; ram[29] = 20'h00342; ram[28] = 20'h0232B; 
-  ram[27] = 20'h00900; ram[26] = 20'h00302; ram[25] = 20'h00102; 
-  ram[24] = 20'h04002; ram[23] = 20'h00900; ram[22] = 20'h08201; 
-  ram[21] = 20'h02023; ram[20] = 20'h00303; ram[19] = 20'h02433; 
-  ram[18] = 20'h00301; ram[17] = 20'h04004; ram[16] = 20'h00301; 
-  ram[15] = 20'h00102; ram[14] = 20'h02137; ram[13] = 20'h02036; 
-  ram[12] = 20'h00301; ram[11] = 20'h00102; ram[10] = 20'h02237; 
-  ram[9]  = 20'h04004; ram[8]  = 20'h00304; ram[7] = 20'h04040; 
-  ram[6]  = 20'h02500; ram[5]  = 20'h02500; ram[4] = 20'h02500; 
-  ram[3]  = 20'h0030D; ram[2]  = 20'h02341; ram[1] = 20'h08201; 
-  ram[0]  = 20'h0400D;
-end
- 
-always @(posedge clk)
-begin
-  if (we)
-    ram[addr] <= di;
-  dout <= ram[addr];
-end 
-
-endmodule
diff --git a/tests/xilinx_ug901/rams_sp_rom.ys b/tests/xilinx_ug901/rams_sp_rom.ys
deleted file mode 100644
index bb8680df0..000000000
--- a/tests/xilinx_ug901/rams_sp_rom.ys
+++ /dev/null
@@ -1,22 +0,0 @@
-read_verilog rams_sp_rom.v
-hierarchy -top rams_sp_rom
-proc
-memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-memory
-opt -full
-
-# TODO
-#equiv_opt -run prove: -assert null
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
-
-design -load postopt
-cd rams_sp_rom
-stat
-#Vivado synthesizes 1 RAMB18E1.
-select -assert-count 1 t:BUFG
-select -assert-count 20 t:RAM64X1D
-select -assert-count 20 t:FDRE
-
-select -assert-none t:BUFG t:RAM64X1D t:FDRE %% t:* %D
diff --git a/tests/xilinx_ug901/rams_sp_rom_1.v b/tests/xilinx_ug901/rams_sp_rom_1.v
deleted file mode 100644
index b3b8e89fe..000000000
--- a/tests/xilinx_ug901/rams_sp_rom_1.v
+++ /dev/null
@@ -1,53 +0,0 @@
-// ROMs Using Block RAM Resources.
-// File: rams_sp_rom_1.v
-//
-module rams_sp_rom_1 (clk, en, addr, dout);
-input clk;
-input en;
-input [5:0] addr;
-output  [19:0] dout;
-
-(*rom_style = "block" *) reg [19:0] data;
-
-always @(posedge clk) 
-begin 
-  if (en)
-    case(addr)
-      6'b000000: data <= 20'h0200A; 6'b100000: data <= 20'h02222;
-      6'b000001: data <= 20'h00300; 6'b100001: data <= 20'h04001;
-      6'b000010: data <= 20'h08101; 6'b100010: data <= 20'h00342;
-      6'b000011: data <= 20'h04000; 6'b100011: data <= 20'h0232B;
-      6'b000100: data <= 20'h08601; 6'b100100: data <= 20'h00900;
-      6'b000101: data <= 20'h0233A; 6'b100101: data <= 20'h00302;
-      6'b000110: data <= 20'h00300; 6'b100110: data <= 20'h00102;
-      6'b000111: data <= 20'h08602; 6'b100111: data <= 20'h04002;
-      6'b001000: data <= 20'h02310; 6'b101000: data <= 20'h00900;
-      6'b001001: data <= 20'h0203B; 6'b101001: data <= 20'h08201;
-      6'b001010: data <= 20'h08300; 6'b101010: data <= 20'h02023;
-      6'b001011: data <= 20'h04002; 6'b101011: data <= 20'h00303;
-      6'b001100: data <= 20'h08201; 6'b101100: data <= 20'h02433;
-      6'b001101: data <= 20'h00500; 6'b101101: data <= 20'h00301;
-      6'b001110: data <= 20'h04001; 6'b101110: data <= 20'h04004;
-      6'b001111: data <= 20'h02500; 6'b101111: data <= 20'h00301;
-      6'b010000: data <= 20'h00340; 6'b110000: data <= 20'h00102;
-      6'b010001: data <= 20'h00241; 6'b110001: data <= 20'h02137;
-      6'b010010: data <= 20'h04002; 6'b110010: data <= 20'h02036;
-      6'b010011: data <= 20'h08300; 6'b110011: data <= 20'h00301;
-      6'b010100: data <= 20'h08201; 6'b110100: data <= 20'h00102;
-      6'b010101: data <= 20'h00500; 6'b110101: data <= 20'h02237;
-      6'b010110: data <= 20'h08101; 6'b110110: data <= 20'h04004;
-      6'b010111: data <= 20'h00602; 6'b110111: data <= 20'h00304;
-      6'b011000: data <= 20'h04003; 6'b111000: data <= 20'h04040;
-      6'b011001: data <= 20'h0241E; 6'b111001: data <= 20'h02500;
-      6'b011010: data <= 20'h00301; 6'b111010: data <= 20'h02500;
-      6'b011011: data <= 20'h00102; 6'b111011: data <= 20'h02500;
-      6'b011100: data <= 20'h02122; 6'b111100: data <= 20'h0030D;
-      6'b011101: data <= 20'h02021; 6'b111101: data <= 20'h02341;
-      6'b011110: data <= 20'h00301; 6'b111110: data <= 20'h08201;
-      6'b011111: data <= 20'h00102; 6'b111111: data <= 20'h0400D;
-    endcase
-end 
-
-assign dout = data;
-
-endmodule
diff --git a/tests/xilinx_ug901/rams_sp_rom_1.ys b/tests/xilinx_ug901/rams_sp_rom_1.ys
deleted file mode 100644
index 4285df1f8..000000000
--- a/tests/xilinx_ug901/rams_sp_rom_1.ys
+++ /dev/null
@@ -1,22 +0,0 @@
-read_verilog rams_sp_rom_1.v
-hierarchy -top rams_sp_rom_1
-proc
-memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-memory
-opt -full
-
-# TODO
-#equiv_opt -run prove: -assert null
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
-
-design -load postopt
-cd rams_sp_rom_1
-stat
-#Vivado synthesizes 1 RAMB18E1.
-select -assert-count 1 t:BUFG
-select -assert-count 14 t:LUT6
-select -assert-count 14 t:FDRE
-
-select -assert-none t:BUFG t:LUT6 t:FDRE %% t:* %D
diff --git a/tests/xilinx_ug901/rams_sp_wf.v b/tests/xilinx_ug901/rams_sp_wf.v
deleted file mode 100644
index 55ed6bd54..000000000
--- a/tests/xilinx_ug901/rams_sp_wf.v
+++ /dev/null
@@ -1,26 +0,0 @@
-// Single-Port Block RAM Write-First Mode (recommended template)
-// File: rams_sp_wf.v
-module rams_sp_wf (clk, we, en, addr, di, dout);
-input clk; 
-input we; 
-input en;
-input [9:0] addr; 
-input [15:0] di; 
-output [15:0] dout;
-reg [15:0] RAM [1023:0];
-reg [15:0] dout;
-
-always @(posedge clk)
-begin
-  if (en)
-  begin
-    if (we)
-      begin
-        RAM[addr] <= di;
-        dout <= di;
-      end
-   else
-    dout <= RAM[addr];
-  end
-end
-endmodule
diff --git a/tests/xilinx_ug901/rams_sp_wf.ys b/tests/xilinx_ug901/rams_sp_wf.ys
deleted file mode 100644
index 4d9a9cfea..000000000
--- a/tests/xilinx_ug901/rams_sp_wf.ys
+++ /dev/null
@@ -1,26 +0,0 @@
-read_verilog rams_sp_wf.v
-hierarchy -top rams_sp_wf
-proc
-memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-memory
-opt -full
-
-# TODO
-#equiv_opt -run prove: -assert null
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
-
-design -load postopt
-cd rams_sp_wf
-stat
-#Vivado synthesizes 1 RAMB18E1.
-
-select -assert-count 1 t:BUFG
-select -assert-count 16 t:FDRE
-select -assert-count 44 t:LUT5
-select -assert-count 38 t:LUT6
-select -assert-count 10 t:MUXF7
-select -assert-count 128 t:RAM128X1D
-
-select -assert-none t:BUFG t:LUT2 t:FDRE t:LUT5 t:LUT6 t:MUXF7 t:RAM128X1D %% t:* %D
diff --git a/tests/xilinx_ug901/rams_tdp_rf_rf.v b/tests/xilinx_ug901/rams_tdp_rf_rf.v
deleted file mode 100644
index 63899226f..000000000
--- a/tests/xilinx_ug901/rams_tdp_rf_rf.v
+++ /dev/null
@@ -1,33 +0,0 @@
-// Dual-Port Block RAM with Two Write Ports
-// File: rams_tdp_rf_rf.v
-
-module rams_tdp_rf_rf (clka,clkb,ena,enb,wea,web,addra,addrb,dia,dib,doa,dob);
-
-input clka,clkb,ena,enb,wea,web;
-input [9:0] addra,addrb;
-input [15:0] dia,dib;
-output [15:0] doa,dob;
-reg [15:0] ram [1023:0];
-reg [15:0] doa,dob;
-
-always @(posedge clka)
-begin 
-  if (ena)
-    begin
-      if (wea)
-        ram[addra] <= dia;
-      doa <= ram[addra];
-    end
-end
-
-always @(posedge clkb) 
-begin 
-  if (enb)
-    begin
-      if (web)
-        ram[addrb] <= dib;
-      dob <= ram[addrb];
-    end
-end
-
-endmodule
diff --git a/tests/xilinx_ug901/rams_tdp_rf_rf.ys b/tests/xilinx_ug901/rams_tdp_rf_rf.ys
deleted file mode 100644
index 20cf4fdcc..000000000
--- a/tests/xilinx_ug901/rams_tdp_rf_rf.ys
+++ /dev/null
@@ -1,21 +0,0 @@
-read_verilog rams_tdp_rf_rf.v
-hierarchy -top rams_tdp_rf_rf
-proc
-memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-memory
-opt -full
-
-# TODO
-#equiv_opt -run prove: -assert null
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
-
-design -load postopt
-cd rams_tdp_rf_rf
-stat
-#Vivado synthesizes 1 RAMB18E1.
-select -assert-count 1 t:$mem
-select -assert-count 2 t:LUT2
-
-select -assert-none t:$mem t:LUT2 %% t:* %D
diff --git a/tests/xilinx_ug901/registers_1.v b/tests/xilinx_ug901/registers_1.v
deleted file mode 100644
index beea6e666..000000000
--- a/tests/xilinx_ug901/registers_1.v
+++ /dev/null
@@ -1,25 +0,0 @@
-// 8-bit Register with
-// Rising-edge Clock
-// Active-high Synchronous Clear
-// Active-high Clock Enable
-// File: registers_1.v
-
-module registers_1(d_in,ce,clk,clr,dout);
-input [7:0] d_in;
-input ce;
-input clk;
-input clr;
-output [7:0] dout;
-reg [7:0] d_reg;
-
-always @ (posedge clk)
-begin
- if(clr)
-  d_reg <= 8'b0;
- else if(ce)
-  d_reg <= d_in;
-end
-
-assign dout = d_reg;
-endmodule
-
diff --git a/tests/xilinx_ug901/registers_1.ys b/tests/xilinx_ug901/registers_1.ys
deleted file mode 100644
index 39ca894a2..000000000
--- a/tests/xilinx_ug901/registers_1.ys
+++ /dev/null
@@ -1,12 +0,0 @@
-read_verilog registers_1.v
-hierarchy -top registers_1
-proc
-flatten
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd registers_1 # Constrain all select calls below inside the top module
-#Vivado synthesizes 1 BUFG, 8 FDRE.
-select -assert-count 1 t:BUFG
-select -assert-count 8 t:FDRE
-select -assert-count 9 t:LUT2
-select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D
diff --git a/tests/xilinx_ug901/run-test.sh b/tests/xilinx_ug901/run-test.sh
deleted file mode 100755
index ea56b70f0..000000000
--- a/tests/xilinx_ug901/run-test.sh
+++ /dev/null
@@ -1,20 +0,0 @@
-#!/usr/bin/env bash
-set -e
-{
-echo "all::"
-for x in *.ys; do
-	echo "all:: run-$x"
-	echo "run-$x:"
-	echo "	@echo 'Running $x..'"
-	echo "	@../../yosys -ql ${x%.ys}.log $x"
-done
-for s in *.sh; do
-	if [ "$s" != "run-test.sh" ]; then
-		echo "all:: run-$s"
-		echo "run-$s:"
-		echo "	@echo 'Running $s..'"
-		echo "	@bash $s"
-	fi
-done
-} > run-test.mk
-exec ${MAKE:-make} -f run-test.mk
diff --git a/tests/xilinx_ug901/sfir_shifter.v b/tests/xilinx_ug901/sfir_shifter.v
deleted file mode 100644
index a8b144bcd..000000000
--- a/tests/xilinx_ug901/sfir_shifter.v
+++ /dev/null
@@ -1,19 +0,0 @@
-//sfir_shifter.v
-(* dont_touch = "yes" *)
-module sfir_shifter #(parameter dsize = 16, nbtap = 4)
-                     (input clk,input [dsize-1:0] datain, output [dsize-1:0] dataout);
-
-   (* srl_style = "srl_register" *) reg [dsize-1:0] tmp [0:2*nbtap-1];
-   integer i;
-
-   always @(posedge clk)
-     begin
-        tmp[0] <= datain;
-        for (i=0; i<=2*nbtap-2; i=i+1)
-          tmp[i+1] <= tmp[i];
-     end
-
-   assign dataout = tmp[2*nbtap-1];
-
-endmodule
-// sfir_shifter
diff --git a/tests/xilinx_ug901/sfir_shifter.ys b/tests/xilinx_ug901/sfir_shifter.ys
deleted file mode 100644
index b9fbeb8cb..000000000
--- a/tests/xilinx_ug901/sfir_shifter.ys
+++ /dev/null
@@ -1,16 +0,0 @@
-read_verilog sfir_shifter.v
-hierarchy -top sfir_shifter
-proc
-flatten
-#ERROR: Found 32 unproven $equiv cells in 'equiv_status -assert'.
-#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-
-cd sfir_shifter
-#Vivado synthesizes 32 FDRE, 16 SRL16E.
-stat
-select -assert-count 1 t:BUFG
-select -assert-count 16 t:SRL16E
-
-select -assert-none t:BUFG t:SRL16E %% t:* %D
diff --git a/tests/xilinx_ug901/shift_registers_0.v b/tests/xilinx_ug901/shift_registers_0.v
deleted file mode 100644
index 77a3ec893..000000000
--- a/tests/xilinx_ug901/shift_registers_0.v
+++ /dev/null
@@ -1,22 +0,0 @@
-//  8-bit Shift Register
-//  Rising edge clock
-//  Active high clock enable
-//  Concatenation-based template
-//  File: shift_registers_0.v
-
-module shift_registers_0 (clk, clken, SI, SO);
-parameter WIDTH = 32; 
-input clk, clken, SI; 
-output SO;
-
-reg [WIDTH-1:0] shreg;
-
-always @(posedge clk)
-  begin
-    if (clken)
-      shreg = {shreg[WIDTH-2:0], SI};
-  end
-
-assign SO = shreg[WIDTH-1];
-
-endmodule
diff --git a/tests/xilinx_ug901/shift_registers_0.ys b/tests/xilinx_ug901/shift_registers_0.ys
deleted file mode 100644
index 89da1d7cc..000000000
--- a/tests/xilinx_ug901/shift_registers_0.ys
+++ /dev/null
@@ -1,14 +0,0 @@
-read_verilog shift_registers_0.v
-hierarchy -top shift_registers_0
-proc
-flatten
-#ERROR: Found 2 unproven $equiv cells in 'equiv_status -assert'.
-#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd shift_registers_0 # Constrain all select calls below inside the top module
-#Vivado synthesizes 1 BUFG, 2 FDRE, 3 SRLC32E.
-select -assert-count 1 t:BUFG
-select -assert-count 1 t:SRLC32E
-select -assert-none t:BUFG t:SRLC32E %% t:* %D
diff --git a/tests/xilinx_ug901/shift_registers_1.v b/tests/xilinx_ug901/shift_registers_1.v
deleted file mode 100644
index d50820e7b..000000000
--- a/tests/xilinx_ug901/shift_registers_1.v
+++ /dev/null
@@ -1,24 +0,0 @@
-// 32-bit Shift Register
-// Rising edge clock
-// Active high clock enable
-// For-loop based template
-// File: shift_registers_1.v
-
-module shift_registers_1 (clk, clken, SI, SO);
-parameter WIDTH = 32; 
-input clk, clken, SI; 
-output SO;
-reg [WIDTH-1:0] shreg;
-
-integer i;
-always @(posedge clk)
-begin
-  if (clken)
-    begin
-      for (i = 0; i < WIDTH-1; i = i+1)
-        shreg[i+1] <= shreg[i];
-      shreg[0] <= SI; 
-    end
-end
-assign SO = shreg[WIDTH-1];
-endmodule
diff --git a/tests/xilinx_ug901/shift_registers_1.ys b/tests/xilinx_ug901/shift_registers_1.ys
deleted file mode 100644
index b53b6cb25..000000000
--- a/tests/xilinx_ug901/shift_registers_1.ys
+++ /dev/null
@@ -1,14 +0,0 @@
-read_verilog shift_registers_1.v
-hierarchy -top shift_registers_1
-proc
-flatten
-#ERROR: Found 2 unproven $equiv cells in 'equiv_status -assert'.
-#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd shift_registers_1 # Constrain all select calls below inside the top module
-#Vivado synthesizes 1 BUFG, 2 FDRE, 3 SRLC32E.
-select -assert-count 1 t:BUFG
-select -assert-count 1 t:SRLC32E
-select -assert-none t:BUFG t:SRLC32E %% t:* %D
diff --git a/tests/xilinx_ug901/squarediffmacc.v b/tests/xilinx_ug901/squarediffmacc.v
deleted file mode 100644
index 6535b24c4..000000000
--- a/tests/xilinx_ug901/squarediffmacc.v
+++ /dev/null
@@ -1,52 +0,0 @@
-// This module performs subtraction of two inputs, squaring on the diff
-// and then accumulation
-// This can be implemented in 1 DSP Block (Ultrascale architecture)
-// File : squarediffmacc.v
-module squarediffmacc  # (
-						//Default parameters were changed because of slow test
-                          //parameter SIZEIN = 16,
-                                    //SIZEOUT = 40
-						  parameter SIZEIN = 8,
-                          SIZEOUT = 20
-                         )
-                        (
-                         input clk,
-                         input ce,
-                         input sload,
-                         input signed [SIZEIN-1:0]   a,
-                         input signed [SIZEIN-1:0]   b,
-                         output signed [SIZEOUT+1:0] accum_out
-                        );
-
-// Declare registers for intermediate values
-reg signed [SIZEIN-1:0]  a_reg, b_reg;
-reg signed [SIZEIN:0]  diff_reg;
-reg                       sload_reg;
-reg signed [2*SIZEIN+1:0] m_reg;
-reg signed [SIZEOUT-1:0]  adder_out, old_result;
-
-  always @(sload_reg or adder_out)
-  if (sload_reg)
-    old_result <= 0;
-  else
-    // 'sload' is now and opens the accumulation loop.
-    // The accumulator takes the next multiplier output
-    // in the same cycle.
-    old_result <= adder_out;
-
-  always @(posedge clk)
-  if (ce)
-  begin
-    a_reg     <= a;
-    b_reg     <= b;
-    diff_reg  <= a_reg - b_reg;
-    m_reg  <= diff_reg * diff_reg;
-    sload_reg <= sload;
-    // Store accumulation result into a register
-    adder_out <= old_result + m_reg;
-  end
-
-  // Output accumulation result
-  assign accum_out = adder_out;
-
-endmodule // squarediffmacc
diff --git a/tests/xilinx_ug901/squarediffmacc.ys b/tests/xilinx_ug901/squarediffmacc.ys
deleted file mode 100644
index 92474bea3..000000000
--- a/tests/xilinx_ug901/squarediffmacc.ys
+++ /dev/null
@@ -1,23 +0,0 @@
-read_verilog squarediffmacc.v
-hierarchy -top squarediffmacc
-proc
-flatten
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-
-cd squarediffmacc
-#Vivado synthesizes 1 DSP48E1, 33 FDRE, 16 LUT.
-stat
-select -assert-count 1 t:BUFG
-select -assert-count 64 t:FDRE
-select -assert-count 78 t:LUT2
-select -assert-count 7 t:LUT3
-select -assert-count 11 t:LUT4
-select -assert-count 8 t:LUT5
-select -assert-count 125 t:LUT6
-select -assert-count 44 t:MUXCY
-select -assert-count 50 t:MUXF7
-select -assert-count 17 t:MUXF8
-select -assert-count 47 t:XORCY
-
-select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
diff --git a/tests/xilinx_ug901/squarediffmult.v b/tests/xilinx_ug901/squarediffmult.v
deleted file mode 100644
index 0f41b67bc..000000000
--- a/tests/xilinx_ug901/squarediffmult.v
+++ /dev/null
@@ -1,42 +0,0 @@
-// Squarer support for DSP block (DSP48E2) with 
-// pre-adder configured
-// as subtractor
-// File: squarediffmult.v
-
-module squarediffmult # (parameter SIZEIN = 16)
-                        (
-                          input clk, ce, rst,
-                          input  signed [SIZEIN-1:0]   a, b,
-                          output signed [2*SIZEIN+1:0] square_out
-                        );
-
-   // Declare registers for intermediate values
-reg signed [SIZEIN-1:0]   a_reg, b_reg;
-reg signed [SIZEIN:0]     diff_reg;
-reg signed [2*SIZEIN+1:0] m_reg, p_reg;
-
-always @(posedge clk)
-begin
- if (rst)
-  begin
-   a_reg    <= 0;
-   b_reg    <= 0;
-   diff_reg <= 0;   
-   m_reg    <= 0;
-   p_reg    <= 0;
-  end
- else
-  if (ce)
-  begin
-    a_reg     <= a;
-    b_reg     <= b;
-    diff_reg <= a_reg - b_reg;
-    m_reg  <= diff_reg * diff_reg;
-    p_reg  <= m_reg;     
- end
-end
-
-// Output result
-assign square_out = p_reg;
-   
-endmodule // squarediffmult
diff --git a/tests/xilinx_ug901/squarediffmult.ys b/tests/xilinx_ug901/squarediffmult.ys
deleted file mode 100644
index 3468e5bb4..000000000
--- a/tests/xilinx_ug901/squarediffmult.ys
+++ /dev/null
@@ -1,30 +0,0 @@
-read_verilog squarediffmult.v
-hierarchy -top squarediffmult
-proc
-memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-memory
-opt -full
-
-# TODO
-#equiv_opt -run prove: -assert null
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
-
-design -load postopt
-cd squarediffmult
-stat
-#Vivado synthesizes 16 FDRE, 1 DSP48E1.
-select -assert-count 1 t:BUFG
-select -assert-count 117 t:FDRE
-select -assert-count 223 t:LUT2
-select -assert-count 50 t:LUT3
-select -assert-count 38 t:LUT4
-select -assert-count 56 t:LUT5
-select -assert-count 372 t:LUT6
-select -assert-count 49 t:MUXCY
-select -assert-count 99 t:MUXF7
-select -assert-count 26 t:MUXF8
-select -assert-count 51 t:XORCY
-
-select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
diff --git a/tests/xilinx_ug901/top_mux.v b/tests/xilinx_ug901/top_mux.v
deleted file mode 100644
index c23c7491c..000000000
--- a/tests/xilinx_ug901/top_mux.v
+++ /dev/null
@@ -1,18 +0,0 @@
-// Multiplexer using case statement 
-module mux4 (sel, a, b, c, d, outmux);
-input [1:0] sel;
-input [1:0] a, b, c, d;
-output [1:0] outmux;
-reg [1:0] outmux;
-
-always @ *
-   begin 
-	   case(sel)
-		  2'b00 : outmux = a;
-      2'b01 : outmux = b;
-      2'b10 : outmux = c;
-      2'b11 : outmux = d;
-     endcase
-   end 
-endmodule
-
diff --git a/tests/xilinx_ug901/top_mux.ys b/tests/xilinx_ug901/top_mux.ys
deleted file mode 100644
index 0245f3bbc..000000000
--- a/tests/xilinx_ug901/top_mux.ys
+++ /dev/null
@@ -1,13 +0,0 @@
-read_verilog top_mux.v
-hierarchy -top mux4
-proc
-flatten
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-
-cd mux4
-#Vivado synthesizes 2 LUT.
-stat
-select -assert-count 2 t:LUT6
-
-select -assert-none t:LUT6 %% t:* %D
diff --git a/tests/xilinx_ug901/tristates_1.v b/tests/xilinx_ug901/tristates_1.v
deleted file mode 100644
index 0038a9989..000000000
--- a/tests/xilinx_ug901/tristates_1.v
+++ /dev/null
@@ -1,17 +0,0 @@
-// Tristate Description Using Combinatorial Always Block
-// File: tristates_1.v
-//
-module tristates_1 (T, I, O);
-input  T, I;
-output O;
-reg    O;
-
-always @(T or I)
-begin
-  if (~T)
-    O = I;
-  else
-   O = 1'bZ;
-end
-
-endmodule
diff --git a/tests/xilinx_ug901/tristates_1.ys b/tests/xilinx_ug901/tristates_1.ys
deleted file mode 100644
index 7c13dc227..000000000
--- a/tests/xilinx_ug901/tristates_1.ys
+++ /dev/null
@@ -1,13 +0,0 @@
-read_verilog tristates_1.v
-hierarchy -top tristates_1
-proc
-tribuf
-flatten
-synth
-equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd tristates_1 # Constrain all select calls below inside the top module
-#Vivado synthesizes 3 IBUF, 1 OBUFT.
-select -assert-count 1 t:LUT1
-select -assert-count 1 t:$_TBUF_
-select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D
diff --git a/tests/xilinx_ug901/tristates_2.v b/tests/xilinx_ug901/tristates_2.v
deleted file mode 100644
index 0c70a1257..000000000
--- a/tests/xilinx_ug901/tristates_2.v
+++ /dev/null
@@ -1,10 +0,0 @@
-// Tristate Description Using Concurrent Assignment
-// File: tristates_2.v
-//
-module tristates_2 (T, I, O);
-input  T, I;
-output O;
-
-assign O = (~T) ? I: 1'bZ;
-
-endmodule
diff --git a/tests/xilinx_ug901/tristates_2.ys b/tests/xilinx_ug901/tristates_2.ys
deleted file mode 100644
index ba2e1d855..000000000
--- a/tests/xilinx_ug901/tristates_2.ys
+++ /dev/null
@@ -1,13 +0,0 @@
-read_verilog tristates_2.v
-hierarchy -top tristates_2
-proc
-tribuf
-flatten
-synth
-equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd tristates_2 # Constrain all select calls below inside the top module
-#Vivado synthesizes 3 IBUF, 1 OBUFT.
-select -assert-count 1 t:LUT1
-select -assert-count 1 t:$_TBUF_
-select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D
diff --git a/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.v b/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.v
deleted file mode 100644
index f5e843dc9..000000000
--- a/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.v
+++ /dev/null
@@ -1,78 +0,0 @@
-//  Xilinx UltraRAM Single Port No Change Mode.  This code implements
-//  a parameterizable UltraRAM block in No Change mode. The behavior of this RAM is
-//  when data is written, the output of RAM is unchanged. Only when write is
-//  inactive data corresponding to the address is presented on the output port.
-//
-module xilinx_ultraram_single_port_no_change #(
-//Default parameters were changed because of slow test
-  //parameter AWIDTH = 12,  // Address Width
-  //parameter DWIDTH = 72,  // Data Width
-  //parameter NBPIPE = 3    // Number of pipeline Registers
-  parameter AWIDTH = 8,  // Address Width
-  parameter DWIDTH = 8,  // Data Width
-  parameter NBPIPE = 3    // Number of pipeline Registers
- ) (
-    input clk,                    // Clock
-    input rst,                    // Reset
-    input we,                     // Write Enable
-    input regce,                  // Output Register Enable
-    input mem_en,                 // Memory Enable
-    input [DWIDTH-1:0] din,       // Data Input
-    input [AWIDTH-1:0] addr,      // Address Input
-    output reg [DWIDTH-1:0] dout  // Data Output
-   );
-
-(* ram_style = "ultra" *)
-reg [DWIDTH-1:0] mem[(1<<AWIDTH)-1:0];        // Memory Declaration
-reg [DWIDTH-1:0] memreg;
-reg [DWIDTH-1:0] mem_pipe_reg[NBPIPE-1:0];    // Pipelines for memory
-reg mem_en_pipe_reg[NBPIPE:0];                // Pipelines for memory enable
-
-integer          i;
-
-// RAM : Read has one latency, Write has one latency as well.
-always @ (posedge clk)
-begin
- if(mem_en)
-  begin
-  if(we)
-    mem[addr] <= din;
-  else
-   memreg <= mem[addr];
-  end
-end
-// The enable of the RAM goes through a pipeline to produce a
-// series of pipelined enable signals required to control the data
-// pipeline.
-always @ (posedge clk)
-begin
-mem_en_pipe_reg[0] <= mem_en;
- for (i=0; i<NBPIPE; i=i+1)
-  mem_en_pipe_reg[i+1] <= mem_en_pipe_reg[i];
-end
-
-// RAM output data goes through a pipeline.
-always @ (posedge clk)
-begin
- if (mem_en_pipe_reg[0])
-  mem_pipe_reg[0] <= memreg;
-end
-
-always @ (posedge clk)
-begin
- for (i = 0; i < NBPIPE-1; i = i+1)
-  if (mem_en_pipe_reg[i+1])
-    mem_pipe_reg[i+1] <= mem_pipe_reg[i];
-end
-
-// Final output register gives user the option to add a reset and
-// an additional enable signal just for the data ouptut
-always @ (posedge clk)
-begin
- if (rst)
-  dout <= 0;
- else if (mem_en_pipe_reg[NBPIPE] && regce)
-  dout <= mem_pipe_reg[NBPIPE-1];
-end
-endmodule
-
diff --git a/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.ys b/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.ys
deleted file mode 100644
index df3126e67..000000000
--- a/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.ys
+++ /dev/null
@@ -1,25 +0,0 @@
-read_verilog xilinx_ultraram_single_port_no_change.v
-hierarchy -top xilinx_ultraram_single_port_no_change
-proc
-memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-memory
-opt -full
-
-# TODO
-#equiv_opt -run prove: -assert null
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
-
-design -load postopt
-cd xilinx_ultraram_single_port_no_change
-stat
-#Vivado synthesizes 1 RAMB36E1, 28 FDRE.
-select -assert-count 1 t:BUFG
-select -assert-count 53 t:FDRE
-select -assert-count 1 t:LUT1
-select -assert-count 9 t:LUT2
-select -assert-count 11 t:LUT3
-select -assert-count 16 t:RAM128X1D
-
-select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D
diff --git a/tests/xilinx_ug901/xilinx_ultraram_single_port_read_first.v b/tests/xilinx_ug901/xilinx_ultraram_single_port_read_first.v
deleted file mode 100644
index d36c38fe1..000000000
--- a/tests/xilinx_ug901/xilinx_ultraram_single_port_read_first.v
+++ /dev/null
@@ -1,78 +0,0 @@
-//  Xilinx UltraRAM Single Port Read First Mode.  This code implements
-//  a parameterizable UltraRAM block in read first mode. The behavior of this RAM is
-//  when data is written, the old memory contents at the write address are
-//  presented on the output port.
-//
-module xilinx_ultraram_single_port_read_first #(
-
-//Default parameters were changed because of slow test
-  //parameter AWIDTH = 12,  // Address Width
-  //parameter DWIDTH = 72,  // Data Width
-  //parameter NBPIPE = 3    // Number of pipeline Registers
-  parameter AWIDTH = 8,  // Address Width
-  parameter DWIDTH = 8,  // Data Width
-  parameter NBPIPE = 3    // Number of pipeline Registers
- ) (
-    input clk,                    // Clock
-    input rst,                    // Reset
-    input we,                     // Write Enable
-    input regce,                  // Output Register Enable
-    input mem_en,                 // Memory Enable
-    input [DWIDTH-1:0] din,       // Data Input
-    input [AWIDTH-1:0] addr,      // Address Input
-    output reg [DWIDTH-1:0] dout  // Data Output
-   );
-
-(* ram_style = "ultra" *)
-reg [DWIDTH-1:0] mem[(1<<AWIDTH)-1:0];        // Memory Declaration
-reg [DWIDTH-1:0] memreg;
-reg [DWIDTH-1:0] mem_pipe_reg[NBPIPE-1:0];    // Pipelines for memory
-reg mem_en_pipe_reg[NBPIPE:0];                // Pipelines for memory enable
-
-integer          i;
-
-// RAM : Both READ and WRITE have a latency of one
-always @ (posedge clk)
-begin
- if(mem_en)
-  begin
-   if(we)
-    mem[addr] <= din;
-   memreg <= mem[addr];
-  end
-end
-
-// The enable of the RAM goes through a pipeline to produce a
-// series of pipelined enable signals required to control the data
-// pipeline.
-always @ (posedge clk)
-begin
- mem_en_pipe_reg[0] <= mem_en;
- for (i=0; i<NBPIPE; i=i+1)
-   mem_en_pipe_reg[i+1] <= mem_en_pipe_reg[i];
-end
-
-// RAM output data goes through a pipeline.
-always @ (posedge clk)
-begin
- if (mem_en_pipe_reg[0])
-  mem_pipe_reg[0] <= memreg;
-end
-
-always @ (posedge clk)
-begin
- for (i = 0; i < NBPIPE-1; i = i+1)
-  if (mem_en_pipe_reg[i+1])
-   mem_pipe_reg[i+1] <= mem_pipe_reg[i];
-end
-
-// Final output register gives user the option to add a reset and
-// an additional enable signal just for the data ouptut
-always @ (posedge clk)
-begin
- if (rst)
-   dout <= 0;
- else if (mem_en_pipe_reg[NBPIPE] && regce)
-   dout <= mem_pipe_reg[NBPIPE-1];
-end
-endmodule
diff --git a/tests/xilinx_ug901/xilinx_ultraram_single_port_read_first.ys b/tests/xilinx_ug901/xilinx_ultraram_single_port_read_first.ys
deleted file mode 100644
index 4907d042d..000000000
--- a/tests/xilinx_ug901/xilinx_ultraram_single_port_read_first.ys
+++ /dev/null
@@ -1,24 +0,0 @@
-read_verilog xilinx_ultraram_single_port_read_first.v
-hierarchy -top xilinx_ultraram_single_port_read_first
-proc
-memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-memory
-opt -full
-
-# TODO
-#equiv_opt -run prove: -assert null
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
-
-design -load postopt
-cd xilinx_ultraram_single_port_read_first
-#Vivado synthesizes 1 RAMB18E1, 28 FDRE.
-select -assert-count 1 t:BUFG
-select -assert-count 53 t:FDRE
-select -assert-count 1 t:LUT1
-select -assert-count 8 t:LUT2
-select -assert-count 11 t:LUT3
-select -assert-count 16 t:RAM128X1D
-
-select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D
diff --git a/tests/xilinx_ug901/xilinx_ultraram_single_port_write_first.v b/tests/xilinx_ug901/xilinx_ultraram_single_port_write_first.v
deleted file mode 100644
index 7985d3d4a..000000000
--- a/tests/xilinx_ug901/xilinx_ultraram_single_port_write_first.v
+++ /dev/null
@@ -1,82 +0,0 @@
-//  Xilinx UltraRAM Single Port Write First Mode.  This code implements
-//  a parameterizable UltraRAM block in write first mode. The behavior of this RAM is
-//  when data is written, the new memory contents at the write address are
-//  presented on the output port.
-//
-module xilinx_ultraram_single_port_write_first #(
-
-//Default parameters were changed because of slow test
-  //parameter AWIDTH = 12,  // Address Width
-  //parameter DWIDTH = 72,  // Data Width
-  //parameter NBPIPE = 3    // Number of pipeline Registers
-  parameter AWIDTH = 8,  // Address Width
-  parameter DWIDTH = 8,  // Data Width
-  parameter NBPIPE = 3    // Number of pipeline Registers
- ) (
-    input clk,                    // Clock
-    input rst,                    // Reset
-    input we,                     // Write Enable
-    input regce,                  // Output Register Enable
-    input mem_en,                 // Memory Enable
-    input [DWIDTH-1:0] din,       // Data Input
-    input [AWIDTH-1:0] addr,      // Address Input
-    output reg [DWIDTH-1:0] dout  // Data Output
-   );
-
-(* ram_style = "ultra" *)
-reg [DWIDTH-1:0] mem[(1<<AWIDTH)-1:0];        // Memory Declaration
-reg [DWIDTH-1:0] memreg;
-reg [DWIDTH-1:0] mem_pipe_reg[NBPIPE-1:0];    // Pipelines for memory
-reg mem_en_pipe_reg[NBPIPE:0];                // Pipelines for memory enable
-
-integer          i;
-
-// RAM : Both READ and WRITE have a latency of one
-always @ (posedge clk)
-begin
- if(mem_en)
-  begin
-    if(we)
-    begin
-      mem[addr] <= din;
-     memreg <= din;
-   end
-    else
-     memreg <= mem[addr];
-  end
-end
-
-// The enable of the RAM goes through a pipeline to produce a
-// series of pipelined enable signals required to control the data
-// pipeline.
-always @ (posedge clk)
-begin
- mem_en_pipe_reg[0] <= mem_en;
- for (i=0; i<NBPIPE; i=i+1)
-   mem_en_pipe_reg[i+1] <= mem_en_pipe_reg[i];
-end
-
-// RAM output data goes through a pipeline.
-always @ (posedge clk)
-begin
- if (mem_en_pipe_reg[0])
-  mem_pipe_reg[0] <= memreg;
-end
-
-always @ (posedge clk)
-begin
-  for (i = 0; i < NBPIPE-1; i = i+1)
-   if (mem_en_pipe_reg[i+1])
-     mem_pipe_reg[i+1] <= mem_pipe_reg[i];
-end
-
-// Final output register gives user the option to add a reset and
-// an additional enable signal just for the data ouptut
-always @ (posedge clk)
-begin
- if (rst)
-  dout <= 0;
- else if (mem_en_pipe_reg[NBPIPE] && regce)
-  dout <= mem_pipe_reg[NBPIPE-1];
-end
-endmodule
diff --git a/tests/xilinx_ug901/xilinx_ultraram_single_port_write_first.ys b/tests/xilinx_ug901/xilinx_ultraram_single_port_write_first.ys
deleted file mode 100644
index 9ca6b4d89..000000000
--- a/tests/xilinx_ug901/xilinx_ultraram_single_port_write_first.ys
+++ /dev/null
@@ -1,24 +0,0 @@
-read_verilog xilinx_ultraram_single_port_write_first.v
-hierarchy -top xilinx_ultraram_single_port_write_first
-proc
-memory -nomap
-equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
-memory
-opt -full
-
-# TODO
-#equiv_opt -run prove: -assert null
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
-
-design -load postopt
-cd xilinx_ultraram_single_port_write_first
-#Vivado synthesizes 1 RAMB18E1, 28 FDRE.
-select -assert-count 1 t:BUFG
-select -assert-count 44 t:FDRE
-select -assert-count 8 t:LUT5
-select -assert-count 8 t:LUT2
-select -assert-count 3 t:LUT3
-select -assert-count 16 t:RAM128X1D
-
-select -assert-none t:BUFG t:FDRE t:LUT5 t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D
-- 
cgit v1.2.3


From 489444bcba0d54a45605872eb466792f07357f84 Mon Sep 17 00:00:00 2001
From: SergeyDegtyar <sndegtyar@gmail.com>
Date: Tue, 10 Sep 2019 08:36:59 +0300
Subject: Fix latches.ys test

---
 tests/xilinx/latches.ys | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

(limited to 'tests')

diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys
index 9ab562bcf..042ee2d4f 100644
--- a/tests/xilinx/latches.ys
+++ b/tests/xilinx/latches.ys
@@ -11,10 +11,9 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 design -load read
 
 synth_xilinx
-#cd top
-
+flatten
+cd top
 select -assert-count 1 t:LUT1
 select -assert-count 2 t:LUT3
 select -assert-count 3 t:$_DLATCH_P_
-#ERROR: Assertion failed: selection is not empty: t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D
-#select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D
+select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D
-- 
cgit v1.2.3


From 7bc8f0c2e234641b8af7f8dd991ea65bd9a6ef1a Mon Sep 17 00:00:00 2001
From: SergeyDegtyar <sndegtyar@gmail.com>
Date: Wed, 11 Sep 2019 17:01:19 +0300
Subject: Add comment with expected behavior for latches,tribuf tests;Update
 adffs test

---
 tests/xilinx/adffs.v    | 18 +++++++-----------
 tests/xilinx/adffs.ys   |  5 ++---
 tests/xilinx/latches.ys |  1 +
 tests/xilinx/tribuf.ys  |  1 +
 4 files changed, 11 insertions(+), 14 deletions(-)

(limited to 'tests')

diff --git a/tests/xilinx/adffs.v b/tests/xilinx/adffs.v
index 93c8bf52c..05e68caf7 100644
--- a/tests/xilinx/adffs.v
+++ b/tests/xilinx/adffs.v
@@ -22,30 +22,26 @@ module adffn
             q <= d;
 endmodule
 
-module dffsr
+module dffs
     ( input d, clk, pre, clr, output reg q );
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge pre, posedge clr )
-		if ( clr )
-			q <= 1'b0;
-		else if ( pre )
+	always @( posedge clk )
+		if ( pre )
 			q <= 1'b1;
 		else
             q <= d;
 endmodule
 
-module ndffnsnr
+module ndffnr
     ( input d, clk, pre, clr, output reg q );
     initial begin
       q = 0;
     end
-	always @( negedge clk, negedge pre, negedge clr )
+	always @( negedge clk )
 		if ( !clr )
 			q <= 1'b0;
-		else if ( !pre )
-			q <= 1'b1;
 		else
             q <= d;
 endmodule
@@ -58,7 +54,7 @@ input a,
 output b,b1,b2,b3
 );
 
-dffsr u_dffsr (
+dffs u_dffs (
         .clk (clk ),
         .clr (clr),
         .pre (pre),
@@ -66,7 +62,7 @@ dffsr u_dffsr (
         .q (b )
     );
 
-ndffnsnr u_ndffnsnr (
+ndffnr u_ndffnr (
         .clk (clk ),
         .clr (clr),
         .pre (pre),
diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys
index 96d8e176f..38c82a36f 100644
--- a/tests/xilinx/adffs.ys
+++ b/tests/xilinx/adffs.ys
@@ -9,6 +9,5 @@ cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
 select -assert-count 3 t:FDRE
 select -assert-count 1 t:FDRE_1
-select -assert-count 4 t:LUT2
-select -assert-count 4 t:LUT3
-select -assert-none t:BUFG t:FDRE t:FDRE_1 t:LUT2 t:LUT3 %% t:* %D
+select -assert-count 5 t:LUT2
+select -assert-none t:BUFG t:FDRE t:FDRE_1 t:LUT2 %% t:* %D
diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys
index 042ee2d4f..1f643cb4e 100644
--- a/tests/xilinx/latches.ys
+++ b/tests/xilinx/latches.ys
@@ -15,5 +15,6 @@ flatten
 cd top
 select -assert-count 1 t:LUT1
 select -assert-count 2 t:LUT3
+#Xilinx Vivado synthesizes LDCE cell for this case. Need support it.
 select -assert-count 3 t:$_DLATCH_P_
 select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D
diff --git a/tests/xilinx/tribuf.ys b/tests/xilinx/tribuf.ys
index fc7ed37ef..76b00647d 100644
--- a/tests/xilinx/tribuf.ys
+++ b/tests/xilinx/tribuf.ys
@@ -7,5 +7,6 @@ synth
 equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
+#Xilinx Vivado synthesizes OBUFT cell for this case. Need support it.
 select -assert-count 1 t:$_TBUF_
 select -assert-none t:$_TBUF_ %% t:* %D
-- 
cgit v1.2.3


From df7fe40529f7e0a26626ac1b0ed12acf66bb40d3 Mon Sep 17 00:00:00 2001
From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com>
Date: Wed, 11 Sep 2019 20:34:22 +0300
Subject: Fix div_mod test

---
 tests/xilinx/div_mod.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys
index cc00b1a27..52e536a7f 100644
--- a/tests/xilinx/div_mod.ys
+++ b/tests/xilinx/div_mod.ys
@@ -6,7 +6,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd top # Constrain all select calls below inside the top module
 
 select -assert-count 12 t:LUT1
-select -assert-count 21 t:LUT2
+select -assert-count 23 t:LUT2
 select -assert-count 13 t:LUT4
 select -assert-count 6  t:LUT5
 select -assert-count 80 t:LUT6
-- 
cgit v1.2.3


From 205f52ffe53778daf9fc1bcdd9bee4b53a6e2a60 Mon Sep 17 00:00:00 2001
From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com>
Date: Wed, 11 Sep 2019 21:28:40 +0300
Subject: Fix div_mod test

---
 tests/xilinx/div_mod.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys
index 52e536a7f..e1c4d6912 100644
--- a/tests/xilinx/div_mod.ys
+++ b/tests/xilinx/div_mod.ys
@@ -7,7 +7,7 @@ cd top # Constrain all select calls below inside the top module
 
 select -assert-count 12 t:LUT1
 select -assert-count 23 t:LUT2
-select -assert-count 13 t:LUT4
+select -assert-count 12 t:LUT4
 select -assert-count 6  t:LUT5
 select -assert-count 80 t:LUT6
 select -assert-count 65 t:MUXCY
-- 
cgit v1.2.3


From c340d54657688542c5f3a8dabe3f68563dcc8d1c Mon Sep 17 00:00:00 2001
From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com>
Date: Thu, 12 Sep 2019 06:24:18 +0300
Subject: Fix div_mod test

---
 tests/xilinx/div_mod.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys
index e1c4d6912..7db336d00 100644
--- a/tests/xilinx/div_mod.ys
+++ b/tests/xilinx/div_mod.ys
@@ -8,7 +8,7 @@ cd top # Constrain all select calls below inside the top module
 select -assert-count 12 t:LUT1
 select -assert-count 23 t:LUT2
 select -assert-count 12 t:LUT4
-select -assert-count 6  t:LUT5
+select -assert-count 9  t:LUT5
 select -assert-count 80 t:LUT6
 select -assert-count 65 t:MUXCY
 select -assert-count 36 t:MUXF7
-- 
cgit v1.2.3


From df6d0b95da89a4a7bd558dab0c112f5c7a989561 Mon Sep 17 00:00:00 2001
From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com>
Date: Thu, 12 Sep 2019 07:13:49 +0300
Subject: Fix div_mod test

---
 tests/xilinx/div_mod.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys
index 7db336d00..c5855f1dd 100644
--- a/tests/xilinx/div_mod.ys
+++ b/tests/xilinx/div_mod.ys
@@ -9,7 +9,7 @@ select -assert-count 12 t:LUT1
 select -assert-count 23 t:LUT2
 select -assert-count 12 t:LUT4
 select -assert-count 9  t:LUT5
-select -assert-count 80 t:LUT6
+select -assert-count 84 t:LUT6
 select -assert-count 65 t:MUXCY
 select -assert-count 36 t:MUXF7
 select -assert-count 9  t:MUXF8
-- 
cgit v1.2.3


From 68f9239c5758e4f48dc290871cf108f85d5f5387 Mon Sep 17 00:00:00 2001
From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com>
Date: Thu, 12 Sep 2019 13:58:49 +0300
Subject: Fix div_mod test

---
 tests/xilinx/div_mod.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys
index c5855f1dd..6a4c1e971 100644
--- a/tests/xilinx/div_mod.ys
+++ b/tests/xilinx/div_mod.ys
@@ -11,7 +11,7 @@ select -assert-count 12 t:LUT4
 select -assert-count 9  t:LUT5
 select -assert-count 84 t:LUT6
 select -assert-count 65 t:MUXCY
-select -assert-count 36 t:MUXF7
+select -assert-count 39 t:MUXF7
 select -assert-count 9  t:MUXF8
 select -assert-count 28 t:XORCY
 select -assert-none t:LUT1 t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
-- 
cgit v1.2.3


From bb70eb977dc29dbfe8cfb9af847046f387bd54b2 Mon Sep 17 00:00:00 2001
From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com>
Date: Thu, 12 Sep 2019 14:54:01 +0300
Subject: Fix div_mod test

---
 tests/xilinx/div_mod.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys
index 6a4c1e971..4518db8bf 100644
--- a/tests/xilinx/div_mod.ys
+++ b/tests/xilinx/div_mod.ys
@@ -12,6 +12,6 @@ select -assert-count 9  t:LUT5
 select -assert-count 84 t:LUT6
 select -assert-count 65 t:MUXCY
 select -assert-count 39 t:MUXF7
-select -assert-count 9  t:MUXF8
+select -assert-count 15 t:MUXF8
 select -assert-count 28 t:XORCY
 select -assert-none t:LUT1 t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
-- 
cgit v1.2.3


From 305672170bcd6346bebbb01c843225fe0392a37d Mon Sep 17 00:00:00 2001
From: SergeyDegtyar <sndegtyar@gmail.com>
Date: Tue, 17 Sep 2019 11:53:49 +0300
Subject: adffs test update (equiv_opt -multiclock)

---
 tests/xilinx/adffs.ys | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

(limited to 'tests')

diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys
index 38c82a36f..961e08ae9 100644
--- a/tests/xilinx/adffs.ys
+++ b/tests/xilinx/adffs.ys
@@ -1,13 +1,14 @@
 read_verilog adffs.v
 proc
-async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock
 flatten
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -multiclock -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
 select -assert-count 1 t:BUFG
-select -assert-count 3 t:FDRE
+select -assert-count 2 t:FDCE
+select -assert-count 1 t:FDRE
 select -assert-count 1 t:FDRE_1
-select -assert-count 5 t:LUT2
-select -assert-none t:BUFG t:FDRE t:FDRE_1 t:LUT2 %% t:* %D
+select -assert-count 1 t:LUT1
+select -assert-count 2 t:LUT2
+select -assert-none t:BUFG t:FDCE t:FDRE t:FDRE_1 t:LUT1 t:LUT2 %% t:* %D
-- 
cgit v1.2.3


From eded90b6b42117ba427469a6100c74e708c4f142 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Sep 2019 14:16:45 -0700
Subject: Move $x to end as 7f0eec8

---
 tests/xilinx/run-test.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/xilinx/run-test.sh b/tests/xilinx/run-test.sh
index 2c72ca3a9..46716f9a0 100755
--- a/tests/xilinx/run-test.sh
+++ b/tests/xilinx/run-test.sh
@@ -6,7 +6,7 @@ for x in *.ys; do
 	echo "all:: run-$x"
 	echo "run-$x:"
 	echo "	@echo 'Running $x..'"
-	echo "	@../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'"
+	echo "	@../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
 done
 for s in *.sh; do
 	if [ "$s" != "run-test.sh" ]; then
-- 
cgit v1.2.3


From a12801843bb400bba8f2f8ce99a3f524ac05b7e8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Sep 2019 14:17:59 -0700
Subject: Add comment for lack of tristate logic pointing to #1225

---
 tests/xilinx/tribuf.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/xilinx/tribuf.ys b/tests/xilinx/tribuf.ys
index 76b00647d..696be2620 100644
--- a/tests/xilinx/tribuf.ys
+++ b/tests/xilinx/tribuf.ys
@@ -7,6 +7,6 @@ synth
 equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
-#Xilinx Vivado synthesizes OBUFT cell for this case. Need support it.
+# TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225
 select -assert-count 1 t:$_TBUF_
 select -assert-none t:$_TBUF_ %% t:* %D
-- 
cgit v1.2.3


From 08bd1816e39d2abfbe36ce0b58c0d4506db303e4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Sep 2019 14:20:47 -0700
Subject: Update area for div_mod

---
 tests/xilinx/div_mod.ys | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

(limited to 'tests')

diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys
index 4518db8bf..da7e60a9a 100644
--- a/tests/xilinx/div_mod.ys
+++ b/tests/xilinx/div_mod.ys
@@ -6,12 +6,12 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd top # Constrain all select calls below inside the top module
 
 select -assert-count 12 t:LUT1
-select -assert-count 23 t:LUT2
-select -assert-count 12 t:LUT4
-select -assert-count 9  t:LUT5
-select -assert-count 84 t:LUT6
+select -assert-count 19 t:LUT2
+select -assert-count 13 t:LUT4
+select -assert-count 6  t:LUT5
+select -assert-count 82 t:LUT6
 select -assert-count 65 t:MUXCY
-select -assert-count 39 t:MUXF7
-select -assert-count 15 t:MUXF8
+select -assert-count 37 t:MUXF7
+select -assert-count 11 t:MUXF8
 select -assert-count 28 t:XORCY
 select -assert-none t:LUT1 t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
-- 
cgit v1.2.3


From 5b7bc3ab85d31920883995636d26dc5b971ca24d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Sep 2019 14:38:06 -0700
Subject: Update mul test to DSP48E1

---
 tests/xilinx/mul.ys | 11 ++---------
 1 file changed, 2 insertions(+), 9 deletions(-)

(limited to 'tests')

diff --git a/tests/xilinx/mul.ys b/tests/xilinx/mul.ys
index ec30c9c2c..f5306e848 100644
--- a/tests/xilinx/mul.ys
+++ b/tests/xilinx/mul.ys
@@ -4,12 +4,5 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
-select -assert-count 12 t:LUT2
-select -assert-count 1  t:LUT3
-select -assert-count 6  t:LUT4
-select -assert-count 1  t:LUT5
-select -assert-count 33 t:LUT6
-select -assert-count 11 t:MUXCY
-select -assert-count 1  t:MUXF7
-select -assert-count 12 t:XORCY
-select -assert-none t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:XORCY %% t:* %D
+select -assert-count 1 t:DSP48E1
+select -assert-none t:DSP48E1 %% t:* %D
-- 
cgit v1.2.3


From 8422ad3e3a5db583f59906f8a5d81587dd777f6d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Sep 2019 14:56:19 -0700
Subject: Use built-in async2sync call as per #1417

---
 tests/xilinx/latches.ys | 4 ----
 1 file changed, 4 deletions(-)

(limited to 'tests')

diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys
index 1f643cb4e..795ac9074 100644
--- a/tests/xilinx/latches.ys
+++ b/tests/xilinx/latches.ys
@@ -4,11 +4,7 @@ design -save read
 proc
 async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock
 flatten
-synth_xilinx
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-
-design -load read
 
 synth_xilinx
 flatten
-- 
cgit v1.2.3


From 3b4408432073ec4d9a2b8995b8e08a5bf6175f39 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Sep 2019 19:57:26 -0700
Subject: Add -assert

---
 tests/xilinx/counter.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/xilinx/counter.ys b/tests/xilinx/counter.ys
index b602b74d7..3bb3a8eb0 100644
--- a/tests/xilinx/counter.ys
+++ b/tests/xilinx/counter.ys
@@ -2,7 +2,7 @@ read_verilog counter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
-- 
cgit v1.2.3


From a7fbc8c3fe1e2ad867ffc3456943644e70ab2575 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 08:19:26 +0200
Subject: Test per flip-flop type

---
 tests/xilinx/adffs.v  | 40 ----------------------------------------
 tests/xilinx/adffs.ys | 44 +++++++++++++++++++++++++++++++++++++-------
 2 files changed, 37 insertions(+), 47 deletions(-)

(limited to 'tests')

diff --git a/tests/xilinx/adffs.v b/tests/xilinx/adffs.v
index 05e68caf7..223b52d21 100644
--- a/tests/xilinx/adffs.v
+++ b/tests/xilinx/adffs.v
@@ -45,43 +45,3 @@ module ndffnr
 		else
             q <= d;
 endmodule
-
-module top (
-input clk,
-input clr,
-input pre,
-input a,
-output b,b1,b2,b3
-);
-
-dffs u_dffs (
-        .clk (clk ),
-        .clr (clr),
-        .pre (pre),
-        .d (a ),
-        .q (b )
-    );
-
-ndffnr u_ndffnr (
-        .clk (clk ),
-        .clr (clr),
-        .pre (pre),
-        .d (a ),
-        .q (b1 )
-    );
-
-adff u_adff (
-        .clk (clk ),
-        .clr (clr),
-        .d (a ),
-        .q (b2 )
-    );
-
-adffn u_adffn (
-        .clk (clk ),
-        .clr (clr),
-        .d (a ),
-        .q (b3 )
-    );
-
-endmodule
diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys
index 961e08ae9..7edab67c7 100644
--- a/tests/xilinx/adffs.ys
+++ b/tests/xilinx/adffs.ys
@@ -1,14 +1,44 @@
 read_verilog adffs.v
+design -save read
+
 proc
-flatten
-equiv_opt -multiclock -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+hierarchy -top adff
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd adff # Constrain all select calls below inside the top module
+select -assert-count 1 t:BUFG
+select -assert-count 1 t:FDCE
+select -assert-none t:BUFG t:FDCE %% t:* %D
+
+design -load read
+proc
+hierarchy -top adffn
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adffn # Constrain all select calls below inside the top module
+select -assert-count 1 t:BUFG
+select -assert-count 1 t:FDCE
+select -assert-count 1 t:LUT1
+select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D
 
+design -load read
+proc
+hierarchy -top dffs
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffs # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
-select -assert-count 2 t:FDCE
 select -assert-count 1 t:FDRE
+select -assert-count 1 t:LUT2
+select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D
+
+design -load read
+proc
+hierarchy -top ndffnr
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd ndffnr # Constrain all select calls below inside the top module
+select -assert-count 1 t:BUFG
 select -assert-count 1 t:FDRE_1
-select -assert-count 1 t:LUT1
-select -assert-count 2 t:LUT2
-select -assert-none t:BUFG t:FDCE t:FDRE t:FDRE_1 t:LUT1 t:LUT2 %% t:* %D
+select -assert-count 1 t:LUT2
+select -assert-none t:BUFG t:FDRE_1 t:LUT2 %% t:* %D
\ No newline at end of file
-- 
cgit v1.2.3


From d37cd267a56295737e95f5bc5e6f446c27605639 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 08:24:37 +0200
Subject: Removed alu and div_mod test as agreed, ignore generated files

---
 tests/xilinx/.gitignore |  1 +
 tests/xilinx/alu.v      | 19 -------------------
 tests/xilinx/alu.ys     | 21 ---------------------
 tests/xilinx/div_mod.v  | 13 -------------
 tests/xilinx/div_mod.ys | 17 -----------------
 5 files changed, 1 insertion(+), 70 deletions(-)
 delete mode 100644 tests/xilinx/alu.v
 delete mode 100644 tests/xilinx/alu.ys
 delete mode 100644 tests/xilinx/div_mod.v
 delete mode 100644 tests/xilinx/div_mod.ys

(limited to 'tests')

diff --git a/tests/xilinx/.gitignore b/tests/xilinx/.gitignore
index 54733fb71..89879f209 100644
--- a/tests/xilinx/.gitignore
+++ b/tests/xilinx/.gitignore
@@ -2,3 +2,4 @@
 /*.out
 /run-test.mk
 /*_uut.v
+/test_macc
\ No newline at end of file
diff --git a/tests/xilinx/alu.v b/tests/xilinx/alu.v
deleted file mode 100644
index f82cc2e21..000000000
--- a/tests/xilinx/alu.v
+++ /dev/null
@@ -1,19 +0,0 @@
-module top (
-	input clock,
-	input [31:0] dinA, dinB,
-	input [2:0] opcode,
-	output reg [31:0] dout
-);
-	always @(posedge clock) begin
-		case (opcode)
-		0: dout <= dinA + dinB;
-		1: dout <= dinA - dinB;
-		2: dout <= dinA >> dinB;
-		3: dout <= $signed(dinA) >>> dinB;
-		4: dout <= dinA << dinB;
-		5: dout <= dinA & dinB;
-		6: dout <= dinA | dinB;
-		7: dout <= dinA ^ dinB;
-		endcase
-	end
-endmodule
diff --git a/tests/xilinx/alu.ys b/tests/xilinx/alu.ys
deleted file mode 100644
index f85f03928..000000000
--- a/tests/xilinx/alu.ys
+++ /dev/null
@@ -1,21 +0,0 @@
-read_verilog alu.v
-hierarchy -top top
-proc
-flatten
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-
-
-select -assert-count 1 t:BUFG
-select -assert-count 32 t:LUT1
-select -assert-count 142 t:LUT2
-select -assert-count 55  t:LUT3
-select -assert-count 70  t:LUT4
-select -assert-count 46  t:LUT5
-select -assert-count 625 t:LUT6
-select -assert-count 62 t:MUXCY
-select -assert-count 265  t:MUXF7
-select -assert-count 79  t:MUXF8
-select -assert-count 64 t:XORCY
-select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
diff --git a/tests/xilinx/div_mod.v b/tests/xilinx/div_mod.v
deleted file mode 100644
index 64a36707d..000000000
--- a/tests/xilinx/div_mod.v
+++ /dev/null
@@ -1,13 +0,0 @@
-module top
-(
- input [3:0] x,
- input [3:0] y,
-
- output [3:0] A,
- output [3:0] B
- );
-
-assign A =  x % y;
-assign B =  x / y;
-
-endmodule
diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys
deleted file mode 100644
index da7e60a9a..000000000
--- a/tests/xilinx/div_mod.ys
+++ /dev/null
@@ -1,17 +0,0 @@
-read_verilog div_mod.v
-hierarchy -top top
-flatten
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-
-select -assert-count 12 t:LUT1
-select -assert-count 19 t:LUT2
-select -assert-count 13 t:LUT4
-select -assert-count 6  t:LUT5
-select -assert-count 82 t:LUT6
-select -assert-count 65 t:MUXCY
-select -assert-count 37 t:MUXF7
-select -assert-count 11 t:MUXF8
-select -assert-count 28 t:XORCY
-select -assert-none t:LUT1 t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
-- 
cgit v1.2.3


From 53bc499a907cc3bfbeb91866d8839286ae0dfdf1 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 08:27:49 +0200
Subject: Clean verilog code from not used define block

---
 tests/xilinx/shifter.v | 6 ------
 tests/xilinx/tribuf.v  | 6 ------
 2 files changed, 12 deletions(-)

(limited to 'tests')

diff --git a/tests/xilinx/shifter.v b/tests/xilinx/shifter.v
index c55632552..04ae49d83 100644
--- a/tests/xilinx/shifter.v
+++ b/tests/xilinx/shifter.v
@@ -9,14 +9,8 @@ in
 
     always @(posedge clk)
 	begin
-`ifndef BUG
 		out    <= out >> 1;
 		out[7] <= in;
-`else
-
-		out    <= out << 1;
-		out[7] <= in;
-`endif
 	end
 
 endmodule
diff --git a/tests/xilinx/tribuf.v b/tests/xilinx/tribuf.v
index 3fa6eb6c6..75149d8ba 100644
--- a/tests/xilinx/tribuf.v
+++ b/tests/xilinx/tribuf.v
@@ -2,15 +2,9 @@ module tristate (en, i, o);
     input en;
     input i;
     output reg o;
-`ifndef BUG 
     
     always @(en or i)
 		o <= (en)? i : 1'bZ;
-`else
-	
-    always @(en or i)
-		o <= (en)? ~i : 1'bZ;
-`endif
 endmodule
 
 
-- 
cgit v1.2.3


From fba6229718a45188514e016eec8678f1facb82a4 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 09:19:17 +0200
Subject: Fix formatting

---
 tests/xilinx/adffs.ys | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys
index 7edab67c7..2d23749ac 100644
--- a/tests/xilinx/adffs.ys
+++ b/tests/xilinx/adffs.ys
@@ -8,8 +8,10 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd adff # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
 select -assert-count 1 t:FDCE
+
 select -assert-none t:BUFG t:FDCE %% t:* %D
 
+
 design -load read
 proc
 hierarchy -top adffn
@@ -19,8 +21,10 @@ cd adffn # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
 select -assert-count 1 t:FDCE
 select -assert-count 1 t:LUT1
+
 select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D
 
+
 design -load read
 proc
 hierarchy -top dffs
@@ -30,8 +34,10 @@ cd dffs # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
 select -assert-count 1 t:FDRE
 select -assert-count 1 t:LUT2
+
 select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D
 
+
 design -load read
 proc
 hierarchy -top ndffnr
@@ -41,4 +47,5 @@ cd ndffnr # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
 select -assert-count 1 t:FDRE_1
 select -assert-count 1 t:LUT2
-select -assert-none t:BUFG t:FDRE_1 t:LUT2 %% t:* %D
\ No newline at end of file
+
+select -assert-none t:BUFG t:FDRE_1 t:LUT2 %% t:* %D
-- 
cgit v1.2.3


From 487b38b124cbb388bd680cb54cb43c58829ca1d3 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 09:24:22 +0200
Subject: Split latches into separete tests

---
 tests/xilinx/latches.v  | 34 ----------------------------------
 tests/xilinx/latches.ys | 35 +++++++++++++++++++++++++++--------
 2 files changed, 27 insertions(+), 42 deletions(-)

(limited to 'tests')

diff --git a/tests/xilinx/latches.v b/tests/xilinx/latches.v
index 9dc43e4c2..adb5d5319 100644
--- a/tests/xilinx/latches.v
+++ b/tests/xilinx/latches.v
@@ -22,37 +22,3 @@ module latchsr
 		else if ( en )
 			q <= d;
 endmodule
-
-
-module top (
-input clk,
-input clr,
-input pre,
-input a,
-output b,b1,b2
-);
-
-
-latchp u_latchp (
-        .en (clk ),
-        .d (a ),
-        .q (b )
-    );
-
-
-latchn u_latchn (
-        .en (clk ),
-        .d (a ),
-        .q (b1 )
-    );
-
-
-latchsr u_latchsr (
-        .en (clk ),
-        .clr (clr),
-        .pre (pre),
-        .d (a ),
-        .q (b2 )
-    );
-
-endmodule
diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys
index 795ac9074..68ca42b10 100644
--- a/tests/xilinx/latches.ys
+++ b/tests/xilinx/latches.ys
@@ -2,15 +2,34 @@ read_verilog latches.v
 design -save read
 
 proc
-async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock
-flatten
+hierarchy -top latchp
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd latchp # Constrain all select calls below inside the top module
+select -assert-count 1 t:LDCE
 
-synth_xilinx
-flatten
-cd top
+select -assert-none t:LDCE %% t:* %D
+
+
+design -load read
+proc
+hierarchy -top latchn
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd latchn # Constrain all select calls below inside the top module
+select -assert-count 1 t:LDCE
 select -assert-count 1 t:LUT1
+
+select -assert-none t:LDCE t:LUT1 %% t:* %D
+
+
+design -load read
+proc
+hierarchy -top latchsr
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd latchsr # Constrain all select calls below inside the top module
+select -assert-count 1 t:LDCE
 select -assert-count 2 t:LUT3
-#Xilinx Vivado synthesizes LDCE cell for this case. Need support it.
-select -assert-count 3 t:$_DLATCH_P_
-select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D
+
+select -assert-none t:LDCE t:LUT3 %% t:* %D
-- 
cgit v1.2.3


From 36af10280136f0fda7b743075ac52e48576abf26 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 09:28:18 +0200
Subject: Test dffs separetely

---
 tests/xilinx/dffs.v  | 22 ----------------------
 tests/xilinx/dffs.ys | 23 +++++++++++++++++++----
 2 files changed, 19 insertions(+), 26 deletions(-)

(limited to 'tests')

diff --git a/tests/xilinx/dffs.v b/tests/xilinx/dffs.v
index d97840c43..3418787c9 100644
--- a/tests/xilinx/dffs.v
+++ b/tests/xilinx/dffs.v
@@ -13,25 +13,3 @@ module dffe
 		if ( en )
 			q <= d;
 endmodule
-
-module top (
-input clk,
-input en,
-input a,
-output b,b1,
-);
-
-dff u_dff (
-        .clk (clk ),
-        .d (a ),
-        .q (b )
-    );
-
-dffe u_ndffe (
-        .clk (clk ),
-        .en (en),
-        .d (a ),
-        .q (b1 )
-    );
-
-endmodule
diff --git a/tests/xilinx/dffs.ys b/tests/xilinx/dffs.ys
index 6a98994c0..2d48a816c 100644
--- a/tests/xilinx/dffs.ys
+++ b/tests/xilinx/dffs.ys
@@ -1,10 +1,25 @@
 read_verilog dffs.v
-hierarchy -top top
+design -save read
+
 proc
-flatten
+hierarchy -top dff
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd dff # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
-select -assert-count 2 t:FDRE
+select -assert-count 1 t:FDRE
+
 select -assert-none t:BUFG t:FDRE %% t:* %D
+
+
+design -load read
+proc
+hierarchy -top dffe
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffe # Constrain all select calls below inside the top module
+select -assert-count 1 t:BUFG
+select -assert-count 1 t:FDRE
+
+select -assert-none t:BUFG t:FDRE %% t:* %D
+
-- 
cgit v1.2.3


From a198bcdd4ffe6b09787ea5bf2e69528ace375020 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 09:39:22 +0200
Subject: split muxes synth per type

---
 tests/xilinx/mux.v  | 35 -----------------------------------
 tests/xilinx/mux.ys | 43 +++++++++++++++++++++++++++++++++++++++----
 2 files changed, 39 insertions(+), 39 deletions(-)

(limited to 'tests')

diff --git a/tests/xilinx/mux.v b/tests/xilinx/mux.v
index 0814b733e..27bc0bf0b 100644
--- a/tests/xilinx/mux.v
+++ b/tests/xilinx/mux.v
@@ -63,38 +63,3 @@ module mux16 (D, S, Y);
 assign Y = D[S];
 
 endmodule
-
-
-module top (
-input [3:0] S,
-input [15:0] D,
-output M2,M4,M8,M16
-);
-
-mux2 u_mux2 (
-        .S (S[0]),
-        .A (D[0]),
-        .B (D[1]),
-        .Y (M2)
-    );
-
-
-mux4 u_mux4 (
-        .S (S[1:0]),
-        .D (D[3:0]),
-        .Y (M4)
-    );
-
-mux8 u_mux8 (
-        .S (S[2:0]),
-        .D (D[7:0]),
-        .Y (M8)
-    );
-
-mux16 u_mux16 (
-        .S (S[3:0]),
-        .D (D[15:0]),
-        .Y (M16)
-    );
-
-endmodule
diff --git a/tests/xilinx/mux.ys b/tests/xilinx/mux.ys
index 6ecee58f5..4cdb12e47 100644
--- a/tests/xilinx/mux.ys
+++ b/tests/xilinx/mux.ys
@@ -1,10 +1,45 @@
 read_verilog mux.v
+design -save read
+
+proc
+hierarchy -top mux2
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux2 # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT3
+
+select -assert-none t:LUT3 %% t:* %D
+
+
+design -load read
 proc
-flatten
+hierarchy -top mux4
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd mux4 # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT6
+
+select -assert-none t:LUT6 %% t:* %D
+
+
+design -load read
+proc
+hierarchy -top mux8
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux8 # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT3
+select -assert-count 2 t:LUT6
 
-select -assert-count 2  t:LUT3
-select -assert-count 5  t:LUT6
 select -assert-none t:LUT3 t:LUT6 %% t:* %D
+
+
+design -load read
+proc
+hierarchy -top mux16
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux16 # Constrain all select calls below inside the top module
+select -assert-count 5 t:LUT6
+
+select -assert-none t:LUT6 %% t:* %D
-- 
cgit v1.2.3


From 1a399c6456b6ca7becf89a5c825b2c8d7b34dc3e Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 09:39:34 +0200
Subject: remove not needed top module

---
 tests/xilinx/tribuf.v  | 15 ---------------
 tests/xilinx/tribuf.ys |  4 ++--
 2 files changed, 2 insertions(+), 17 deletions(-)

(limited to 'tests')

diff --git a/tests/xilinx/tribuf.v b/tests/xilinx/tribuf.v
index 75149d8ba..c64468253 100644
--- a/tests/xilinx/tribuf.v
+++ b/tests/xilinx/tribuf.v
@@ -6,18 +6,3 @@ module tristate (en, i, o);
     always @(en or i)
 		o <= (en)? i : 1'bZ;
 endmodule
-
-
-module top (
-input en,
-input a,
-output b
-);
-
-tristate u_tri (
-        .en (en ),
-        .i (a ),
-        .o (b )
-    );
-
-endmodule
diff --git a/tests/xilinx/tribuf.ys b/tests/xilinx/tribuf.ys
index 696be2620..c9cfb8546 100644
--- a/tests/xilinx/tribuf.ys
+++ b/tests/xilinx/tribuf.ys
@@ -1,12 +1,12 @@
 read_verilog tribuf.v
-hierarchy -top top
+hierarchy -top tristate
 proc
 tribuf
 flatten
 synth
 equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd tristate # Constrain all select calls below inside the top module
 # TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225
 select -assert-count 1 t:$_TBUF_
 select -assert-none t:$_TBUF_ %% t:* %D
-- 
cgit v1.2.3


From b2f0d75807c99c74f9860098b74e8300514ba9e5 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 09:41:45 +0200
Subject: remove not needed top module

---
 tests/xilinx/fsm.v  | 18 ------------------
 tests/xilinx/fsm.ys |  4 ++--
 2 files changed, 2 insertions(+), 20 deletions(-)

(limited to 'tests')

diff --git a/tests/xilinx/fsm.v b/tests/xilinx/fsm.v
index 0605bd102..368fbaace 100644
--- a/tests/xilinx/fsm.v
+++ b/tests/xilinx/fsm.v
@@ -52,22 +52,4 @@
  endcase
  end
 
- endmodule
-
- module top (
-input clk,
-input rst,
-input a,
-input b,
-output g0,
-output g1
-);
-
-fsm u_fsm ( .clock(clk),
-            .reset(rst),
-            .req_0(a),
-            .req_1(b),
-            .gnt_0(g0),
-            .gnt_1(g1));
-
 endmodule
diff --git a/tests/xilinx/fsm.ys b/tests/xilinx/fsm.ys
index 3b73891c2..a9e94c2c0 100644
--- a/tests/xilinx/fsm.ys
+++ b/tests/xilinx/fsm.ys
@@ -1,10 +1,10 @@
 read_verilog fsm.v
-hierarchy -top top
+hierarchy -top fsm
 proc
 flatten
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd fsm # Constrain all select calls below inside the top module
 
 select -assert-count 1 t:BUFG
 select -assert-count 5 t:FDRE
-- 
cgit v1.2.3


From 980df499abb63e5dfadc29b3326032b55b6dbf18 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 17 Oct 2019 17:24:53 +0200
Subject: Make equivalence work with latest master

---
 tests/xilinx/adffs.ys   | 8 ++++----
 tests/xilinx/counter.ys | 2 +-
 tests/xilinx/latches.ys | 6 +++---
 3 files changed, 8 insertions(+), 8 deletions(-)

(limited to 'tests')

diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys
index 2d23749ac..9e8ba44ab 100644
--- a/tests/xilinx/adffs.ys
+++ b/tests/xilinx/adffs.ys
@@ -3,7 +3,7 @@ design -save read
 
 proc
 hierarchy -top adff
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adff # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
@@ -15,7 +15,7 @@ select -assert-none t:BUFG t:FDCE %% t:* %D
 design -load read
 proc
 hierarchy -top adffn
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adffn # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
@@ -28,7 +28,7 @@ select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D
 design -load read
 proc
 hierarchy -top dffs
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffs # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
@@ -41,7 +41,7 @@ select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D
 design -load read
 proc
 hierarchy -top ndffnr
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd ndffnr # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
diff --git a/tests/xilinx/counter.ys b/tests/xilinx/counter.ys
index 3bb3a8eb0..459541656 100644
--- a/tests/xilinx/counter.ys
+++ b/tests/xilinx/counter.ys
@@ -2,7 +2,7 @@ read_verilog counter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys
index 68ca42b10..52e96834d 100644
--- a/tests/xilinx/latches.ys
+++ b/tests/xilinx/latches.ys
@@ -3,7 +3,7 @@ design -save read
 
 proc
 hierarchy -top latchp
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd latchp # Constrain all select calls below inside the top module
 select -assert-count 1 t:LDCE
@@ -14,7 +14,7 @@ select -assert-none t:LDCE %% t:* %D
 design -load read
 proc
 hierarchy -top latchn
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd latchn # Constrain all select calls below inside the top module
 select -assert-count 1 t:LDCE
@@ -26,7 +26,7 @@ select -assert-none t:LDCE t:LUT1 %% t:* %D
 design -load read
 proc
 hierarchy -top latchsr
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd latchsr # Constrain all select calls below inside the top module
 select -assert-count 1 t:LDCE
-- 
cgit v1.2.3


From e6ad714d20134612521e995c72e4fa06ed791dd3 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 18 Oct 2019 08:06:57 +0200
Subject: hierarchy - proc reorder

---
 tests/xilinx/.gitignore      | 2 +-
 tests/xilinx/add_sub.ys      | 1 +
 tests/xilinx/adffs.ys        | 8 ++++----
 tests/xilinx/dffs.ys         | 4 ++--
 tests/xilinx/latches.ys      | 6 +++---
 tests/xilinx/logic.ys        | 1 +
 tests/xilinx/macc.ys         | 4 ++--
 tests/xilinx/mul.ys          | 1 +
 tests/xilinx/mul_unsigned.ys | 3 ++-
 tests/xilinx/mux.ys          | 8 ++++----
 10 files changed, 21 insertions(+), 17 deletions(-)

(limited to 'tests')

diff --git a/tests/xilinx/.gitignore b/tests/xilinx/.gitignore
index 89879f209..c99b79371 100644
--- a/tests/xilinx/.gitignore
+++ b/tests/xilinx/.gitignore
@@ -2,4 +2,4 @@
 /*.out
 /run-test.mk
 /*_uut.v
-/test_macc
\ No newline at end of file
+/test_macc
diff --git a/tests/xilinx/add_sub.ys b/tests/xilinx/add_sub.ys
index 821341f20..f06e7fa01 100644
--- a/tests/xilinx/add_sub.ys
+++ b/tests/xilinx/add_sub.ys
@@ -1,5 +1,6 @@
 read_verilog add_sub.v
 hierarchy -top top
+proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys
index 9e8ba44ab..1923b9802 100644
--- a/tests/xilinx/adffs.ys
+++ b/tests/xilinx/adffs.ys
@@ -1,8 +1,8 @@
 read_verilog adffs.v
 design -save read
 
-proc
 hierarchy -top adff
+proc
 equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adff # Constrain all select calls below inside the top module
@@ -13,8 +13,8 @@ select -assert-none t:BUFG t:FDCE %% t:* %D
 
 
 design -load read
-proc
 hierarchy -top adffn
+proc
 equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adffn # Constrain all select calls below inside the top module
@@ -26,8 +26,8 @@ select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D
 
 
 design -load read
-proc
 hierarchy -top dffs
+proc
 equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffs # Constrain all select calls below inside the top module
@@ -39,8 +39,8 @@ select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D
 
 
 design -load read
-proc
 hierarchy -top ndffnr
+proc
 equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd ndffnr # Constrain all select calls below inside the top module
diff --git a/tests/xilinx/dffs.ys b/tests/xilinx/dffs.ys
index 2d48a816c..f1716dabb 100644
--- a/tests/xilinx/dffs.ys
+++ b/tests/xilinx/dffs.ys
@@ -1,8 +1,8 @@
 read_verilog dffs.v
 design -save read
 
-proc
 hierarchy -top dff
+proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dff # Constrain all select calls below inside the top module
@@ -13,8 +13,8 @@ select -assert-none t:BUFG t:FDRE %% t:* %D
 
 
 design -load read
-proc
 hierarchy -top dffe
+proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffe # Constrain all select calls below inside the top module
diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys
index 52e96834d..3eb550a42 100644
--- a/tests/xilinx/latches.ys
+++ b/tests/xilinx/latches.ys
@@ -1,8 +1,8 @@
 read_verilog latches.v
 design -save read
 
-proc
 hierarchy -top latchp
+proc
 equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd latchp # Constrain all select calls below inside the top module
@@ -12,8 +12,8 @@ select -assert-none t:LDCE %% t:* %D
 
 
 design -load read
-proc
 hierarchy -top latchn
+proc
 equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd latchn # Constrain all select calls below inside the top module
@@ -24,8 +24,8 @@ select -assert-none t:LDCE t:LUT1 %% t:* %D
 
 
 design -load read
-proc
 hierarchy -top latchsr
+proc
 equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd latchsr # Constrain all select calls below inside the top module
diff --git a/tests/xilinx/logic.ys b/tests/xilinx/logic.ys
index e138ae6a3..9ae5993aa 100644
--- a/tests/xilinx/logic.ys
+++ b/tests/xilinx/logic.ys
@@ -1,5 +1,6 @@
 read_verilog logic.v
 hierarchy -top top
+proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
diff --git a/tests/xilinx/macc.ys b/tests/xilinx/macc.ys
index 417a3b21b..6e884b35a 100644
--- a/tests/xilinx/macc.ys
+++ b/tests/xilinx/macc.ys
@@ -1,8 +1,8 @@
 read_verilog macc.v
 design -save read
 
-proc
 hierarchy -top macc
+proc
 #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO
 equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
@@ -15,8 +15,8 @@ select -assert-count 1 t:DSP48E1
 select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D
 
 design -load read
-proc
 hierarchy -top macc2
+proc
 #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO
 equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
diff --git a/tests/xilinx/mul.ys b/tests/xilinx/mul.ys
index f5306e848..66a06efdc 100644
--- a/tests/xilinx/mul.ys
+++ b/tests/xilinx/mul.ys
@@ -1,5 +1,6 @@
 read_verilog mul.v
 hierarchy -top top
+proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
diff --git a/tests/xilinx/mul_unsigned.ys b/tests/xilinx/mul_unsigned.ys
index 77990bd68..62495b90c 100644
--- a/tests/xilinx/mul_unsigned.ys
+++ b/tests/xilinx/mul_unsigned.ys
@@ -1,6 +1,7 @@
 read_verilog mul_unsigned.v
-proc
 hierarchy -top mul_unsigned
+proc
+
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mul_unsigned # Constrain all select calls below inside the top module
diff --git a/tests/xilinx/mux.ys b/tests/xilinx/mux.ys
index 4cdb12e47..420dece4e 100644
--- a/tests/xilinx/mux.ys
+++ b/tests/xilinx/mux.ys
@@ -1,8 +1,8 @@
 read_verilog mux.v
 design -save read
 
-proc
 hierarchy -top mux2
+proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux2 # Constrain all select calls below inside the top module
@@ -12,8 +12,8 @@ select -assert-none t:LUT3 %% t:* %D
 
 
 design -load read
-proc
 hierarchy -top mux4
+proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
@@ -23,8 +23,8 @@ select -assert-none t:LUT6 %% t:* %D
 
 
 design -load read
-proc
 hierarchy -top mux8
+proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
@@ -35,8 +35,8 @@ select -assert-none t:LUT3 t:LUT6 %% t:* %D
 
 
 design -load read
-proc
 hierarchy -top mux16
+proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
-- 
cgit v1.2.3