From 07c4a7d4388cdacaa15512dd2f6f0f9e9fcb31f5 Mon Sep 17 00:00:00 2001
From: Bogdan Vukobratovic <bogdan.vukobratovic@gmail.com>
Date: Fri, 26 Jul 2019 11:36:48 +0200
Subject: Implement opt_share

This pass identifies arithmetic operators that share an operand and whose
results are used in mutually exclusive cases controlled by a multiplexer, and
merges them together by multiplexing the other operands
---
 tests/opt/opt_share_cat.v       | 15 +++++++++++++++
 tests/opt/opt_share_cat.ys      |  9 +++++++++
 tests/opt/opt_share_mux_tree.v  | 19 +++++++++++++++++++
 tests/opt/opt_share_mux_tree.ys | 10 ++++++++++
 4 files changed, 53 insertions(+)
 create mode 100644 tests/opt/opt_share_cat.v
 create mode 100644 tests/opt/opt_share_cat.ys
 create mode 100644 tests/opt/opt_share_mux_tree.v
 create mode 100644 tests/opt/opt_share_mux_tree.ys

(limited to 'tests')

diff --git a/tests/opt/opt_share_cat.v b/tests/opt/opt_share_cat.v
new file mode 100644
index 000000000..c32073360
--- /dev/null
+++ b/tests/opt/opt_share_cat.v
@@ -0,0 +1,15 @@
+module add_sub(
+               input [15:0]  a,
+               input [15:0]  b,
+               input [15:0]  c,
+               input [15:0]  d,
+               input 				 sel,
+               output [63:0] res,
+               );
+
+  reg [31: 0] 							 cat1 = {a+b, c+d};
+  reg [31: 0] 							 cat2 = {a-b, c-d};
+
+  assign res = {b, sel ? cat1 : cat2, a};
+
+endmodule
diff --git a/tests/opt/opt_share_cat.ys b/tests/opt/opt_share_cat.ys
new file mode 100644
index 000000000..c3f2f5a2f
--- /dev/null
+++ b/tests/opt/opt_share_cat.ys
@@ -0,0 +1,9 @@
+read_verilog opt_share_cat.v
+prep -flatten
+opt
+pmuxtree
+opt_share
+opt_clean
+
+select -assert-count 2 t:$sub
+select -assert-count 0 t:$add
diff --git a/tests/opt/opt_share_mux_tree.v b/tests/opt/opt_share_mux_tree.v
new file mode 100644
index 000000000..807ed2978
--- /dev/null
+++ b/tests/opt/opt_share_mux_tree.v
@@ -0,0 +1,19 @@
+module add_sub(
+               input [15:0] 		 a,
+               input [15:0] 		 b,
+               input [15:0] 		 c,
+               input [1:0] 			 sel,
+               output reg [15:0] res
+               );
+
+
+  always @* begin
+    case(sel)
+      0: res = a + b;
+      1: res = a - b;
+      2: res = a + c;
+      default: res = 16'bx;
+    endcase
+  end
+
+endmodule
diff --git a/tests/opt/opt_share_mux_tree.ys b/tests/opt/opt_share_mux_tree.ys
new file mode 100644
index 000000000..94d6aa7d2
--- /dev/null
+++ b/tests/opt/opt_share_mux_tree.ys
@@ -0,0 +1,10 @@
+read_verilog opt_share_mux_tree.v
+prep -flatten
+opt
+pmuxtree
+opt_share;
+opt_share;
+opt_clean
+
+select -assert-count 1 t:$add
+select -assert-count 0 t:$sub
-- 
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