From 01626e6746e85832d5b75785b9e45f39ff8eb299 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Thu, 14 Jan 2021 09:58:33 +0100
Subject: opt_share: Fix X and CO signal width for shifted $alu in opt_share.

These need to be the same length as actual Y, not visible part of Y.

Fixes #2538.
---
 tests/opt/opt_share_bug2538.ys | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100644 tests/opt/opt_share_bug2538.ys

(limited to 'tests')

diff --git a/tests/opt/opt_share_bug2538.ys b/tests/opt/opt_share_bug2538.ys
new file mode 100644
index 000000000..7261c6695
--- /dev/null
+++ b/tests/opt/opt_share_bug2538.ys
@@ -0,0 +1,20 @@
+read_verilog <<EOT
+
+module top(...);
+
+input [3:0] A;
+input S;
+output [1:0] Y;
+
+wire [3:0] A1 = A + 1;
+wire [3:0] A2 = A + 2;
+assign Y = S ? A1[3:2] : A2[3:2];
+
+endmodule
+
+EOT
+
+proc
+alumacc
+equiv_opt -assert opt_share
+
-- 
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