From 5d680590d6bccd929ed3909248dbb73fb3876e65 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 3 Oct 2019 10:30:33 -0700
Subject: Use equiv_opt -async2sync for xilinx

---
 tests/xilinx/latches.ys | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

(limited to 'tests/xilinx')

diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys
index ac1102896..bd1dffd21 100644
--- a/tests/xilinx/latches.ys
+++ b/tests/xilinx/latches.ys
@@ -2,9 +2,7 @@ read_verilog latches.v
 
 proc
 flatten
-equiv_opt -assert -run :prove -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-async2sync
-equiv_opt -assert -run prove: -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 
 design -load preopt
 synth_xilinx
-- 
cgit v1.2.3


From 757c476f625bef871f9a4388d4d19bf8c3bc400b Mon Sep 17 00:00:00 2001
From: SergeyDegtyar <sndegtyar@gmail.com>
Date: Tue, 10 Sep 2019 08:08:03 +0300
Subject: Add smoke tests to tests/xilinx

---
 tests/xilinx/add_sub.v   |  13 ++++++
 tests/xilinx/add_sub.ys  |  10 +++++
 tests/xilinx/adffs.v     |  91 ++++++++++++++++++++++++++++++++++++++++++
 tests/xilinx/adffs.ys    |  14 +++++++
 tests/xilinx/alu.v       |  19 +++++++++
 tests/xilinx/alu.ys      |  21 ++++++++++
 tests/xilinx/counter.v   |  17 ++++++++
 tests/xilinx/counter.ys  |  14 +++++++
 tests/xilinx/dffs.v      |  37 ++++++++++++++++++
 tests/xilinx/dffs.ys     |  10 +++++
 tests/xilinx/div_mod.v   |  13 ++++++
 tests/xilinx/div_mod.ys  |  17 ++++++++
 tests/xilinx/fsm.v       |  73 ++++++++++++++++++++++++++++++++++
 tests/xilinx/fsm.ys      |  14 +++++++
 tests/xilinx/latches.v   |   6 +--
 tests/xilinx/latches.ys  |  17 +++++---
 tests/xilinx/logic.v     |  18 +++++++++
 tests/xilinx/logic.ys    |  10 +++++
 tests/xilinx/memory.v    |  21 ++++++++++
 tests/xilinx/memory.ys   |  17 ++++++++
 tests/xilinx/mul.v       |  11 ++++++
 tests/xilinx/mul.ys      |  15 +++++++
 tests/xilinx/mux.v       | 100 +++++++++++++++++++++++++++++++++++++++++++++++
 tests/xilinx/mux.ys      |  10 +++++
 tests/xilinx/run-test.sh |   2 +-
 tests/xilinx/shifter.v   |  22 +++++++++++
 tests/xilinx/shifter.ys  |  11 ++++++
 tests/xilinx/tribuf.v    |  29 ++++++++++++++
 tests/xilinx/tribuf.ys   |  11 ++++++
 29 files changed, 654 insertions(+), 9 deletions(-)
 create mode 100644 tests/xilinx/add_sub.v
 create mode 100644 tests/xilinx/add_sub.ys
 create mode 100644 tests/xilinx/adffs.v
 create mode 100644 tests/xilinx/adffs.ys
 create mode 100644 tests/xilinx/alu.v
 create mode 100644 tests/xilinx/alu.ys
 create mode 100644 tests/xilinx/counter.v
 create mode 100644 tests/xilinx/counter.ys
 create mode 100644 tests/xilinx/dffs.v
 create mode 100644 tests/xilinx/dffs.ys
 create mode 100644 tests/xilinx/div_mod.v
 create mode 100644 tests/xilinx/div_mod.ys
 create mode 100644 tests/xilinx/fsm.v
 create mode 100644 tests/xilinx/fsm.ys
 create mode 100644 tests/xilinx/logic.v
 create mode 100644 tests/xilinx/logic.ys
 create mode 100644 tests/xilinx/memory.v
 create mode 100644 tests/xilinx/memory.ys
 create mode 100644 tests/xilinx/mul.v
 create mode 100644 tests/xilinx/mul.ys
 create mode 100644 tests/xilinx/mux.v
 create mode 100644 tests/xilinx/mux.ys
 create mode 100644 tests/xilinx/shifter.v
 create mode 100644 tests/xilinx/shifter.ys
 create mode 100644 tests/xilinx/tribuf.v
 create mode 100644 tests/xilinx/tribuf.ys

(limited to 'tests/xilinx')

diff --git a/tests/xilinx/add_sub.v b/tests/xilinx/add_sub.v
new file mode 100644
index 000000000..177c32e30
--- /dev/null
+++ b/tests/xilinx/add_sub.v
@@ -0,0 +1,13 @@
+module top
+(
+ input [3:0] x,
+ input [3:0] y,
+
+ output [3:0] A,
+ output [3:0] B
+ );
+
+assign A =  x + y;
+assign B =  x - y;
+
+endmodule
diff --git a/tests/xilinx/add_sub.ys b/tests/xilinx/add_sub.ys
new file mode 100644
index 000000000..821341f20
--- /dev/null
+++ b/tests/xilinx/add_sub.ys
@@ -0,0 +1,10 @@
+read_verilog add_sub.v
+hierarchy -top top
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 14 t:LUT2
+select -assert-count 6 t:MUXCY
+select -assert-count 8 t:XORCY
+select -assert-none t:LUT2 t:MUXCY t:XORCY %% t:* %D
+
diff --git a/tests/xilinx/adffs.v b/tests/xilinx/adffs.v
new file mode 100644
index 000000000..93c8bf52c
--- /dev/null
+++ b/tests/xilinx/adffs.v
@@ -0,0 +1,91 @@
+module adff
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+			q <= 1'b0;
+		else
+            q <= d;
+endmodule
+
+module adffn
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+			q <= 1'b0;
+		else
+            q <= d;
+endmodule
+
+module dffsr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge pre, posedge clr )
+		if ( clr )
+			q <= 1'b0;
+		else if ( pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module ndffnsnr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk, negedge pre, negedge clr )
+		if ( !clr )
+			q <= 1'b0;
+		else if ( !pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2,b3
+);
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+
+ndffnsnr u_ndffnsnr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b1 )
+    );
+
+adff u_adff (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b2 )
+    );
+
+adffn u_adffn (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b3 )
+    );
+
+endmodule
diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys
new file mode 100644
index 000000000..96d8e176f
--- /dev/null
+++ b/tests/xilinx/adffs.ys
@@ -0,0 +1,14 @@
+read_verilog adffs.v
+proc
+async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock
+flatten
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:BUFG
+select -assert-count 3 t:FDRE
+select -assert-count 1 t:FDRE_1
+select -assert-count 4 t:LUT2
+select -assert-count 4 t:LUT3
+select -assert-none t:BUFG t:FDRE t:FDRE_1 t:LUT2 t:LUT3 %% t:* %D
diff --git a/tests/xilinx/alu.v b/tests/xilinx/alu.v
new file mode 100644
index 000000000..f82cc2e21
--- /dev/null
+++ b/tests/xilinx/alu.v
@@ -0,0 +1,19 @@
+module top (
+	input clock,
+	input [31:0] dinA, dinB,
+	input [2:0] opcode,
+	output reg [31:0] dout
+);
+	always @(posedge clock) begin
+		case (opcode)
+		0: dout <= dinA + dinB;
+		1: dout <= dinA - dinB;
+		2: dout <= dinA >> dinB;
+		3: dout <= $signed(dinA) >>> dinB;
+		4: dout <= dinA << dinB;
+		5: dout <= dinA & dinB;
+		6: dout <= dinA | dinB;
+		7: dout <= dinA ^ dinB;
+		endcase
+	end
+endmodule
diff --git a/tests/xilinx/alu.ys b/tests/xilinx/alu.ys
new file mode 100644
index 000000000..f85f03928
--- /dev/null
+++ b/tests/xilinx/alu.ys
@@ -0,0 +1,21 @@
+read_verilog alu.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+
+select -assert-count 1 t:BUFG
+select -assert-count 32 t:LUT1
+select -assert-count 142 t:LUT2
+select -assert-count 55  t:LUT3
+select -assert-count 70  t:LUT4
+select -assert-count 46  t:LUT5
+select -assert-count 625 t:LUT6
+select -assert-count 62 t:MUXCY
+select -assert-count 265  t:MUXF7
+select -assert-count 79  t:MUXF8
+select -assert-count 64 t:XORCY
+select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
diff --git a/tests/xilinx/counter.v b/tests/xilinx/counter.v
new file mode 100644
index 000000000..52852f8ac
--- /dev/null
+++ b/tests/xilinx/counter.v
@@ -0,0 +1,17 @@
+module top    (
+out,
+clk,
+reset
+);
+    output [7:0] out;
+    input clk, reset;
+    reg [7:0] out;
+
+    always @(posedge clk, posedge reset)
+		if (reset) begin
+			out <= 8'b0 ;
+		end else
+			out <= out + 1;
+
+
+endmodule
diff --git a/tests/xilinx/counter.ys b/tests/xilinx/counter.ys
new file mode 100644
index 000000000..b602b74d7
--- /dev/null
+++ b/tests/xilinx/counter.ys
@@ -0,0 +1,14 @@
+read_verilog counter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:BUFG
+select -assert-count 8 t:FDCE
+select -assert-count 1 t:LUT1
+select -assert-count 7 t:MUXCY
+select -assert-count 8 t:XORCY
+select -assert-none t:BUFG t:FDCE t:LUT1 t:MUXCY t:XORCY %% t:* %D
diff --git a/tests/xilinx/dffs.v b/tests/xilinx/dffs.v
new file mode 100644
index 000000000..d97840c43
--- /dev/null
+++ b/tests/xilinx/dffs.v
@@ -0,0 +1,37 @@
+module dff
+    ( input d, clk, output reg q );
+	always @( posedge clk )
+            q <= d;
+endmodule
+
+module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk )
+		if ( en )
+			q <= d;
+endmodule
+
+module top (
+input clk,
+input en,
+input a,
+output b,b1,
+);
+
+dff u_dff (
+        .clk (clk ),
+        .d (a ),
+        .q (b )
+    );
+
+dffe u_ndffe (
+        .clk (clk ),
+        .en (en),
+        .d (a ),
+        .q (b1 )
+    );
+
+endmodule
diff --git a/tests/xilinx/dffs.ys b/tests/xilinx/dffs.ys
new file mode 100644
index 000000000..6a98994c0
--- /dev/null
+++ b/tests/xilinx/dffs.ys
@@ -0,0 +1,10 @@
+read_verilog dffs.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:BUFG
+select -assert-count 2 t:FDRE
+select -assert-none t:BUFG t:FDRE %% t:* %D
diff --git a/tests/xilinx/div_mod.v b/tests/xilinx/div_mod.v
new file mode 100644
index 000000000..64a36707d
--- /dev/null
+++ b/tests/xilinx/div_mod.v
@@ -0,0 +1,13 @@
+module top
+(
+ input [3:0] x,
+ input [3:0] y,
+
+ output [3:0] A,
+ output [3:0] B
+ );
+
+assign A =  x % y;
+assign B =  x / y;
+
+endmodule
diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys
new file mode 100644
index 000000000..cc00b1a27
--- /dev/null
+++ b/tests/xilinx/div_mod.ys
@@ -0,0 +1,17 @@
+read_verilog div_mod.v
+hierarchy -top top
+flatten
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 12 t:LUT1
+select -assert-count 21 t:LUT2
+select -assert-count 13 t:LUT4
+select -assert-count 6  t:LUT5
+select -assert-count 80 t:LUT6
+select -assert-count 65 t:MUXCY
+select -assert-count 36 t:MUXF7
+select -assert-count 9  t:MUXF8
+select -assert-count 28 t:XORCY
+select -assert-none t:LUT1 t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
diff --git a/tests/xilinx/fsm.v b/tests/xilinx/fsm.v
new file mode 100644
index 000000000..0605bd102
--- /dev/null
+++ b/tests/xilinx/fsm.v
@@ -0,0 +1,73 @@
+ module fsm (
+ clock,
+ reset,
+ req_0,
+ req_1,
+ gnt_0,
+ gnt_1
+ );
+ input   clock,reset,req_0,req_1;
+ output  gnt_0,gnt_1;
+ wire    clock,reset,req_0,req_1;
+ reg     gnt_0,gnt_1;
+
+ parameter SIZE = 3           ;
+ parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;
+
+ reg [SIZE-1:0] state;
+ reg [SIZE-1:0] next_state;
+
+ always @ (posedge clock)
+ begin : FSM
+ if (reset == 1'b1) begin
+   state <=  #1  IDLE;
+   gnt_0 <= 0;
+   gnt_1 <= 0;
+ end else
+  case(state)
+    IDLE : if (req_0 == 1'b1) begin
+                 state <=  #1  GNT0;
+                 gnt_0 <= 1;
+               end else if (req_1 == 1'b1) begin
+                 gnt_1 <= 1;
+                 state <=  #1  GNT0;
+               end else begin
+                 state <=  #1  IDLE;
+               end
+    GNT0 : if (req_0 == 1'b1) begin
+                 state <=  #1  GNT0;
+               end else begin
+                 gnt_0 <= 0;
+                 state <=  #1  IDLE;
+               end
+    GNT1 : if (req_1 == 1'b1) begin
+                 state <=  #1  GNT2;
+				 gnt_1 <= req_0;
+               end
+    GNT2 : if (req_0 == 1'b1) begin
+                 state <=  #1  GNT1;
+				 gnt_1 <= req_1;
+               end
+    default : state <=  #1  IDLE;
+ endcase
+ end
+
+ endmodule
+
+ module top (
+input clk,
+input rst,
+input a,
+input b,
+output g0,
+output g1
+);
+
+fsm u_fsm ( .clock(clk),
+            .reset(rst),
+            .req_0(a),
+            .req_1(b),
+            .gnt_0(g0),
+            .gnt_1(g1));
+
+endmodule
diff --git a/tests/xilinx/fsm.ys b/tests/xilinx/fsm.ys
new file mode 100644
index 000000000..3b73891c2
--- /dev/null
+++ b/tests/xilinx/fsm.ys
@@ -0,0 +1,14 @@
+read_verilog fsm.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:BUFG
+select -assert-count 5 t:FDRE
+select -assert-count 1 t:LUT3
+select -assert-count 2 t:LUT4
+select -assert-count 4 t:LUT6
+select -assert-none t:BUFG t:FDRE t:LUT3 t:LUT4 t:LUT6 %% t:* %D
diff --git a/tests/xilinx/latches.v b/tests/xilinx/latches.v
index 83bad7f35..9dc43e4c2 100644
--- a/tests/xilinx/latches.v
+++ b/tests/xilinx/latches.v
@@ -1,19 +1,19 @@
 module latchp
-    ( input d, en, output reg q );
+    ( input d, clk, en, output reg q );
 	always @*
 		if ( en )
 			q <= d;
 endmodule
 
 module latchn
-    ( input d, en, output reg q );
+    ( input d, clk, en, output reg q );
 	always @*
 		if ( !en )
 			q <= d;
 endmodule
 
 module latchsr
-    ( input d, en, clr, pre, output reg q );
+    ( input d, clk, en, clr, pre, output reg q );
 	always @*
 		if ( clr )
 			q <= 1'b0;
diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys
index bd1dffd21..9ab562bcf 100644
--- a/tests/xilinx/latches.ys
+++ b/tests/xilinx/latches.ys
@@ -1,13 +1,20 @@
 read_verilog latches.v
+design -save read
 
 proc
+async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock
 flatten
-equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+synth_xilinx
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+
+design -load read
 
-design -load preopt
 synth_xilinx
-cd top
+#cd top
+
 select -assert-count 1 t:LUT1
 select -assert-count 2 t:LUT3
-select -assert-count 3 t:LDCE
-select -assert-none t:LUT1 t:LUT3 t:LDCE %% t:* %D
+select -assert-count 3 t:$_DLATCH_P_
+#ERROR: Assertion failed: selection is not empty: t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D
+#select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D
diff --git a/tests/xilinx/logic.v b/tests/xilinx/logic.v
new file mode 100644
index 000000000..e5343cae0
--- /dev/null
+++ b/tests/xilinx/logic.v
@@ -0,0 +1,18 @@
+module top
+(
+ input [0:7] in,
+ output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
+ );
+
+   assign     B1 =  in[0] & in[1];
+   assign     B2 =  in[0] | in[1];
+   assign     B3 =  in[0] ~& in[1];
+   assign     B4 =  in[0] ~| in[1];
+   assign     B5 =  in[0] ^ in[1];
+   assign     B6 =  in[0] ~^ in[1];
+   assign     B7 =  ~in[0];
+   assign     B8 =  in[0];
+   assign     B9 =  in[0:1] && in [2:3];
+   assign     B10 =  in[0:1] || in [2:3];
+
+endmodule
diff --git a/tests/xilinx/logic.ys b/tests/xilinx/logic.ys
new file mode 100644
index 000000000..e138ae6a3
--- /dev/null
+++ b/tests/xilinx/logic.ys
@@ -0,0 +1,10 @@
+read_verilog logic.v
+hierarchy -top top
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:LUT1
+select -assert-count 6 t:LUT2
+select -assert-count 2 t:LUT4
+select -assert-none t:LUT1 t:LUT2 t:LUT4 %% t:* %D
diff --git a/tests/xilinx/memory.v b/tests/xilinx/memory.v
new file mode 100644
index 000000000..cb7753f7b
--- /dev/null
+++ b/tests/xilinx/memory.v
@@ -0,0 +1,21 @@
+module top
+(
+	input [7:0] data_a,
+	input [6:1] addr_a,
+	input we_a, clk,
+	output reg [7:0] q_a
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	// Port A
+	always @ (posedge clk)
+	begin
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		q_a <= ram[addr_a];
+	end
+endmodule
diff --git a/tests/xilinx/memory.ys b/tests/xilinx/memory.ys
new file mode 100644
index 000000000..5402513a2
--- /dev/null
+++ b/tests/xilinx/memory.ys
@@ -0,0 +1,17 @@
+read_verilog memory.v
+hierarchy -top top
+proc
+memory -nomap
+equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
+memory
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
+
+design -load postopt
+cd top
+select -assert-count 1 t:BUFG
+select -assert-count 8 t:FDRE
+select -assert-count 8 t:RAM64X1D
+select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D
diff --git a/tests/xilinx/mul.v b/tests/xilinx/mul.v
new file mode 100644
index 000000000..d5b48b1d7
--- /dev/null
+++ b/tests/xilinx/mul.v
@@ -0,0 +1,11 @@
+module top
+(
+ input [5:0] x,
+ input [5:0] y,
+
+ output [11:0] A,
+ );
+
+assign A =  x * y;
+
+endmodule
diff --git a/tests/xilinx/mul.ys b/tests/xilinx/mul.ys
new file mode 100644
index 000000000..ec30c9c2c
--- /dev/null
+++ b/tests/xilinx/mul.ys
@@ -0,0 +1,15 @@
+read_verilog mul.v
+hierarchy -top top
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 12 t:LUT2
+select -assert-count 1  t:LUT3
+select -assert-count 6  t:LUT4
+select -assert-count 1  t:LUT5
+select -assert-count 33 t:LUT6
+select -assert-count 11 t:MUXCY
+select -assert-count 1  t:MUXF7
+select -assert-count 12 t:XORCY
+select -assert-none t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:XORCY %% t:* %D
diff --git a/tests/xilinx/mux.v b/tests/xilinx/mux.v
new file mode 100644
index 000000000..0814b733e
--- /dev/null
+++ b/tests/xilinx/mux.v
@@ -0,0 +1,100 @@
+module mux2 (S,A,B,Y);
+    input S;
+    input A,B;
+    output reg Y;
+
+    always @(*)
+		Y = (S)? B : A;
+endmodule
+
+module mux4 ( S, D, Y );
+
+input[1:0] S;
+input[3:0] D;
+output Y;
+
+reg Y;
+wire[1:0] S;
+wire[3:0] D;
+
+always @*
+begin
+    case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+   endcase
+end
+
+endmodule
+
+module mux8 ( S, D, Y );
+
+input[2:0] S;
+input[7:0] D;
+output Y;
+
+reg Y;
+wire[2:0] S;
+wire[7:0] D;
+
+always @*
+begin
+   case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+       4 : Y = D[4];
+       5 : Y = D[5];
+       6 : Y = D[6];
+       7 : Y = D[7];
+   endcase
+end
+
+endmodule
+
+module mux16 (D, S, Y);
+ 	input  [15:0] D;
+ 	input  [3:0] S;
+ 	output Y;
+
+assign Y = D[S];
+
+endmodule
+
+
+module top (
+input [3:0] S,
+input [15:0] D,
+output M2,M4,M8,M16
+);
+
+mux2 u_mux2 (
+        .S (S[0]),
+        .A (D[0]),
+        .B (D[1]),
+        .Y (M2)
+    );
+
+
+mux4 u_mux4 (
+        .S (S[1:0]),
+        .D (D[3:0]),
+        .Y (M4)
+    );
+
+mux8 u_mux8 (
+        .S (S[2:0]),
+        .D (D[7:0]),
+        .Y (M8)
+    );
+
+mux16 u_mux16 (
+        .S (S[3:0]),
+        .D (D[15:0]),
+        .Y (M16)
+    );
+
+endmodule
diff --git a/tests/xilinx/mux.ys b/tests/xilinx/mux.ys
new file mode 100644
index 000000000..6ecee58f5
--- /dev/null
+++ b/tests/xilinx/mux.ys
@@ -0,0 +1,10 @@
+read_verilog mux.v
+proc
+flatten
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 2  t:LUT3
+select -assert-count 5  t:LUT6
+select -assert-none t:LUT3 t:LUT6 %% t:* %D
diff --git a/tests/xilinx/run-test.sh b/tests/xilinx/run-test.sh
index ea56b70f0..2c72ca3a9 100755
--- a/tests/xilinx/run-test.sh
+++ b/tests/xilinx/run-test.sh
@@ -6,7 +6,7 @@ for x in *.ys; do
 	echo "all:: run-$x"
 	echo "run-$x:"
 	echo "	@echo 'Running $x..'"
-	echo "	@../../yosys -ql ${x%.ys}.log $x"
+	echo "	@../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'"
 done
 for s in *.sh; do
 	if [ "$s" != "run-test.sh" ]; then
diff --git a/tests/xilinx/shifter.v b/tests/xilinx/shifter.v
new file mode 100644
index 000000000..c55632552
--- /dev/null
+++ b/tests/xilinx/shifter.v
@@ -0,0 +1,22 @@
+module top    (
+out,
+clk,
+in
+);
+    output [7:0] out;
+    input signed clk, in;
+    reg signed [7:0] out = 0;
+
+    always @(posedge clk)
+	begin
+`ifndef BUG
+		out    <= out >> 1;
+		out[7] <= in;
+`else
+
+		out    <= out << 1;
+		out[7] <= in;
+`endif
+	end
+
+endmodule
diff --git a/tests/xilinx/shifter.ys b/tests/xilinx/shifter.ys
new file mode 100644
index 000000000..84e16f41e
--- /dev/null
+++ b/tests/xilinx/shifter.ys
@@ -0,0 +1,11 @@
+read_verilog shifter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:BUFG
+select -assert-count 8 t:FDRE
+select -assert-none t:BUFG t:FDRE %% t:* %D
diff --git a/tests/xilinx/tribuf.v b/tests/xilinx/tribuf.v
new file mode 100644
index 000000000..3fa6eb6c6
--- /dev/null
+++ b/tests/xilinx/tribuf.v
@@ -0,0 +1,29 @@
+module tristate (en, i, o);
+    input en;
+    input i;
+    output reg o;
+`ifndef BUG 
+    
+    always @(en or i)
+		o <= (en)? i : 1'bZ;
+`else
+	
+    always @(en or i)
+		o <= (en)? ~i : 1'bZ;
+`endif
+endmodule
+
+
+module top (
+input en,
+input a,
+output b
+);
+
+tristate u_tri (
+        .en (en ),
+        .i (a ),
+        .o (b )
+    );
+
+endmodule
diff --git a/tests/xilinx/tribuf.ys b/tests/xilinx/tribuf.ys
new file mode 100644
index 000000000..fc7ed37ef
--- /dev/null
+++ b/tests/xilinx/tribuf.ys
@@ -0,0 +1,11 @@
+read_verilog tribuf.v
+hierarchy -top top
+proc
+tribuf
+flatten
+synth
+equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:$_TBUF_
+select -assert-none t:$_TBUF_ %% t:* %D
-- 
cgit v1.2.3


From 489444bcba0d54a45605872eb466792f07357f84 Mon Sep 17 00:00:00 2001
From: SergeyDegtyar <sndegtyar@gmail.com>
Date: Tue, 10 Sep 2019 08:36:59 +0300
Subject: Fix latches.ys test

---
 tests/xilinx/latches.ys | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

(limited to 'tests/xilinx')

diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys
index 9ab562bcf..042ee2d4f 100644
--- a/tests/xilinx/latches.ys
+++ b/tests/xilinx/latches.ys
@@ -11,10 +11,9 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 design -load read
 
 synth_xilinx
-#cd top
-
+flatten
+cd top
 select -assert-count 1 t:LUT1
 select -assert-count 2 t:LUT3
 select -assert-count 3 t:$_DLATCH_P_
-#ERROR: Assertion failed: selection is not empty: t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D
-#select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D
+select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D
-- 
cgit v1.2.3


From 7bc8f0c2e234641b8af7f8dd991ea65bd9a6ef1a Mon Sep 17 00:00:00 2001
From: SergeyDegtyar <sndegtyar@gmail.com>
Date: Wed, 11 Sep 2019 17:01:19 +0300
Subject: Add comment with expected behavior for latches,tribuf tests;Update
 adffs test

---
 tests/xilinx/adffs.v    | 18 +++++++-----------
 tests/xilinx/adffs.ys   |  5 ++---
 tests/xilinx/latches.ys |  1 +
 tests/xilinx/tribuf.ys  |  1 +
 4 files changed, 11 insertions(+), 14 deletions(-)

(limited to 'tests/xilinx')

diff --git a/tests/xilinx/adffs.v b/tests/xilinx/adffs.v
index 93c8bf52c..05e68caf7 100644
--- a/tests/xilinx/adffs.v
+++ b/tests/xilinx/adffs.v
@@ -22,30 +22,26 @@ module adffn
             q <= d;
 endmodule
 
-module dffsr
+module dffs
     ( input d, clk, pre, clr, output reg q );
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge pre, posedge clr )
-		if ( clr )
-			q <= 1'b0;
-		else if ( pre )
+	always @( posedge clk )
+		if ( pre )
 			q <= 1'b1;
 		else
             q <= d;
 endmodule
 
-module ndffnsnr
+module ndffnr
     ( input d, clk, pre, clr, output reg q );
     initial begin
       q = 0;
     end
-	always @( negedge clk, negedge pre, negedge clr )
+	always @( negedge clk )
 		if ( !clr )
 			q <= 1'b0;
-		else if ( !pre )
-			q <= 1'b1;
 		else
             q <= d;
 endmodule
@@ -58,7 +54,7 @@ input a,
 output b,b1,b2,b3
 );
 
-dffsr u_dffsr (
+dffs u_dffs (
         .clk (clk ),
         .clr (clr),
         .pre (pre),
@@ -66,7 +62,7 @@ dffsr u_dffsr (
         .q (b )
     );
 
-ndffnsnr u_ndffnsnr (
+ndffnr u_ndffnr (
         .clk (clk ),
         .clr (clr),
         .pre (pre),
diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys
index 96d8e176f..38c82a36f 100644
--- a/tests/xilinx/adffs.ys
+++ b/tests/xilinx/adffs.ys
@@ -9,6 +9,5 @@ cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
 select -assert-count 3 t:FDRE
 select -assert-count 1 t:FDRE_1
-select -assert-count 4 t:LUT2
-select -assert-count 4 t:LUT3
-select -assert-none t:BUFG t:FDRE t:FDRE_1 t:LUT2 t:LUT3 %% t:* %D
+select -assert-count 5 t:LUT2
+select -assert-none t:BUFG t:FDRE t:FDRE_1 t:LUT2 %% t:* %D
diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys
index 042ee2d4f..1f643cb4e 100644
--- a/tests/xilinx/latches.ys
+++ b/tests/xilinx/latches.ys
@@ -15,5 +15,6 @@ flatten
 cd top
 select -assert-count 1 t:LUT1
 select -assert-count 2 t:LUT3
+#Xilinx Vivado synthesizes LDCE cell for this case. Need support it.
 select -assert-count 3 t:$_DLATCH_P_
 select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D
diff --git a/tests/xilinx/tribuf.ys b/tests/xilinx/tribuf.ys
index fc7ed37ef..76b00647d 100644
--- a/tests/xilinx/tribuf.ys
+++ b/tests/xilinx/tribuf.ys
@@ -7,5 +7,6 @@ synth
 equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
+#Xilinx Vivado synthesizes OBUFT cell for this case. Need support it.
 select -assert-count 1 t:$_TBUF_
 select -assert-none t:$_TBUF_ %% t:* %D
-- 
cgit v1.2.3


From df7fe40529f7e0a26626ac1b0ed12acf66bb40d3 Mon Sep 17 00:00:00 2001
From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com>
Date: Wed, 11 Sep 2019 20:34:22 +0300
Subject: Fix div_mod test

---
 tests/xilinx/div_mod.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests/xilinx')

diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys
index cc00b1a27..52e536a7f 100644
--- a/tests/xilinx/div_mod.ys
+++ b/tests/xilinx/div_mod.ys
@@ -6,7 +6,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd top # Constrain all select calls below inside the top module
 
 select -assert-count 12 t:LUT1
-select -assert-count 21 t:LUT2
+select -assert-count 23 t:LUT2
 select -assert-count 13 t:LUT4
 select -assert-count 6  t:LUT5
 select -assert-count 80 t:LUT6
-- 
cgit v1.2.3


From 205f52ffe53778daf9fc1bcdd9bee4b53a6e2a60 Mon Sep 17 00:00:00 2001
From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com>
Date: Wed, 11 Sep 2019 21:28:40 +0300
Subject: Fix div_mod test

---
 tests/xilinx/div_mod.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests/xilinx')

diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys
index 52e536a7f..e1c4d6912 100644
--- a/tests/xilinx/div_mod.ys
+++ b/tests/xilinx/div_mod.ys
@@ -7,7 +7,7 @@ cd top # Constrain all select calls below inside the top module
 
 select -assert-count 12 t:LUT1
 select -assert-count 23 t:LUT2
-select -assert-count 13 t:LUT4
+select -assert-count 12 t:LUT4
 select -assert-count 6  t:LUT5
 select -assert-count 80 t:LUT6
 select -assert-count 65 t:MUXCY
-- 
cgit v1.2.3


From c340d54657688542c5f3a8dabe3f68563dcc8d1c Mon Sep 17 00:00:00 2001
From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com>
Date: Thu, 12 Sep 2019 06:24:18 +0300
Subject: Fix div_mod test

---
 tests/xilinx/div_mod.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests/xilinx')

diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys
index e1c4d6912..7db336d00 100644
--- a/tests/xilinx/div_mod.ys
+++ b/tests/xilinx/div_mod.ys
@@ -8,7 +8,7 @@ cd top # Constrain all select calls below inside the top module
 select -assert-count 12 t:LUT1
 select -assert-count 23 t:LUT2
 select -assert-count 12 t:LUT4
-select -assert-count 6  t:LUT5
+select -assert-count 9  t:LUT5
 select -assert-count 80 t:LUT6
 select -assert-count 65 t:MUXCY
 select -assert-count 36 t:MUXF7
-- 
cgit v1.2.3


From df6d0b95da89a4a7bd558dab0c112f5c7a989561 Mon Sep 17 00:00:00 2001
From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com>
Date: Thu, 12 Sep 2019 07:13:49 +0300
Subject: Fix div_mod test

---
 tests/xilinx/div_mod.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests/xilinx')

diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys
index 7db336d00..c5855f1dd 100644
--- a/tests/xilinx/div_mod.ys
+++ b/tests/xilinx/div_mod.ys
@@ -9,7 +9,7 @@ select -assert-count 12 t:LUT1
 select -assert-count 23 t:LUT2
 select -assert-count 12 t:LUT4
 select -assert-count 9  t:LUT5
-select -assert-count 80 t:LUT6
+select -assert-count 84 t:LUT6
 select -assert-count 65 t:MUXCY
 select -assert-count 36 t:MUXF7
 select -assert-count 9  t:MUXF8
-- 
cgit v1.2.3


From 68f9239c5758e4f48dc290871cf108f85d5f5387 Mon Sep 17 00:00:00 2001
From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com>
Date: Thu, 12 Sep 2019 13:58:49 +0300
Subject: Fix div_mod test

---
 tests/xilinx/div_mod.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests/xilinx')

diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys
index c5855f1dd..6a4c1e971 100644
--- a/tests/xilinx/div_mod.ys
+++ b/tests/xilinx/div_mod.ys
@@ -11,7 +11,7 @@ select -assert-count 12 t:LUT4
 select -assert-count 9  t:LUT5
 select -assert-count 84 t:LUT6
 select -assert-count 65 t:MUXCY
-select -assert-count 36 t:MUXF7
+select -assert-count 39 t:MUXF7
 select -assert-count 9  t:MUXF8
 select -assert-count 28 t:XORCY
 select -assert-none t:LUT1 t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
-- 
cgit v1.2.3


From bb70eb977dc29dbfe8cfb9af847046f387bd54b2 Mon Sep 17 00:00:00 2001
From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com>
Date: Thu, 12 Sep 2019 14:54:01 +0300
Subject: Fix div_mod test

---
 tests/xilinx/div_mod.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests/xilinx')

diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys
index 6a4c1e971..4518db8bf 100644
--- a/tests/xilinx/div_mod.ys
+++ b/tests/xilinx/div_mod.ys
@@ -12,6 +12,6 @@ select -assert-count 9  t:LUT5
 select -assert-count 84 t:LUT6
 select -assert-count 65 t:MUXCY
 select -assert-count 39 t:MUXF7
-select -assert-count 9  t:MUXF8
+select -assert-count 15 t:MUXF8
 select -assert-count 28 t:XORCY
 select -assert-none t:LUT1 t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
-- 
cgit v1.2.3


From 305672170bcd6346bebbb01c843225fe0392a37d Mon Sep 17 00:00:00 2001
From: SergeyDegtyar <sndegtyar@gmail.com>
Date: Tue, 17 Sep 2019 11:53:49 +0300
Subject: adffs test update (equiv_opt -multiclock)

---
 tests/xilinx/adffs.ys | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

(limited to 'tests/xilinx')

diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys
index 38c82a36f..961e08ae9 100644
--- a/tests/xilinx/adffs.ys
+++ b/tests/xilinx/adffs.ys
@@ -1,13 +1,14 @@
 read_verilog adffs.v
 proc
-async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock
 flatten
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -multiclock -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
 select -assert-count 1 t:BUFG
-select -assert-count 3 t:FDRE
+select -assert-count 2 t:FDCE
+select -assert-count 1 t:FDRE
 select -assert-count 1 t:FDRE_1
-select -assert-count 5 t:LUT2
-select -assert-none t:BUFG t:FDRE t:FDRE_1 t:LUT2 %% t:* %D
+select -assert-count 1 t:LUT1
+select -assert-count 2 t:LUT2
+select -assert-none t:BUFG t:FDCE t:FDRE t:FDRE_1 t:LUT1 t:LUT2 %% t:* %D
-- 
cgit v1.2.3


From eded90b6b42117ba427469a6100c74e708c4f142 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Sep 2019 14:16:45 -0700
Subject: Move $x to end as 7f0eec8

---
 tests/xilinx/run-test.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests/xilinx')

diff --git a/tests/xilinx/run-test.sh b/tests/xilinx/run-test.sh
index 2c72ca3a9..46716f9a0 100755
--- a/tests/xilinx/run-test.sh
+++ b/tests/xilinx/run-test.sh
@@ -6,7 +6,7 @@ for x in *.ys; do
 	echo "all:: run-$x"
 	echo "run-$x:"
 	echo "	@echo 'Running $x..'"
-	echo "	@../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'"
+	echo "	@../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
 done
 for s in *.sh; do
 	if [ "$s" != "run-test.sh" ]; then
-- 
cgit v1.2.3


From a12801843bb400bba8f2f8ce99a3f524ac05b7e8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Sep 2019 14:17:59 -0700
Subject: Add comment for lack of tristate logic pointing to #1225

---
 tests/xilinx/tribuf.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests/xilinx')

diff --git a/tests/xilinx/tribuf.ys b/tests/xilinx/tribuf.ys
index 76b00647d..696be2620 100644
--- a/tests/xilinx/tribuf.ys
+++ b/tests/xilinx/tribuf.ys
@@ -7,6 +7,6 @@ synth
 equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
-#Xilinx Vivado synthesizes OBUFT cell for this case. Need support it.
+# TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225
 select -assert-count 1 t:$_TBUF_
 select -assert-none t:$_TBUF_ %% t:* %D
-- 
cgit v1.2.3


From 08bd1816e39d2abfbe36ce0b58c0d4506db303e4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Sep 2019 14:20:47 -0700
Subject: Update area for div_mod

---
 tests/xilinx/div_mod.ys | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

(limited to 'tests/xilinx')

diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys
index 4518db8bf..da7e60a9a 100644
--- a/tests/xilinx/div_mod.ys
+++ b/tests/xilinx/div_mod.ys
@@ -6,12 +6,12 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd top # Constrain all select calls below inside the top module
 
 select -assert-count 12 t:LUT1
-select -assert-count 23 t:LUT2
-select -assert-count 12 t:LUT4
-select -assert-count 9  t:LUT5
-select -assert-count 84 t:LUT6
+select -assert-count 19 t:LUT2
+select -assert-count 13 t:LUT4
+select -assert-count 6  t:LUT5
+select -assert-count 82 t:LUT6
 select -assert-count 65 t:MUXCY
-select -assert-count 39 t:MUXF7
-select -assert-count 15 t:MUXF8
+select -assert-count 37 t:MUXF7
+select -assert-count 11 t:MUXF8
 select -assert-count 28 t:XORCY
 select -assert-none t:LUT1 t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
-- 
cgit v1.2.3


From 5b7bc3ab85d31920883995636d26dc5b971ca24d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Sep 2019 14:38:06 -0700
Subject: Update mul test to DSP48E1

---
 tests/xilinx/mul.ys | 11 ++---------
 1 file changed, 2 insertions(+), 9 deletions(-)

(limited to 'tests/xilinx')

diff --git a/tests/xilinx/mul.ys b/tests/xilinx/mul.ys
index ec30c9c2c..f5306e848 100644
--- a/tests/xilinx/mul.ys
+++ b/tests/xilinx/mul.ys
@@ -4,12 +4,5 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
-select -assert-count 12 t:LUT2
-select -assert-count 1  t:LUT3
-select -assert-count 6  t:LUT4
-select -assert-count 1  t:LUT5
-select -assert-count 33 t:LUT6
-select -assert-count 11 t:MUXCY
-select -assert-count 1  t:MUXF7
-select -assert-count 12 t:XORCY
-select -assert-none t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:XORCY %% t:* %D
+select -assert-count 1 t:DSP48E1
+select -assert-none t:DSP48E1 %% t:* %D
-- 
cgit v1.2.3


From 8422ad3e3a5db583f59906f8a5d81587dd777f6d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Sep 2019 14:56:19 -0700
Subject: Use built-in async2sync call as per #1417

---
 tests/xilinx/latches.ys | 4 ----
 1 file changed, 4 deletions(-)

(limited to 'tests/xilinx')

diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys
index 1f643cb4e..795ac9074 100644
--- a/tests/xilinx/latches.ys
+++ b/tests/xilinx/latches.ys
@@ -4,11 +4,7 @@ design -save read
 proc
 async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock
 flatten
-synth_xilinx
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-
-design -load read
 
 synth_xilinx
 flatten
-- 
cgit v1.2.3


From 3b4408432073ec4d9a2b8995b8e08a5bf6175f39 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Sep 2019 19:57:26 -0700
Subject: Add -assert

---
 tests/xilinx/counter.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests/xilinx')

diff --git a/tests/xilinx/counter.ys b/tests/xilinx/counter.ys
index b602b74d7..3bb3a8eb0 100644
--- a/tests/xilinx/counter.ys
+++ b/tests/xilinx/counter.ys
@@ -2,7 +2,7 @@ read_verilog counter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
-- 
cgit v1.2.3


From a7fbc8c3fe1e2ad867ffc3456943644e70ab2575 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 08:19:26 +0200
Subject: Test per flip-flop type

---
 tests/xilinx/adffs.v  | 40 ----------------------------------------
 tests/xilinx/adffs.ys | 44 +++++++++++++++++++++++++++++++++++++-------
 2 files changed, 37 insertions(+), 47 deletions(-)

(limited to 'tests/xilinx')

diff --git a/tests/xilinx/adffs.v b/tests/xilinx/adffs.v
index 05e68caf7..223b52d21 100644
--- a/tests/xilinx/adffs.v
+++ b/tests/xilinx/adffs.v
@@ -45,43 +45,3 @@ module ndffnr
 		else
             q <= d;
 endmodule
-
-module top (
-input clk,
-input clr,
-input pre,
-input a,
-output b,b1,b2,b3
-);
-
-dffs u_dffs (
-        .clk (clk ),
-        .clr (clr),
-        .pre (pre),
-        .d (a ),
-        .q (b )
-    );
-
-ndffnr u_ndffnr (
-        .clk (clk ),
-        .clr (clr),
-        .pre (pre),
-        .d (a ),
-        .q (b1 )
-    );
-
-adff u_adff (
-        .clk (clk ),
-        .clr (clr),
-        .d (a ),
-        .q (b2 )
-    );
-
-adffn u_adffn (
-        .clk (clk ),
-        .clr (clr),
-        .d (a ),
-        .q (b3 )
-    );
-
-endmodule
diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys
index 961e08ae9..7edab67c7 100644
--- a/tests/xilinx/adffs.ys
+++ b/tests/xilinx/adffs.ys
@@ -1,14 +1,44 @@
 read_verilog adffs.v
+design -save read
+
 proc
-flatten
-equiv_opt -multiclock -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+hierarchy -top adff
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd adff # Constrain all select calls below inside the top module
+select -assert-count 1 t:BUFG
+select -assert-count 1 t:FDCE
+select -assert-none t:BUFG t:FDCE %% t:* %D
+
+design -load read
+proc
+hierarchy -top adffn
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adffn # Constrain all select calls below inside the top module
+select -assert-count 1 t:BUFG
+select -assert-count 1 t:FDCE
+select -assert-count 1 t:LUT1
+select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D
 
+design -load read
+proc
+hierarchy -top dffs
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffs # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
-select -assert-count 2 t:FDCE
 select -assert-count 1 t:FDRE
+select -assert-count 1 t:LUT2
+select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D
+
+design -load read
+proc
+hierarchy -top ndffnr
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd ndffnr # Constrain all select calls below inside the top module
+select -assert-count 1 t:BUFG
 select -assert-count 1 t:FDRE_1
-select -assert-count 1 t:LUT1
-select -assert-count 2 t:LUT2
-select -assert-none t:BUFG t:FDCE t:FDRE t:FDRE_1 t:LUT1 t:LUT2 %% t:* %D
+select -assert-count 1 t:LUT2
+select -assert-none t:BUFG t:FDRE_1 t:LUT2 %% t:* %D
\ No newline at end of file
-- 
cgit v1.2.3


From d37cd267a56295737e95f5bc5e6f446c27605639 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 08:24:37 +0200
Subject: Removed alu and div_mod test as agreed, ignore generated files

---
 tests/xilinx/.gitignore |  1 +
 tests/xilinx/alu.v      | 19 -------------------
 tests/xilinx/alu.ys     | 21 ---------------------
 tests/xilinx/div_mod.v  | 13 -------------
 tests/xilinx/div_mod.ys | 17 -----------------
 5 files changed, 1 insertion(+), 70 deletions(-)
 delete mode 100644 tests/xilinx/alu.v
 delete mode 100644 tests/xilinx/alu.ys
 delete mode 100644 tests/xilinx/div_mod.v
 delete mode 100644 tests/xilinx/div_mod.ys

(limited to 'tests/xilinx')

diff --git a/tests/xilinx/.gitignore b/tests/xilinx/.gitignore
index 54733fb71..89879f209 100644
--- a/tests/xilinx/.gitignore
+++ b/tests/xilinx/.gitignore
@@ -2,3 +2,4 @@
 /*.out
 /run-test.mk
 /*_uut.v
+/test_macc
\ No newline at end of file
diff --git a/tests/xilinx/alu.v b/tests/xilinx/alu.v
deleted file mode 100644
index f82cc2e21..000000000
--- a/tests/xilinx/alu.v
+++ /dev/null
@@ -1,19 +0,0 @@
-module top (
-	input clock,
-	input [31:0] dinA, dinB,
-	input [2:0] opcode,
-	output reg [31:0] dout
-);
-	always @(posedge clock) begin
-		case (opcode)
-		0: dout <= dinA + dinB;
-		1: dout <= dinA - dinB;
-		2: dout <= dinA >> dinB;
-		3: dout <= $signed(dinA) >>> dinB;
-		4: dout <= dinA << dinB;
-		5: dout <= dinA & dinB;
-		6: dout <= dinA | dinB;
-		7: dout <= dinA ^ dinB;
-		endcase
-	end
-endmodule
diff --git a/tests/xilinx/alu.ys b/tests/xilinx/alu.ys
deleted file mode 100644
index f85f03928..000000000
--- a/tests/xilinx/alu.ys
+++ /dev/null
@@ -1,21 +0,0 @@
-read_verilog alu.v
-hierarchy -top top
-proc
-flatten
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-
-
-select -assert-count 1 t:BUFG
-select -assert-count 32 t:LUT1
-select -assert-count 142 t:LUT2
-select -assert-count 55  t:LUT3
-select -assert-count 70  t:LUT4
-select -assert-count 46  t:LUT5
-select -assert-count 625 t:LUT6
-select -assert-count 62 t:MUXCY
-select -assert-count 265  t:MUXF7
-select -assert-count 79  t:MUXF8
-select -assert-count 64 t:XORCY
-select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
diff --git a/tests/xilinx/div_mod.v b/tests/xilinx/div_mod.v
deleted file mode 100644
index 64a36707d..000000000
--- a/tests/xilinx/div_mod.v
+++ /dev/null
@@ -1,13 +0,0 @@
-module top
-(
- input [3:0] x,
- input [3:0] y,
-
- output [3:0] A,
- output [3:0] B
- );
-
-assign A =  x % y;
-assign B =  x / y;
-
-endmodule
diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys
deleted file mode 100644
index da7e60a9a..000000000
--- a/tests/xilinx/div_mod.ys
+++ /dev/null
@@ -1,17 +0,0 @@
-read_verilog div_mod.v
-hierarchy -top top
-flatten
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-
-select -assert-count 12 t:LUT1
-select -assert-count 19 t:LUT2
-select -assert-count 13 t:LUT4
-select -assert-count 6  t:LUT5
-select -assert-count 82 t:LUT6
-select -assert-count 65 t:MUXCY
-select -assert-count 37 t:MUXF7
-select -assert-count 11 t:MUXF8
-select -assert-count 28 t:XORCY
-select -assert-none t:LUT1 t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D
-- 
cgit v1.2.3


From 53bc499a907cc3bfbeb91866d8839286ae0dfdf1 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 08:27:49 +0200
Subject: Clean verilog code from not used define block

---
 tests/xilinx/shifter.v | 6 ------
 tests/xilinx/tribuf.v  | 6 ------
 2 files changed, 12 deletions(-)

(limited to 'tests/xilinx')

diff --git a/tests/xilinx/shifter.v b/tests/xilinx/shifter.v
index c55632552..04ae49d83 100644
--- a/tests/xilinx/shifter.v
+++ b/tests/xilinx/shifter.v
@@ -9,14 +9,8 @@ in
 
     always @(posedge clk)
 	begin
-`ifndef BUG
 		out    <= out >> 1;
 		out[7] <= in;
-`else
-
-		out    <= out << 1;
-		out[7] <= in;
-`endif
 	end
 
 endmodule
diff --git a/tests/xilinx/tribuf.v b/tests/xilinx/tribuf.v
index 3fa6eb6c6..75149d8ba 100644
--- a/tests/xilinx/tribuf.v
+++ b/tests/xilinx/tribuf.v
@@ -2,15 +2,9 @@ module tristate (en, i, o);
     input en;
     input i;
     output reg o;
-`ifndef BUG 
     
     always @(en or i)
 		o <= (en)? i : 1'bZ;
-`else
-	
-    always @(en or i)
-		o <= (en)? ~i : 1'bZ;
-`endif
 endmodule
 
 
-- 
cgit v1.2.3


From fba6229718a45188514e016eec8678f1facb82a4 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 09:19:17 +0200
Subject: Fix formatting

---
 tests/xilinx/adffs.ys | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

(limited to 'tests/xilinx')

diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys
index 7edab67c7..2d23749ac 100644
--- a/tests/xilinx/adffs.ys
+++ b/tests/xilinx/adffs.ys
@@ -8,8 +8,10 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd adff # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
 select -assert-count 1 t:FDCE
+
 select -assert-none t:BUFG t:FDCE %% t:* %D
 
+
 design -load read
 proc
 hierarchy -top adffn
@@ -19,8 +21,10 @@ cd adffn # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
 select -assert-count 1 t:FDCE
 select -assert-count 1 t:LUT1
+
 select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D
 
+
 design -load read
 proc
 hierarchy -top dffs
@@ -30,8 +34,10 @@ cd dffs # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
 select -assert-count 1 t:FDRE
 select -assert-count 1 t:LUT2
+
 select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D
 
+
 design -load read
 proc
 hierarchy -top ndffnr
@@ -41,4 +47,5 @@ cd ndffnr # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
 select -assert-count 1 t:FDRE_1
 select -assert-count 1 t:LUT2
-select -assert-none t:BUFG t:FDRE_1 t:LUT2 %% t:* %D
\ No newline at end of file
+
+select -assert-none t:BUFG t:FDRE_1 t:LUT2 %% t:* %D
-- 
cgit v1.2.3


From 487b38b124cbb388bd680cb54cb43c58829ca1d3 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 09:24:22 +0200
Subject: Split latches into separete tests

---
 tests/xilinx/latches.v  | 34 ----------------------------------
 tests/xilinx/latches.ys | 35 +++++++++++++++++++++++++++--------
 2 files changed, 27 insertions(+), 42 deletions(-)

(limited to 'tests/xilinx')

diff --git a/tests/xilinx/latches.v b/tests/xilinx/latches.v
index 9dc43e4c2..adb5d5319 100644
--- a/tests/xilinx/latches.v
+++ b/tests/xilinx/latches.v
@@ -22,37 +22,3 @@ module latchsr
 		else if ( en )
 			q <= d;
 endmodule
-
-
-module top (
-input clk,
-input clr,
-input pre,
-input a,
-output b,b1,b2
-);
-
-
-latchp u_latchp (
-        .en (clk ),
-        .d (a ),
-        .q (b )
-    );
-
-
-latchn u_latchn (
-        .en (clk ),
-        .d (a ),
-        .q (b1 )
-    );
-
-
-latchsr u_latchsr (
-        .en (clk ),
-        .clr (clr),
-        .pre (pre),
-        .d (a ),
-        .q (b2 )
-    );
-
-endmodule
diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys
index 795ac9074..68ca42b10 100644
--- a/tests/xilinx/latches.ys
+++ b/tests/xilinx/latches.ys
@@ -2,15 +2,34 @@ read_verilog latches.v
 design -save read
 
 proc
-async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock
-flatten
+hierarchy -top latchp
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd latchp # Constrain all select calls below inside the top module
+select -assert-count 1 t:LDCE
 
-synth_xilinx
-flatten
-cd top
+select -assert-none t:LDCE %% t:* %D
+
+
+design -load read
+proc
+hierarchy -top latchn
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd latchn # Constrain all select calls below inside the top module
+select -assert-count 1 t:LDCE
 select -assert-count 1 t:LUT1
+
+select -assert-none t:LDCE t:LUT1 %% t:* %D
+
+
+design -load read
+proc
+hierarchy -top latchsr
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd latchsr # Constrain all select calls below inside the top module
+select -assert-count 1 t:LDCE
 select -assert-count 2 t:LUT3
-#Xilinx Vivado synthesizes LDCE cell for this case. Need support it.
-select -assert-count 3 t:$_DLATCH_P_
-select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D
+
+select -assert-none t:LDCE t:LUT3 %% t:* %D
-- 
cgit v1.2.3


From 36af10280136f0fda7b743075ac52e48576abf26 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 09:28:18 +0200
Subject: Test dffs separetely

---
 tests/xilinx/dffs.v  | 22 ----------------------
 tests/xilinx/dffs.ys | 23 +++++++++++++++++++----
 2 files changed, 19 insertions(+), 26 deletions(-)

(limited to 'tests/xilinx')

diff --git a/tests/xilinx/dffs.v b/tests/xilinx/dffs.v
index d97840c43..3418787c9 100644
--- a/tests/xilinx/dffs.v
+++ b/tests/xilinx/dffs.v
@@ -13,25 +13,3 @@ module dffe
 		if ( en )
 			q <= d;
 endmodule
-
-module top (
-input clk,
-input en,
-input a,
-output b,b1,
-);
-
-dff u_dff (
-        .clk (clk ),
-        .d (a ),
-        .q (b )
-    );
-
-dffe u_ndffe (
-        .clk (clk ),
-        .en (en),
-        .d (a ),
-        .q (b1 )
-    );
-
-endmodule
diff --git a/tests/xilinx/dffs.ys b/tests/xilinx/dffs.ys
index 6a98994c0..2d48a816c 100644
--- a/tests/xilinx/dffs.ys
+++ b/tests/xilinx/dffs.ys
@@ -1,10 +1,25 @@
 read_verilog dffs.v
-hierarchy -top top
+design -save read
+
 proc
-flatten
+hierarchy -top dff
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd dff # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
-select -assert-count 2 t:FDRE
+select -assert-count 1 t:FDRE
+
 select -assert-none t:BUFG t:FDRE %% t:* %D
+
+
+design -load read
+proc
+hierarchy -top dffe
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffe # Constrain all select calls below inside the top module
+select -assert-count 1 t:BUFG
+select -assert-count 1 t:FDRE
+
+select -assert-none t:BUFG t:FDRE %% t:* %D
+
-- 
cgit v1.2.3


From a198bcdd4ffe6b09787ea5bf2e69528ace375020 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 09:39:22 +0200
Subject: split muxes synth per type

---
 tests/xilinx/mux.v  | 35 -----------------------------------
 tests/xilinx/mux.ys | 43 +++++++++++++++++++++++++++++++++++++++----
 2 files changed, 39 insertions(+), 39 deletions(-)

(limited to 'tests/xilinx')

diff --git a/tests/xilinx/mux.v b/tests/xilinx/mux.v
index 0814b733e..27bc0bf0b 100644
--- a/tests/xilinx/mux.v
+++ b/tests/xilinx/mux.v
@@ -63,38 +63,3 @@ module mux16 (D, S, Y);
 assign Y = D[S];
 
 endmodule
-
-
-module top (
-input [3:0] S,
-input [15:0] D,
-output M2,M4,M8,M16
-);
-
-mux2 u_mux2 (
-        .S (S[0]),
-        .A (D[0]),
-        .B (D[1]),
-        .Y (M2)
-    );
-
-
-mux4 u_mux4 (
-        .S (S[1:0]),
-        .D (D[3:0]),
-        .Y (M4)
-    );
-
-mux8 u_mux8 (
-        .S (S[2:0]),
-        .D (D[7:0]),
-        .Y (M8)
-    );
-
-mux16 u_mux16 (
-        .S (S[3:0]),
-        .D (D[15:0]),
-        .Y (M16)
-    );
-
-endmodule
diff --git a/tests/xilinx/mux.ys b/tests/xilinx/mux.ys
index 6ecee58f5..4cdb12e47 100644
--- a/tests/xilinx/mux.ys
+++ b/tests/xilinx/mux.ys
@@ -1,10 +1,45 @@
 read_verilog mux.v
+design -save read
+
+proc
+hierarchy -top mux2
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux2 # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT3
+
+select -assert-none t:LUT3 %% t:* %D
+
+
+design -load read
 proc
-flatten
+hierarchy -top mux4
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd mux4 # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT6
+
+select -assert-none t:LUT6 %% t:* %D
+
+
+design -load read
+proc
+hierarchy -top mux8
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux8 # Constrain all select calls below inside the top module
+select -assert-count 1 t:LUT3
+select -assert-count 2 t:LUT6
 
-select -assert-count 2  t:LUT3
-select -assert-count 5  t:LUT6
 select -assert-none t:LUT3 t:LUT6 %% t:* %D
+
+
+design -load read
+proc
+hierarchy -top mux16
+equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux16 # Constrain all select calls below inside the top module
+select -assert-count 5 t:LUT6
+
+select -assert-none t:LUT6 %% t:* %D
-- 
cgit v1.2.3


From 1a399c6456b6ca7becf89a5c825b2c8d7b34dc3e Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 09:39:34 +0200
Subject: remove not needed top module

---
 tests/xilinx/tribuf.v  | 15 ---------------
 tests/xilinx/tribuf.ys |  4 ++--
 2 files changed, 2 insertions(+), 17 deletions(-)

(limited to 'tests/xilinx')

diff --git a/tests/xilinx/tribuf.v b/tests/xilinx/tribuf.v
index 75149d8ba..c64468253 100644
--- a/tests/xilinx/tribuf.v
+++ b/tests/xilinx/tribuf.v
@@ -6,18 +6,3 @@ module tristate (en, i, o);
     always @(en or i)
 		o <= (en)? i : 1'bZ;
 endmodule
-
-
-module top (
-input en,
-input a,
-output b
-);
-
-tristate u_tri (
-        .en (en ),
-        .i (a ),
-        .o (b )
-    );
-
-endmodule
diff --git a/tests/xilinx/tribuf.ys b/tests/xilinx/tribuf.ys
index 696be2620..c9cfb8546 100644
--- a/tests/xilinx/tribuf.ys
+++ b/tests/xilinx/tribuf.ys
@@ -1,12 +1,12 @@
 read_verilog tribuf.v
-hierarchy -top top
+hierarchy -top tristate
 proc
 tribuf
 flatten
 synth
 equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd tristate # Constrain all select calls below inside the top module
 # TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225
 select -assert-count 1 t:$_TBUF_
 select -assert-none t:$_TBUF_ %% t:* %D
-- 
cgit v1.2.3


From b2f0d75807c99c74f9860098b74e8300514ba9e5 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 09:41:45 +0200
Subject: remove not needed top module

---
 tests/xilinx/fsm.v  | 18 ------------------
 tests/xilinx/fsm.ys |  4 ++--
 2 files changed, 2 insertions(+), 20 deletions(-)

(limited to 'tests/xilinx')

diff --git a/tests/xilinx/fsm.v b/tests/xilinx/fsm.v
index 0605bd102..368fbaace 100644
--- a/tests/xilinx/fsm.v
+++ b/tests/xilinx/fsm.v
@@ -52,22 +52,4 @@
  endcase
  end
 
- endmodule
-
- module top (
-input clk,
-input rst,
-input a,
-input b,
-output g0,
-output g1
-);
-
-fsm u_fsm ( .clock(clk),
-            .reset(rst),
-            .req_0(a),
-            .req_1(b),
-            .gnt_0(g0),
-            .gnt_1(g1));
-
 endmodule
diff --git a/tests/xilinx/fsm.ys b/tests/xilinx/fsm.ys
index 3b73891c2..a9e94c2c0 100644
--- a/tests/xilinx/fsm.ys
+++ b/tests/xilinx/fsm.ys
@@ -1,10 +1,10 @@
 read_verilog fsm.v
-hierarchy -top top
+hierarchy -top fsm
 proc
 flatten
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd fsm # Constrain all select calls below inside the top module
 
 select -assert-count 1 t:BUFG
 select -assert-count 5 t:FDRE
-- 
cgit v1.2.3


From 980df499abb63e5dfadc29b3326032b55b6dbf18 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 17 Oct 2019 17:24:53 +0200
Subject: Make equivalence work with latest master

---
 tests/xilinx/adffs.ys   | 8 ++++----
 tests/xilinx/counter.ys | 2 +-
 tests/xilinx/latches.ys | 6 +++---
 3 files changed, 8 insertions(+), 8 deletions(-)

(limited to 'tests/xilinx')

diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys
index 2d23749ac..9e8ba44ab 100644
--- a/tests/xilinx/adffs.ys
+++ b/tests/xilinx/adffs.ys
@@ -3,7 +3,7 @@ design -save read
 
 proc
 hierarchy -top adff
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adff # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
@@ -15,7 +15,7 @@ select -assert-none t:BUFG t:FDCE %% t:* %D
 design -load read
 proc
 hierarchy -top adffn
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adffn # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
@@ -28,7 +28,7 @@ select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D
 design -load read
 proc
 hierarchy -top dffs
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffs # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
@@ -41,7 +41,7 @@ select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D
 design -load read
 proc
 hierarchy -top ndffnr
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd ndffnr # Constrain all select calls below inside the top module
 select -assert-count 1 t:BUFG
diff --git a/tests/xilinx/counter.ys b/tests/xilinx/counter.ys
index 3bb3a8eb0..459541656 100644
--- a/tests/xilinx/counter.ys
+++ b/tests/xilinx/counter.ys
@@ -2,7 +2,7 @@ read_verilog counter.v
 hierarchy -top top
 proc
 flatten
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys
index 68ca42b10..52e96834d 100644
--- a/tests/xilinx/latches.ys
+++ b/tests/xilinx/latches.ys
@@ -3,7 +3,7 @@ design -save read
 
 proc
 hierarchy -top latchp
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd latchp # Constrain all select calls below inside the top module
 select -assert-count 1 t:LDCE
@@ -14,7 +14,7 @@ select -assert-none t:LDCE %% t:* %D
 design -load read
 proc
 hierarchy -top latchn
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd latchn # Constrain all select calls below inside the top module
 select -assert-count 1 t:LDCE
@@ -26,7 +26,7 @@ select -assert-none t:LDCE t:LUT1 %% t:* %D
 design -load read
 proc
 hierarchy -top latchsr
-equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
+equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd latchsr # Constrain all select calls below inside the top module
 select -assert-count 1 t:LDCE
-- 
cgit v1.2.3


From e6ad714d20134612521e995c72e4fa06ed791dd3 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 18 Oct 2019 08:06:57 +0200
Subject: hierarchy - proc reorder

---
 tests/xilinx/.gitignore      | 2 +-
 tests/xilinx/add_sub.ys      | 1 +
 tests/xilinx/adffs.ys        | 8 ++++----
 tests/xilinx/dffs.ys         | 4 ++--
 tests/xilinx/latches.ys      | 6 +++---
 tests/xilinx/logic.ys        | 1 +
 tests/xilinx/macc.ys         | 4 ++--
 tests/xilinx/mul.ys          | 1 +
 tests/xilinx/mul_unsigned.ys | 3 ++-
 tests/xilinx/mux.ys          | 8 ++++----
 10 files changed, 21 insertions(+), 17 deletions(-)

(limited to 'tests/xilinx')

diff --git a/tests/xilinx/.gitignore b/tests/xilinx/.gitignore
index 89879f209..c99b79371 100644
--- a/tests/xilinx/.gitignore
+++ b/tests/xilinx/.gitignore
@@ -2,4 +2,4 @@
 /*.out
 /run-test.mk
 /*_uut.v
-/test_macc
\ No newline at end of file
+/test_macc
diff --git a/tests/xilinx/add_sub.ys b/tests/xilinx/add_sub.ys
index 821341f20..f06e7fa01 100644
--- a/tests/xilinx/add_sub.ys
+++ b/tests/xilinx/add_sub.ys
@@ -1,5 +1,6 @@
 read_verilog add_sub.v
 hierarchy -top top
+proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys
index 9e8ba44ab..1923b9802 100644
--- a/tests/xilinx/adffs.ys
+++ b/tests/xilinx/adffs.ys
@@ -1,8 +1,8 @@
 read_verilog adffs.v
 design -save read
 
-proc
 hierarchy -top adff
+proc
 equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adff # Constrain all select calls below inside the top module
@@ -13,8 +13,8 @@ select -assert-none t:BUFG t:FDCE %% t:* %D
 
 
 design -load read
-proc
 hierarchy -top adffn
+proc
 equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd adffn # Constrain all select calls below inside the top module
@@ -26,8 +26,8 @@ select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D
 
 
 design -load read
-proc
 hierarchy -top dffs
+proc
 equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffs # Constrain all select calls below inside the top module
@@ -39,8 +39,8 @@ select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D
 
 
 design -load read
-proc
 hierarchy -top ndffnr
+proc
 equiv_opt -async2sync  -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd ndffnr # Constrain all select calls below inside the top module
diff --git a/tests/xilinx/dffs.ys b/tests/xilinx/dffs.ys
index 2d48a816c..f1716dabb 100644
--- a/tests/xilinx/dffs.ys
+++ b/tests/xilinx/dffs.ys
@@ -1,8 +1,8 @@
 read_verilog dffs.v
 design -save read
 
-proc
 hierarchy -top dff
+proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dff # Constrain all select calls below inside the top module
@@ -13,8 +13,8 @@ select -assert-none t:BUFG t:FDRE %% t:* %D
 
 
 design -load read
-proc
 hierarchy -top dffe
+proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd dffe # Constrain all select calls below inside the top module
diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys
index 52e96834d..3eb550a42 100644
--- a/tests/xilinx/latches.ys
+++ b/tests/xilinx/latches.ys
@@ -1,8 +1,8 @@
 read_verilog latches.v
 design -save read
 
-proc
 hierarchy -top latchp
+proc
 equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd latchp # Constrain all select calls below inside the top module
@@ -12,8 +12,8 @@ select -assert-none t:LDCE %% t:* %D
 
 
 design -load read
-proc
 hierarchy -top latchn
+proc
 equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd latchn # Constrain all select calls below inside the top module
@@ -24,8 +24,8 @@ select -assert-none t:LDCE t:LUT1 %% t:* %D
 
 
 design -load read
-proc
 hierarchy -top latchsr
+proc
 equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd latchsr # Constrain all select calls below inside the top module
diff --git a/tests/xilinx/logic.ys b/tests/xilinx/logic.ys
index e138ae6a3..9ae5993aa 100644
--- a/tests/xilinx/logic.ys
+++ b/tests/xilinx/logic.ys
@@ -1,5 +1,6 @@
 read_verilog logic.v
 hierarchy -top top
+proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
diff --git a/tests/xilinx/macc.ys b/tests/xilinx/macc.ys
index 417a3b21b..6e884b35a 100644
--- a/tests/xilinx/macc.ys
+++ b/tests/xilinx/macc.ys
@@ -1,8 +1,8 @@
 read_verilog macc.v
 design -save read
 
-proc
 hierarchy -top macc
+proc
 #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO
 equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
@@ -15,8 +15,8 @@ select -assert-count 1 t:DSP48E1
 select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D
 
 design -load read
-proc
 hierarchy -top macc2
+proc
 #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO
 equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
diff --git a/tests/xilinx/mul.ys b/tests/xilinx/mul.ys
index f5306e848..66a06efdc 100644
--- a/tests/xilinx/mul.ys
+++ b/tests/xilinx/mul.ys
@@ -1,5 +1,6 @@
 read_verilog mul.v
 hierarchy -top top
+proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
diff --git a/tests/xilinx/mul_unsigned.ys b/tests/xilinx/mul_unsigned.ys
index 77990bd68..62495b90c 100644
--- a/tests/xilinx/mul_unsigned.ys
+++ b/tests/xilinx/mul_unsigned.ys
@@ -1,6 +1,7 @@
 read_verilog mul_unsigned.v
-proc
 hierarchy -top mul_unsigned
+proc
+
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mul_unsigned # Constrain all select calls below inside the top module
diff --git a/tests/xilinx/mux.ys b/tests/xilinx/mux.ys
index 4cdb12e47..420dece4e 100644
--- a/tests/xilinx/mux.ys
+++ b/tests/xilinx/mux.ys
@@ -1,8 +1,8 @@
 read_verilog mux.v
 design -save read
 
-proc
 hierarchy -top mux2
+proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux2 # Constrain all select calls below inside the top module
@@ -12,8 +12,8 @@ select -assert-none t:LUT3 %% t:* %D
 
 
 design -load read
-proc
 hierarchy -top mux4
+proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux4 # Constrain all select calls below inside the top module
@@ -23,8 +23,8 @@ select -assert-none t:LUT6 %% t:* %D
 
 
 design -load read
-proc
 hierarchy -top mux8
+proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
@@ -35,8 +35,8 @@ select -assert-none t:LUT3 t:LUT6 %% t:* %D
 
 
 design -load read
-proc
 hierarchy -top mux16
+proc
 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
-- 
cgit v1.2.3