From 7df0e77565ea9dc46d0eeca536d1be47851326e5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 30 Aug 2019 14:35:05 -0700 Subject: Add mul_unsigned test --- tests/xilinx/mul_unsigned.ys | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 tests/xilinx/mul_unsigned.ys (limited to 'tests/xilinx/mul_unsigned.ys') diff --git a/tests/xilinx/mul_unsigned.ys b/tests/xilinx/mul_unsigned.ys new file mode 100644 index 000000000..72d1f37d7 --- /dev/null +++ b/tests/xilinx/mul_unsigned.ys @@ -0,0 +1,11 @@ +read_verilog mul_unsigned.v +proc +hierarchy -top mul_unsigned +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mul_unsigned # Constrain all select calls below inside the top module +stat +select -assert-count 1 t:BUFG +select -assert-count 1 t:DSP48E1 +select -assert-count 15 t:SRL16E +select -assert-none t:DSP48E1 t:SRL16E t:BUFG %% t:* %D -- cgit v1.2.3 From d508dc2906f27b088e9c1c40e7cf2f475e80c15b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 30 Aug 2019 15:01:08 -0700 Subject: Update test for ffM --- tests/xilinx/mul_unsigned.ys | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tests/xilinx/mul_unsigned.ys') diff --git a/tests/xilinx/mul_unsigned.ys b/tests/xilinx/mul_unsigned.ys index 72d1f37d7..30c034afe 100644 --- a/tests/xilinx/mul_unsigned.ys +++ b/tests/xilinx/mul_unsigned.ys @@ -7,5 +7,5 @@ cd mul_unsigned # Constrain all select calls below inside the top module stat select -assert-count 1 t:BUFG select -assert-count 1 t:DSP48E1 -select -assert-count 15 t:SRL16E -select -assert-none t:DSP48E1 t:SRL16E t:BUFG %% t:* %D +select -assert-count 30 t:FDRE +select -assert-none t:DSP48E1 t:FDRE t:BUFG %% t:* %D -- cgit v1.2.3 From c663a3680b13422c568e3dc438e7b971b81a71c3 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 18 Sep 2019 12:44:34 -0700 Subject: Remove stat --- tests/xilinx/mul_unsigned.ys | 1 - 1 file changed, 1 deletion(-) (limited to 'tests/xilinx/mul_unsigned.ys') diff --git a/tests/xilinx/mul_unsigned.ys b/tests/xilinx/mul_unsigned.ys index 30c034afe..77990bd68 100644 --- a/tests/xilinx/mul_unsigned.ys +++ b/tests/xilinx/mul_unsigned.ys @@ -4,7 +4,6 @@ hierarchy -top mul_unsigned equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mul_unsigned # Constrain all select calls below inside the top module -stat select -assert-count 1 t:BUFG select -assert-count 1 t:DSP48E1 select -assert-count 30 t:FDRE -- cgit v1.2.3