From c79fbfe0a130f1a2979413174c3e5688433bafe3 Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Wed, 26 May 2021 18:22:31 -0400 Subject: mem2reg: tolerate out of bounds constant accesses This brings the mem2reg behavior in line with the nomem2reg behavior. --- tests/verilog/mem_bounds.sv | 27 +++++++++++++++++++++++++++ tests/verilog/mem_bounds.ys | 6 ++++++ 2 files changed, 33 insertions(+) create mode 100644 tests/verilog/mem_bounds.sv create mode 100644 tests/verilog/mem_bounds.ys (limited to 'tests/verilog') diff --git a/tests/verilog/mem_bounds.sv b/tests/verilog/mem_bounds.sv new file mode 100644 index 000000000..7fb2fb042 --- /dev/null +++ b/tests/verilog/mem_bounds.sv @@ -0,0 +1,27 @@ +module top; + reg [0:7] mem [0:2]; + + initial mem[1] = '1; + wire [31:0] a, b, c, d; + assign a = mem[1]; + assign b = mem[-1]; + assign c = mem[-1][0]; + assign d = mem[-1][0:1]; + + always @* begin + + assert ($countbits(a, '0) == 24); + assert ($countbits(a, '1) == 8); + assert ($countbits(a, 'x) == 0); + + assert ($countbits(b, '0) == 24); + assert ($countbits(b, 'x) == 8); + + assert ($countbits(c, '0) == 31); + assert ($countbits(c, 'x) == 1); + + assert ($countbits(d, '0) == 30); + assert ($countbits(d, 'x) == 2); + + end +endmodule diff --git a/tests/verilog/mem_bounds.ys b/tests/verilog/mem_bounds.ys new file mode 100644 index 000000000..42623ad09 --- /dev/null +++ b/tests/verilog/mem_bounds.ys @@ -0,0 +1,6 @@ +read_verilog -sv -mem2reg mem_bounds.sv +proc +flatten +opt -full +select -module top +sat -verify -seq 1 -tempinduct -prove-asserts -show-all -enable_undef -- cgit v1.2.3