From 1d5f3fe5064146955dafdabafe7180ff79c95d08 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Sat, 6 Feb 2021 23:54:17 -0500
Subject: verlog: allow shadowing module ports within generate blocks

This is a somewhat obscure edge case I encountered while working on test
cases for earlier changes. Declarations in generate blocks should not be
checked against the list of ports. This change also adds a check
forbidding declarations within generate blocks being tagged as inputs or
outputs.
---
 tests/verilog/genblk_port_decl.ys | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 tests/verilog/genblk_port_decl.ys

(limited to 'tests/verilog')

diff --git a/tests/verilog/genblk_port_decl.ys b/tests/verilog/genblk_port_decl.ys
new file mode 100644
index 000000000..589d3d2e1
--- /dev/null
+++ b/tests/verilog/genblk_port_decl.ys
@@ -0,0 +1,12 @@
+logger -expect error "Cannot declare module port `\\x' within a generate block\." 1
+read_verilog <<EOT
+module top(x);
+    generate
+        if (1) begin : blk
+            output wire x;
+            assign x = 1;
+        end
+    endgenerate
+    output wire x;
+endmodule
+EOT
-- 
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