From 006c18fc112a686a20b2b138ddc3bf773ee2f2f5 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Wed, 20 Jan 2021 09:15:48 -0700
Subject: sv: fix support wire and var data type modifiers

---
 tests/verilog/wire_and_var.sv | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)
 create mode 100644 tests/verilog/wire_and_var.sv

(limited to 'tests/verilog/wire_and_var.sv')

diff --git a/tests/verilog/wire_and_var.sv b/tests/verilog/wire_and_var.sv
new file mode 100644
index 000000000..79c7c04c6
--- /dev/null
+++ b/tests/verilog/wire_and_var.sv
@@ -0,0 +1,33 @@
+`define TEST(kwd) \
+	kwd kwd``_1; \
+	kwd kwd``_2; \
+	initial kwd``_1 = 1; \
+	assign kwd``_2 = 1;
+
+`define TEST_VAR(kwd) \
+	var kwd var_``kwd``_1; \
+	var kwd var_``kwd``_2; \
+	initial var_``kwd``_1 = 1; \
+	assign var_``kwd``_2 = 1;
+
+`define TEST_WIRE(kwd) \
+	wire kwd wire_``kwd``_1; \
+	wire kwd wire_``kwd``_2; \
+	initial wire_``kwd``_1 = 1; \
+	assign wire_``kwd``_2 = 1;
+
+module top;
+
+`TEST(wire) // wire assigned in a block
+`TEST(reg) // reg assigned in a continuous assignment
+`TEST(logic)
+`TEST(integer)
+
+`TEST_VAR(reg) // reg assigned in a continuous assignment
+`TEST_VAR(logic)
+`TEST_VAR(integer)
+
+`TEST_WIRE(logic) // wire assigned in a block
+`TEST_WIRE(integer) // wire assigned in a block
+
+endmodule
-- 
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