From bbff844acd15c274a6619050d1251aea4698ef56 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Fri, 26 Feb 2021 18:08:23 -0500
Subject: genrtlil: improve name conflict error messaging

---
 tests/verilog/conflict_cell_memory.ys | 9 +++++++++
 1 file changed, 9 insertions(+)
 create mode 100644 tests/verilog/conflict_cell_memory.ys

(limited to 'tests/verilog/conflict_cell_memory.ys')

diff --git a/tests/verilog/conflict_cell_memory.ys b/tests/verilog/conflict_cell_memory.ys
new file mode 100644
index 000000000..ddc67596f
--- /dev/null
+++ b/tests/verilog/conflict_cell_memory.ys
@@ -0,0 +1,9 @@
+logger -expect error "Cannot add cell `\\x' because a memory with the same name was already created" 1
+read_verilog <<EOT
+module mod;
+endmodule
+module top;
+    reg [2:0] x [0:0];
+    mod x();
+endmodule
+EOT
-- 
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