From 88f59770932720cfc1e987c98e53faedd7388ed8 Mon Sep 17 00:00:00 2001 From: tux3 Date: Wed, 5 Jun 2019 00:47:54 +0200 Subject: SystemVerilog support for implicit named port connections This is the `foo foo(.port1, .port2);` SystemVerilog syntax introduced in IEEE1800-2005. --- tests/various/implicit_ports.sv | 19 +++++++++++++++++++ tests/various/implicit_ports.ys | 8 ++++++++ 2 files changed, 27 insertions(+) create mode 100644 tests/various/implicit_ports.sv create mode 100644 tests/various/implicit_ports.ys (limited to 'tests/various') diff --git a/tests/various/implicit_ports.sv b/tests/various/implicit_ports.sv new file mode 100644 index 000000000..6a766bd51 --- /dev/null +++ b/tests/various/implicit_ports.sv @@ -0,0 +1,19 @@ +// Test implicit port connections +module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] result); + assign cout = cin; + assign result = a + b; +endmodule + +module named_ports(output [2:0] alu_result, output cout); + wire [2:0] a = 3'b010, b = 3'b100; + wire cin = 1; + + alu alu ( + .a(a), + .b, // Implicit connection is equivalent to .b(b) + .cin(), // Explicitely unconnected + .cout(cout), + .result(alu_result) + ); +endmodule + diff --git a/tests/various/implicit_ports.ys b/tests/various/implicit_ports.ys new file mode 100644 index 000000000..7b4764921 --- /dev/null +++ b/tests/various/implicit_ports.ys @@ -0,0 +1,8 @@ +read_verilog -sv implicit_ports.sv +proc; opt + +flatten +select -module named_ports + +sat -verify -prove alu_result 6 +sat -verify -set-all-undef cout -- cgit v1.2.3