From 86efe9a616b70ffa64bb344d83aa42956e5fd470 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 12 Jun 2019 09:01:15 -0700 Subject: Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux" This reverts commit 2223ca91b0cc559bb876e8e97372a8f77da1603e, reversing changes made to eaee250a6e63e58dfef63fa30c4120db78223e24. --- tests/various/muxpack.v | 26 -------------------------- tests/various/muxpack.ys | 15 --------------- 2 files changed, 41 deletions(-) (limited to 'tests/various') diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index f1bd5ea8e..7c189fff8 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -110,29 +110,3 @@ always @* begin endcase end endmodule - -module mux_if_bal_8_2 #(parameter N=8, parameter W=2) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); -always @* - if (s[0] == 1'b0) - if (s[1] == 1'b0) - if (s[2] == 1'b0) - o <= i[0*W+:W]; - else - o <= i[1*W+:W]; - else - if (s[2] == 1'b0) - o <= i[2*W+:W]; - else - o <= i[3*W+:W]; - else - if (s[1] == 1'b0) - if (s[2] == 1'b0) - o <= i[4*W+:W]; - else - o <= i[5*W+:W]; - else - if (s[2] == 1'b0) - o <= i[6*W+:W]; - else - o <= i[7*W+:W]; -endmodule diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys index 9ea743b9f..0c5b82818 100644 --- a/tests/various/muxpack.ys +++ b/tests/various/muxpack.ys @@ -133,18 +133,3 @@ design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter - -design -load read -hierarchy -top mux_if_bal_8_2 -prep -design -save gold -muxpack -opt -stat -select -assert-count 7 t:$mux -select -assert-count 0 t:$pmux -design -stash gate -design -import gold -as gold -design -import gate -as gate -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter -- cgit v1.2.3 From 2cbcd6224c0293a3abdf00f51c515fc556d9d3e1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 12 Jun 2019 09:05:02 -0700 Subject: Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux" This reverts commit a138381ac3f2c820d187f08531ffd823d6cbcfd5, reversing changes made to b77c5da76919f7f99f171a0a2775896fbc8debc2. --- tests/various/shregmap.v | 22 ---------------------- tests/various/shregmap.ys | 31 ------------------------------- 2 files changed, 53 deletions(-) delete mode 100644 tests/various/shregmap.v delete mode 100644 tests/various/shregmap.ys (limited to 'tests/various') diff --git a/tests/various/shregmap.v b/tests/various/shregmap.v deleted file mode 100644 index 56e05c2c0..000000000 --- a/tests/various/shregmap.v +++ /dev/null @@ -1,22 +0,0 @@ -module shregmap_test(input i, clk, output [1:0] q); -reg head = 1'b0; -reg [3:0] shift1 = 4'b0000; -reg [3:0] shift2 = 4'b0000; - -always @(posedge clk) begin - head <= i; - shift1 <= {shift1[2:0], head}; - shift2 <= {shift2[2:0], head}; -end - -assign q = {shift2[3], shift1[3]}; -endmodule - -module $__SHREG_DFF_P_(input C, D, output Q); -parameter DEPTH = 1; -parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}}; -reg [DEPTH-1:0] r = INIT; -always @(posedge C) - r <= { r[DEPTH-2:0], D }; -assign Q = r[DEPTH-1]; -endmodule diff --git a/tests/various/shregmap.ys b/tests/various/shregmap.ys deleted file mode 100644 index ca7f47015..000000000 --- a/tests/various/shregmap.ys +++ /dev/null @@ -1,31 +0,0 @@ -read_verilog shregmap.v -design -copy-to model $__SHREG_DFF_P_ -hierarchy -top shregmap_test -prep -design -save gold - -techmap -shregmap -init - -opt - -stat -# show -width -select -assert-count 1 t:$_DFF_P_ -select -assert-count 2 t:$__SHREG_DFF_P_ - -design -stash gate - -design -import gold -as gold -design -import gate -as gate -design -copy-from model -as $__SHREG_DFF_P_ \$__SHREG_DFF_P_ -prep - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports -seq 5 miter - -design -load gold -stat - -design -load gate -stat -- cgit v1.2.3 From 9f275c1437cb48c28b717f0996edab9da9e73aa0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 12 Jun 2019 16:33:05 -0700 Subject: Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux" This reverts commit 2223ca91b0cc559bb876e8e97372a8f77da1603e, reversing changes made to eaee250a6e63e58dfef63fa30c4120db78223e24. --- tests/various/muxpack.v | 112 --------------------------------------- tests/various/muxpack.ys | 135 ----------------------------------------------- 2 files changed, 247 deletions(-) delete mode 100644 tests/various/muxpack.v delete mode 100644 tests/various/muxpack.ys (limited to 'tests/various') diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v deleted file mode 100644 index 7c189fff8..000000000 --- a/tests/various/muxpack.v +++ /dev/null @@ -1,112 +0,0 @@ -module mux_if_unbal_4_1 #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); -always @* - if (s == 0) o <= i[0*W+:W]; - else if (s == 1) o <= i[1*W+:W]; - else if (s == 2) o <= i[2*W+:W]; - else if (s == 3) o <= i[3*W+:W]; - else o <= {W{1'bx}}; -endmodule - -module mux_if_unbal_5_3 #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); -always @* begin - o <= {W{1'bx}}; - if (s == 0) o <= i[0*W+:W]; - if (s == 1) o <= i[1*W+:W]; - if (s == 2) o <= i[2*W+:W]; - if (s == 3) o <= i[3*W+:W]; - if (s == 4) o <= i[4*W+:W]; -end -endmodule - -module mux_if_unbal_5_3_invert #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); -always @* - if (s != 0) - if (s != 1) - if (s != 2) - if (s != 3) - if (s != 4) o <= i[4*W+:W]; - else o <= i[0*W+:W]; - else o <= i[3*W+:W]; - else o <= i[2*W+:W]; - else o <= i[1*W+:W]; - else o <= {W{1'bx}}; -endmodule - -module mux_if_unbal_5_3_width_mismatch #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); -always @* begin - o <= {W{1'bx}}; - if (s == 0) o <= i[0*W+:W]; - if (s == 1) o <= i[1*W+:W]; - if (s == 2) o[W-2:0] <= i[2*W+:W-1]; - if (s == 3) o <= i[3*W+:W]; - if (s == 4) o <= i[4*W+:W]; -end -endmodule - -module mux_if_unbal_4_1_missing #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); -always @* begin - if (s == 0) o <= i[0*W+:W]; -// else if (s == 1) o <= i[1*W+:W]; -// else if (s == 2) o <= i[2*W+:W]; - else if (s == 3) o <= i[3*W+:W]; - else o <= {W{1'bx}}; -end -endmodule - -module mux_if_unbal_5_3_order #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); -always @* begin - o <= {W{1'bx}}; - if (s == 3) o <= i[3*W+:W]; - if (s == 2) o <= i[2*W+:W]; - if (s == 1) o <= i[1*W+:W]; - if (s == 4) o <= i[4*W+:W]; - if (s == 0) o <= i[0*W+:W]; -end -endmodule - -module mux_if_unbal_4_1_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); -always @* - if (s == 0) o <= i[0*W+:W]; - else if (s == 1) o <= i[1*W+:W]; - else if (s == 2) o <= i[2*W+:W]; - else if (s == 3) o <= i[3*W+:W]; - else if (s == 0) o <= {W{1'b0}}; - else o <= {W{1'bx}}; -endmodule - -module mux_if_unbal_5_3_nonexcl #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); -always @* begin - o <= {W{1'bx}}; - if (s == 0) o <= i[0*W+:W]; - if (s == 1) o <= i[1*W+:W]; - if (s == 2) o <= i[2*W+:W]; - if (s == 3) o <= i[3*W+:W]; - if (s == 4) o <= i[4*W+:W]; - if (s == 0) o <= i[2*W+:W]; -end -endmodule - -module mux_case_unbal_8_7#(parameter N=8, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o); -always @* begin - o <= {W{1'bx}}; - case (s) - 0: o <= i[0*W+:W]; - default: - case (s) - 1: o <= i[1*W+:W]; - 2: o <= i[2*W+:W]; - default: - case (s) - 3: o <= i[3*W+:W]; - 4: o <= i[4*W+:W]; - 5: o <= i[5*W+:W]; - default: - case (s) - 6: o <= i[6*W+:W]; - default: o <= i[7*W+:W]; - endcase - endcase - endcase - endcase -end -endmodule diff --git a/tests/various/muxpack.ys b/tests/various/muxpack.ys deleted file mode 100644 index 0c5b82818..000000000 --- a/tests/various/muxpack.ys +++ /dev/null @@ -1,135 +0,0 @@ -read_verilog muxpack.v -design -save read -hierarchy -top mux_if_unbal_4_1 -prep -design -save gold -muxpack -opt -stat -select -assert-count 0 t:$mux -select -assert-count 1 t:$pmux -design -stash gate -design -import gold -as gold -design -import gate -as gate -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter - -design -load read -hierarchy -top mux_if_unbal_5_3 -prep -design -save gold -muxpack -opt -stat -select -assert-count 0 t:$mux -select -assert-count 1 t:$pmux -design -stash gate -design -import gold -as gold -design -import gate -as gate -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter - -design -load read -hierarchy -top mux_if_unbal_5_3_invert -prep -design -save gold -muxpack -opt -stat -select -assert-count 0 t:$mux -select -assert-count 1 t:$pmux -design -stash gate -design -import gold -as gold -design -import gate -as gate -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter - -design -load read -hierarchy -top mux_if_unbal_5_3_width_mismatch -prep -design -save gold -muxpack -opt -stat -select -assert-count 0 t:$mux -select -assert-count 2 t:$pmux -design -stash gate -design -import gold -as gold -design -import gate -as gate -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter - -design -load read -hierarchy -top mux_if_unbal_4_1_missing -prep -design -save gold -muxpack -opt -stat -select -assert-count 0 t:$mux -select -assert-count 1 t:$pmux -design -stash gate -design -import gold -as gold -design -import gate -as gate -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter - -design -load read -hierarchy -top mux_if_unbal_5_3_order -prep -design -save gold -muxpack -opt -stat -select -assert-count 0 t:$mux -select -assert-count 1 t:$pmux -design -stash gate -design -import gold -as gold -design -import gate -as gate -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter - -design -load read -hierarchy -top mux_if_unbal_4_1_nonexcl -prep -design -save gold -muxpack -opt -stat -select -assert-count 0 t:$mux -select -assert-count 1 t:$pmux -design -stash gate -design -import gold -as gold -design -import gate -as gate -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter - -design -load read -hierarchy -top mux_if_unbal_5_3_nonexcl -prep -design -save gold -muxpack -opt -stat -select -assert-count 0 t:$mux -select -assert-count 1 t:$pmux -design -stash gate -design -import gold -as gold -design -import gate -as gate -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter - -design -load read -hierarchy -top mux_case_unbal_8_7 -prep -design -save gold -muxpack -opt -stat -select -assert-count 0 t:$mux -select -assert-count 1 t:$pmux -design -stash gate -design -import gold -as gold -design -import gate -as gate -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports miter -- cgit v1.2.3