From 1cc106452fb25d082ca9491c24df97cc51d4b992 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 19 Nov 2019 17:05:14 -0800
Subject: Add a equiv test too

---
 tests/various/abc9.v  |  7 +++++++
 tests/various/abc9.ys | 16 ++++++++++++++++
 2 files changed, 23 insertions(+)

(limited to 'tests/various')

diff --git a/tests/various/abc9.v b/tests/various/abc9.v
index 30ebd4e26..e53dcdb21 100644
--- a/tests/various/abc9.v
+++ b/tests/various/abc9.v
@@ -9,3 +9,10 @@ wire w;
 unknown u(~i, w);
 unknown2 u2(w, o);
 endmodule
+
+module abc9_test031(input clk, d, r, output reg q);
+initial q = 1'b0;
+always @(negedge clk or negedge r)
+    if (r) q <= 1'b0;
+    else q <= d;
+endmodule
diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys
index 5c9a4075d..9e732bdc8 100644
--- a/tests/various/abc9.ys
+++ b/tests/various/abc9.ys
@@ -22,3 +22,19 @@ abc9 -lut 4
 select -assert-count 1 t:$lut r:LUT=2'b01 r:WIDTH=1 %i %i
 select -assert-count 1 t:unknown
 select -assert-none t:$lut t:unknown %% t: %D
+
+design -load read
+hierarchy -top abc9_test031
+proc
+async2sync
+design -save gold
+
+abc9 -lut 4
+check
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -seq 10 -verify -prove-asserts -show-ports miter
-- 
cgit v1.2.3


From 39fdcb892b1b65363fdf7c1bc6d9e2612c1c38e6 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 21 Nov 2019 16:27:34 -0800
Subject: async2sync -> clk2fflogic

---
 tests/various/abc9.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests/various')

diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys
index 9e732bdc8..f7a3f1fa0 100644
--- a/tests/various/abc9.ys
+++ b/tests/various/abc9.ys
@@ -26,7 +26,7 @@ select -assert-none t:$lut t:unknown %% t: %D
 design -load read
 hierarchy -top abc9_test031
 proc
-async2sync
+clk2fflogic
 design -save gold
 
 abc9 -lut 4
-- 
cgit v1.2.3


From 6841e3b1c2b2bc3124810f3a8f96ed00a96e954c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 21 Nov 2019 16:33:20 -0800
Subject: Another sloppy mistake!

---
 tests/various/abc9.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests/various')

diff --git a/tests/various/abc9.v b/tests/various/abc9.v
index 85828bf30..f0b3f6837 100644
--- a/tests/various/abc9.v
+++ b/tests/various/abc9.v
@@ -13,6 +13,6 @@ endmodule
 module abc9_test032(input clk, d, r, output reg q);
 initial q = 1'b0;
 always @(negedge clk or negedge r)
-    if (r) q <= 1'b0;
+    if (!r) q <= 1'b0;
     else q <= d;
 endmodule
-- 
cgit v1.2.3


From 151f7533e89d1a6db9c52b3c5d77adb2089db366 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 11 Dec 2019 16:26:19 -0800
Subject: Add testcase

---
 tests/various/bug1531.ys | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)
 create mode 100644 tests/various/bug1531.ys

(limited to 'tests/various')

diff --git a/tests/various/bug1531.ys b/tests/various/bug1531.ys
new file mode 100644
index 000000000..542223030
--- /dev/null
+++ b/tests/various/bug1531.ys
@@ -0,0 +1,34 @@
+read_verilog <<EOT
+module top (y, clk, w);
+   output reg y = 1'b0;
+   input clk, w;
+   reg [1:0] i = 2'b00;
+   always @(posedge clk)
+     // If the constant below is set to 2'b00, the correct output is generated.
+     //       vvvv
+     for (i = 1'b0; i < 2'b01; i = i + 2'b01) 
+       y <= w || i[1:1];
+endmodule
+EOT
+
+synth
+design -stash gate
+
+read_verilog <<EOT
+module gold (y, clk, w);
+  input clk;
+  wire [1:0] i;
+  input w;
+  output y;
+  reg y = 1'h0;
+  always @(posedge clk)
+      y <= w;
+  assign i = 2'h0;
+endmodule
+EOT
+proc gold
+
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -seq 10 -verify -prove-asserts -show-ports miter
-- 
cgit v1.2.3


From 1187e91c2f2684cb204c555cb3d53b68c7381c40 Mon Sep 17 00:00:00 2001
From: "N. Engelhardt" <nak@symbioticeda.com>
Date: Thu, 12 Dec 2019 20:51:59 +0100
Subject: add test and make help message more verbose

---
 tests/various/scratchpad.sh | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
 create mode 100755 tests/various/scratchpad.sh

(limited to 'tests/various')

diff --git a/tests/various/scratchpad.sh b/tests/various/scratchpad.sh
new file mode 100755
index 000000000..4e92473f8
--- /dev/null
+++ b/tests/various/scratchpad.sh
@@ -0,0 +1,14 @@
+#!/bin/bash
+
+trap 'echo "ERROR in scratchpad.sh" >&2; exit 1' ERR
+
+../../yosys -qp "scratchpad -set foo \"bar baz\"; \
+scratchpad -copy foo oof; scratchpad -unset foo; \
+tee -o scratchpad1.log scratchpad -get oof; \
+tee -o scratchpad2.log scratchpad -get foo"
+
+test "$(cat scratchpad1.log)" = "bar baz"
+test "$(cat scratchpad2.log)" = "\"foo\" not set"
+
+rm scratchpad1.log
+rm scratchpad2.log
-- 
cgit v1.2.3


From abcd82dacadc8b5af6b2b7f6d7cbdb635d276440 Mon Sep 17 00:00:00 2001
From: "N. Engelhardt" <nak@symbioticeda.com>
Date: Mon, 16 Dec 2019 13:09:31 +0100
Subject: add assert option to scratchpad command

---
 tests/various/scratchpad.sh | 14 --------------
 tests/various/scratchpad.ys |  5 +++++
 2 files changed, 5 insertions(+), 14 deletions(-)
 delete mode 100755 tests/various/scratchpad.sh
 create mode 100644 tests/various/scratchpad.ys

(limited to 'tests/various')

diff --git a/tests/various/scratchpad.sh b/tests/various/scratchpad.sh
deleted file mode 100755
index 4e92473f8..000000000
--- a/tests/various/scratchpad.sh
+++ /dev/null
@@ -1,14 +0,0 @@
-#!/bin/bash
-
-trap 'echo "ERROR in scratchpad.sh" >&2; exit 1' ERR
-
-../../yosys -qp "scratchpad -set foo \"bar baz\"; \
-scratchpad -copy foo oof; scratchpad -unset foo; \
-tee -o scratchpad1.log scratchpad -get oof; \
-tee -o scratchpad2.log scratchpad -get foo"
-
-test "$(cat scratchpad1.log)" = "bar baz"
-test "$(cat scratchpad2.log)" = "\"foo\" not set"
-
-rm scratchpad1.log
-rm scratchpad2.log
diff --git a/tests/various/scratchpad.ys b/tests/various/scratchpad.ys
new file mode 100644
index 000000000..dc94081ea
--- /dev/null
+++ b/tests/various/scratchpad.ys
@@ -0,0 +1,5 @@
+scratchpad -set foo "bar baz"
+scratchpad -copy foo oof
+scratchpad -unset foo
+scratchpad -assert oof "bar baz"
+scratchpad -assert-unset foo
-- 
cgit v1.2.3


From fc4b8b89912c14f42b04a7c9f2ce350db3ce7c0b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Dec 2019 14:56:14 -0800
Subject: Remove submod changes

---
 tests/various/submod.ys | 102 ------------------------------------------------
 1 file changed, 102 deletions(-)
 delete mode 100644 tests/various/submod.ys

(limited to 'tests/various')

diff --git a/tests/various/submod.ys b/tests/various/submod.ys
deleted file mode 100644
index 9d7dabdd7..000000000
--- a/tests/various/submod.ys
+++ /dev/null
@@ -1,102 +0,0 @@
-read_verilog <<EOT
-module top(input a, output b);
-wire c;
-(* submod="bar" *) sub s1(a, c);
-assign b = c;
-endmodule
-
-module sub(input a, output c);
-assign c = a;
-endmodule
-EOT
-
-hierarchy -top top
-proc
-design -save gold
-
-submod
-check -assert
-design -stash gate
-
-design -import gold -as gold
-design -import gate -as gate
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-
-
-design -reset
-read_verilog <<EOT
-module top(input a, output [1:0] b);
-(* submod="bar" *) sub s1(a, b[1]);
-assign b[0] = 1'b0;
-endmodule
-
-module sub(input a, output c);
-assign c = a;
-endmodule
-EOT
-
-hierarchy -top top
-proc
-design -save gold
-
-submod
-check -assert top
-design -stash gate
-
-design -import gold -as gold
-design -import gate -as gate
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-
-
-design -reset
-read_verilog <<EOT
-module top(input a, output [1:0] b, c);
-(* submod="bar" *) sub s1(a, b[0]);
-(* submod="bar" *) sub s2(a, c[1]);
-assign c = b;
-endmodule
-
-module sub(input a, output c);
-assign c = a;
-endmodule
-EOT
-
-hierarchy -top top
-proc
-design -save gold
-
-submod
-check -assert top
-design -stash gate
-
-design -import gold -as gold
-design -import gate -as gate
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-
-
-
-design -reset
-read_verilog -icells <<EOT
-module top(input d, c, (* init = 3'b011 *) output reg [2:0] q);
-(* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q[1]));
-DFF s2(.D(d), .C(c), .Q(q[0]));
-DFF s3(.D(d), .C(c), .Q(q[2]));
-endmodule
-
-module DFF(input D, C, output Q);
-parameter INIT = 1'b0;
-endmodule
-EOT
-
-hierarchy -top top
-proc
-
-submod
-dffinit -ff DFF Q INIT
-check -noinit -assert
-- 
cgit v1.2.3


From 00964e999d5bc1825ff664e1514efcacb6d2e23f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 14 Jan 2020 10:13:03 -0800
Subject: autoname: add testcase with $-prefix-ed port

---
 tests/various/autoname.ys | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 tests/various/autoname.ys

(limited to 'tests/various')

diff --git a/tests/various/autoname.ys b/tests/various/autoname.ys
new file mode 100644
index 000000000..830962e81
--- /dev/null
+++ b/tests/various/autoname.ys
@@ -0,0 +1,19 @@
+read_ilang <<EOT
+autoidx 2
+module \top
+  wire output 3 $y
+  wire input 1 \a
+  wire input 2 \b
+  cell $and \b_$and_B
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \a
+    connect \B \b
+    connect \Y $y
+  end
+end
+EOT
+autoname
-- 
cgit v1.2.3


From 6a163b5ddd378ba847054ad9226af8ca569c977a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 17 Jan 2020 17:07:03 -0800
Subject: xilinx_dsp: another typo; move xilinx specific test

---
 tests/various/bug1462.ys | 11 -----------
 1 file changed, 11 deletions(-)
 delete mode 100644 tests/various/bug1462.ys

(limited to 'tests/various')

diff --git a/tests/various/bug1462.ys b/tests/various/bug1462.ys
deleted file mode 100644
index 15cab5121..000000000
--- a/tests/various/bug1462.ys
+++ /dev/null
@@ -1,11 +0,0 @@
-read_verilog << EOF
-module top(...);
-input wire [31:0] A;
-output wire [31:0] P;
-
-assign P = A * 32'h12300000;
-
-endmodule
-EOF
-
-synth_xilinx
-- 
cgit v1.2.3


From cd8f55a91100b8dcf8b4775803cbacf70f5a998c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 21 Jan 2020 09:43:04 -0800
Subject: write_xaiger: fix for (* keep *) on flop output

---
 tests/various/abc9.ys | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

(limited to 'tests/various')

diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys
index 81d0afd1b..0c7695089 100644
--- a/tests/various/abc9.ys
+++ b/tests/various/abc9.ys
@@ -14,6 +14,7 @@ design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
 
+
 design -load read
 hierarchy -top abc9_test028
 proc
@@ -23,6 +24,7 @@ select -assert-count 1 t:$lut r:LUT=2'b01 r:WIDTH=1 %i %i
 select -assert-count 1 t:unknown
 select -assert-none t:$lut t:unknown %% t: %D
 
+
 design -load read
 hierarchy -top abc9_test032
 proc
@@ -38,3 +40,16 @@ design -import gate -as gate
 
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -seq 10 -verify -prove-asserts -show-ports miter
+
+
+design -reset
+read_verilog -icells <<EOT
+module abc9_test036(input clk, d, output q);
+(* keep *) reg w;
+$__ABC9_FF_ ff(.D(d), .Q(w));
+wire \ff.clock = clk;
+wire \ff.init = 1'b0;
+assign q = w;
+endmodule
+EOT
+abc9 -lut 4 -dff
-- 
cgit v1.2.3


From d004953772bdf4b4183621c2cc2b776dbaa237af Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 28 Jan 2020 18:11:34 -0800
Subject: Add "help -all" and "help -celltypes" sanity test

---
 tests/various/help.ys | 2 ++
 1 file changed, 2 insertions(+)
 create mode 100644 tests/various/help.ys

(limited to 'tests/various')

diff --git a/tests/various/help.ys b/tests/various/help.ys
new file mode 100644
index 000000000..9283ce8f1
--- /dev/null
+++ b/tests/various/help.ys
@@ -0,0 +1,2 @@
+help -all
+help -celltypes
-- 
cgit v1.2.3