From 88f59770932720cfc1e987c98e53faedd7388ed8 Mon Sep 17 00:00:00 2001
From: tux3 <barrdetwix@gmail.com>
Date: Wed, 5 Jun 2019 00:47:54 +0200
Subject: SystemVerilog support for implicit named port connections

This is the `foo foo(.port1, .port2);` SystemVerilog syntax
introduced in IEEE1800-2005.
---
 tests/various/implicit_ports.ys | 8 ++++++++
 1 file changed, 8 insertions(+)
 create mode 100644 tests/various/implicit_ports.ys

(limited to 'tests/various/implicit_ports.ys')

diff --git a/tests/various/implicit_ports.ys b/tests/various/implicit_ports.ys
new file mode 100644
index 000000000..7b4764921
--- /dev/null
+++ b/tests/various/implicit_ports.ys
@@ -0,0 +1,8 @@
+read_verilog -sv implicit_ports.sv
+proc; opt
+
+flatten
+select -module named_ports
+
+sat -verify -prove alu_result 6
+sat -verify -set-all-undef cout
-- 
cgit v1.2.3