From a10016ccc57638aa837acd76fc93f296eda83b32 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 9 Jan 2020 18:17:06 -0800
Subject: Add abc9 sanity test

---
 tests/techmap/abc9.ys | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)
 create mode 100644 tests/techmap/abc9.ys

(limited to 'tests/techmap/abc9.ys')

diff --git a/tests/techmap/abc9.ys b/tests/techmap/abc9.ys
new file mode 100644
index 000000000..20f263da8
--- /dev/null
+++ b/tests/techmap/abc9.ys
@@ -0,0 +1,40 @@
+read_verilog <<EOT
+`define N 256
+module top(input [`N-1:0] a, output o);
+wire [`N-2:0] w;
+assign w[0] = a[0] & a[1];
+genvar i;
+generate for (i = 1; i < `N-1; i++)
+assign w[i] = w[i-1] & a[i+1];
+endgenerate
+assign o = w[`N-2];
+endmodule
+EOT
+simplemap
+dump
+design -save gold
+
+abc9 -lut 4
+
+design -load gold
+abc9 -lut 4 -fast
+
+design -load gold
+scratchpad -copy abc9.script.default.area abc9.script
+abc9 -lut 4
+
+design -load gold
+scratchpad -copy abc9.script.default.fast abc9.script
+abc9 -lut 4
+
+design -load gold
+scratchpad -copy abc9.script.flow abc9.script
+abc9 -lut 4
+
+design -load gold
+scratchpad -copy abc9.script.flow2 abc9.script
+abc9 -lut 4
+
+design -load gold
+scratchpad -copy abc9.script.flow3 abc9.script
+abc9 -lut 4
-- 
cgit v1.2.3


From 9ec948f3965eef214bee3af778b67fdd6ee86929 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 13 Jan 2020 19:07:55 -0800
Subject: write_xaiger: add support and test for (* keep *) on wires

---
 tests/techmap/abc9.ys | 13 +++++++++++++
 1 file changed, 13 insertions(+)

(limited to 'tests/techmap/abc9.ys')

diff --git a/tests/techmap/abc9.ys b/tests/techmap/abc9.ys
index 20f263da8..46b6f08d2 100644
--- a/tests/techmap/abc9.ys
+++ b/tests/techmap/abc9.ys
@@ -38,3 +38,16 @@ abc9 -lut 4
 design -load gold
 scratchpad -copy abc9.script.flow3 abc9.script
 abc9 -lut 4
+
+design -reset
+read_verilog <<EOT
+module top(input a, b, output o);
+(* keep *) wire w = a & b;
+assign o = ~w;
+endmodule
+EOT
+
+simplemap
+equiv_opt -assert abc9 -lut 4
+design -load postopt
+select -assert-count 2 t:$lut
-- 
cgit v1.2.3


From a6d4ea74634826741f09793c36d596f2fa239f62 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 13 Jan 2020 19:21:11 -0800
Subject: abc9: respect (* keep *) on cells

---
 tests/techmap/abc9.ys | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

(limited to 'tests/techmap/abc9.ys')

diff --git a/tests/techmap/abc9.ys b/tests/techmap/abc9.ys
index 46b6f08d2..d5a63e1cb 100644
--- a/tests/techmap/abc9.ys
+++ b/tests/techmap/abc9.ys
@@ -51,3 +51,18 @@ simplemap
 equiv_opt -assert abc9 -lut 4
 design -load postopt
 select -assert-count 2 t:$lut
+
+design -reset
+read_verilog -icells <<EOT
+module top(input a, b, output o);
+wire w;
+(* keep *) $_AND_ gate (.Y(w), .A(a), .B(b));
+assign o = ~w;
+endmodule
+EOT
+
+simplemap
+equiv_opt -assert abc9 -lut 4
+design -load postopt
+select -assert-count 1 t:$lut
+select -assert-count 1 t:$_AND_
-- 
cgit v1.2.3


From 5918ede9bd7568d5a5156f20fdc4ce215d4968f8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 15 Jan 2020 14:36:05 -0800
Subject: abc9: aAdd test to check $_NOT_s are absorbed

---
 tests/techmap/abc9.ys | 12 ++++++++++++
 1 file changed, 12 insertions(+)

(limited to 'tests/techmap/abc9.ys')

diff --git a/tests/techmap/abc9.ys b/tests/techmap/abc9.ys
index 20f263da8..62b5dfef6 100644
--- a/tests/techmap/abc9.ys
+++ b/tests/techmap/abc9.ys
@@ -38,3 +38,15 @@ abc9 -lut 4
 design -load gold
 scratchpad -copy abc9.script.flow3 abc9.script
 abc9 -lut 4
+
+
+design -reset
+read_verilog -icells <<EOT
+module top(input a, b, output o);
+assign o = ~(a & b);
+endmodule
+EOT
+abc9 -lut 4
+clean
+select -assert-count 1 t:$lut
+select -assert-none t:$lut t:* %D
-- 
cgit v1.2.3