From 61a1f3f49b7bd0478b92c0933c487af5803c53f9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 11 Dec 2019 23:48:09 -0800
Subject: Make testcase clearer with \o having its own init

---
 tests/sat/initval.ys | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'tests/sat/initval.ys')

diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys
index 337aa9343..6cb68a8d3 100644
--- a/tests/sat/initval.ys
+++ b/tests/sat/initval.ys
@@ -6,6 +6,8 @@ sat -seq 10 -prove-asserts
 design -reset
 read_verilog -icells <<EOT
 module top(input clk, i, output o, p);
+(* init = 1'b0 *)
+wire o;
 (* init = 1'bx *)
 wire p = o;
 $_DFF_P_ dff (.C(clk), .D(i), .Q(o));
-- 
cgit v1.2.3