From e89cc9c02fc5d9ff2a6eedc524e7c0420666ac22 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Tue, 4 Aug 2020 16:30:24 +0200
Subject: peepopt.muldiv: Add a signedness check.

Fixes #2318.
---
 tests/opt/bug2318.ys | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 tests/opt/bug2318.ys

(limited to 'tests/opt')

diff --git a/tests/opt/bug2318.ys b/tests/opt/bug2318.ys
new file mode 100644
index 000000000..9de6f88ec
--- /dev/null
+++ b/tests/opt/bug2318.ys
@@ -0,0 +1,12 @@
+read_verilog <<EOT
+module t(input [3:0] A, input [3:0] B, output signed [3:0] Y);
+
+wire [7:0] P = A * B;
+wire signed [7:0] SP = P;
+wire signed [3:0] SB = B;
+assign Y = SP / SB;
+
+endmodule
+EOT
+
+equiv_opt -assert peepopt
-- 
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