From e64456f92025c26f8b66e77901f78eca726d856a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Thu, 21 Oct 2021 02:58:10 +0200
Subject: extract_reduce: Refactor and fix input signal construction.

Fixes #3047.
---
 tests/opt/bug3047.ys | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 tests/opt/bug3047.ys

(limited to 'tests/opt')

diff --git a/tests/opt/bug3047.ys b/tests/opt/bug3047.ys
new file mode 100644
index 000000000..6713877ce
--- /dev/null
+++ b/tests/opt/bug3047.ys
@@ -0,0 +1,12 @@
+read_verilog << EOT
+
+module test (A, B, C, D, Y);
+  input A, B, C, D;
+  output Y;
+  assign Y = A^B^C^D^A;
+endmodule
+
+EOT
+
+techmap
+equiv_opt -assert extract_reduce
-- 
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