From 98003430d672af05cff7d950e08a42526e766f74 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Sun, 8 Aug 2021 00:33:31 +0200
Subject: opt_merge: Use FfInitVals.

Partial #2920 fix.
---
 tests/opt/bug2920.ys        | 42 ++++++++++++++++++++++++++++++++++++++++++
 tests/opt/opt_merge_init.ys |  2 +-
 2 files changed, 43 insertions(+), 1 deletion(-)
 create mode 100644 tests/opt/bug2920.ys

(limited to 'tests/opt')

diff --git a/tests/opt/bug2920.ys b/tests/opt/bug2920.ys
new file mode 100644
index 000000000..a8281a73a
--- /dev/null
+++ b/tests/opt/bug2920.ys
@@ -0,0 +1,42 @@
+read_ilang <<EOT
+
+module \mod
+  wire input 1 \clk
+  attribute \init 2'00
+  wire width 2 $q1
+  attribute \init 2'00
+  wire width 2 $q2
+  wire output 2 width 4 \q
+  cell $dff $ff1
+    parameter \CLK_POLARITY 1'1
+    parameter \WIDTH 1
+    connect \CLK \clk
+    connect \D 1'0
+    connect \Q $q1 [0]
+  end
+  cell $dff $ff2
+    parameter \CLK_POLARITY 1'1
+    parameter \WIDTH 1
+    connect \CLK \clk
+    connect \D 1'0
+    connect \Q $q2 [0]
+  end
+  cell $dff $ff3
+    parameter \CLK_POLARITY 1'1
+    parameter \WIDTH 2
+    connect \CLK \clk
+    connect \D 2'00
+    connect \Q { $q1 [1] $q2 [1] }
+  end
+  connect \q [0] $q1 [0]
+  connect \q [1] $q2 [0]
+  connect \q [2] $q1 [1]
+  connect \q [3] $q2 [1]
+end
+
+EOT
+
+opt_clean
+opt_merge
+opt_dff
+opt_clean
diff --git a/tests/opt/opt_merge_init.ys b/tests/opt/opt_merge_init.ys
index 0176f09c7..20b6cabee 100644
--- a/tests/opt/opt_merge_init.ys
+++ b/tests/opt/opt_merge_init.ys
@@ -48,7 +48,7 @@ EOT
 
 opt_merge
 select -assert-count 1 t:$dff
-select -assert-count 1 a:init=2'bx1
+select -assert-count 1 a:init=2'bx1 a:init=2'b1x
 
 
 design -reset
-- 
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