From 5628f5a88fa49c126af0149e302a8292229ab9df Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= <mwk@0x04.net>
Date: Tue, 25 May 2021 15:17:29 +0200
Subject: opt_mem_feedback: Respect write port priority.

---
 tests/opt/opt_mem_feedback.ys | 47 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

(limited to 'tests/opt')

diff --git a/tests/opt/opt_mem_feedback.ys b/tests/opt/opt_mem_feedback.ys
index 6a68921c3..56078ec27 100644
--- a/tests/opt/opt_mem_feedback.ys
+++ b/tests/opt/opt_mem_feedback.ys
@@ -140,3 +140,50 @@ memory_map
 design -save postopt
 
 equiv_opt -assert -run prepare: :
+
+
+
+design -reset
+
+# Tricky case: legit feedback path, but priority needs to be preserved.
+
+read_verilog << EOT
+
+module top(...);
+
+input clk;
+input sel;
+input [3:0] wa1;
+input [3:0] wa2;
+input [15:0] wd1;
+input [3:0] ra;
+output [15:0] rd;
+
+reg [15:0] mem [0:15];
+
+always @(posedge clk) begin
+	mem[wa1] <= sel ? wd1 : mem[wa1];
+	mem[wa2] <= mem[wa2];
+end
+
+assign rd = mem[ra];
+
+endmodule
+
+EOT
+
+hierarchy -auto-top
+proc
+opt_clean
+
+design -save start
+memory_map
+design -save preopt
+
+design -load start
+opt_mem_feedback
+select -assert-count 1 t:$memrd
+memory_map
+design -save postopt
+
+equiv_opt -assert -run prepare: :
-- 
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