From 5e641acc905a5c99d037378f6b7a481c43eb7de0 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 1 Aug 2014 03:57:37 +0200
Subject: Consolidated hana test benches into fewer files

for pf in test_simulation_{always,and,buffer,decoder,inc,mux,nand,nor,or,seq,shifter,sop,techmap,xnor,xor}; do
gawk 'FNR == 1 { printf("\n// %s\n",FILENAME); } { gsub("^module *", sprintf("module f%d_",ARGIND)); print; }' \
    ${pf}_*_test.v > $pf.v; ../tools/autotest.sh $pf.v; mv -v ${pf}_*_test.v Attic/; done;

..etc..
---
 tests/hana/test_simulation_techmap_tech.v | 143 ++++++++++++++++++++++++++++++
 1 file changed, 143 insertions(+)
 create mode 100644 tests/hana/test_simulation_techmap_tech.v

(limited to 'tests/hana/test_simulation_techmap_tech.v')

diff --git a/tests/hana/test_simulation_techmap_tech.v b/tests/hana/test_simulation_techmap_tech.v
new file mode 100644
index 000000000..60aeca5c1
--- /dev/null
+++ b/tests/hana/test_simulation_techmap_tech.v
@@ -0,0 +1,143 @@
+
+// test_simulation_techmap_and_19_tech.v
+module f1_TECH_AND18(input [17:0] in, output out);
+assign out = &in;
+endmodule
+
+module f1_TECH_AND4(input [3:0] in, output out);
+assign out = &in;
+endmodule
+
+// test_simulation_techmap_and_5_tech.v
+module f2_TECH_AND5(input [4:0] in, output out);
+assign out = &in;
+endmodule
+
+// test_simulation_techmap_nand_19_tech.v
+module f3_TECH_NAND18(input [17:0] in, output out);
+assign out = ~(&in);
+endmodule
+
+module f3_TECH_NAND4(input [3:0] in, output out);
+assign out = ~(&in);
+endmodule
+
+module f3_TECH_NAND2(input [1:0] in, output out);
+assign out = ~(&in);
+endmodule
+
+// test_simulation_techmap_nand_2_tech.v
+module f4_TECH_NAND18(input [17:0] in, output out);
+assign out = ~(&in);
+endmodule
+
+module f4_TECH_NAND4(input [3:0] in, output out);
+assign out = ~(&in);
+endmodule
+
+module f4_TECH_NAND2(input [1:0] in, output out);
+assign out = ~(&in);
+endmodule
+
+// test_simulation_techmap_nand_5_tech.v
+module f5_TECH_NAND18(input [17:0] in, output out);
+assign out = ~(&in);
+endmodule
+
+module f5_TECH_NAND4(input [3:0] in, output out);
+assign out = ~(&in);
+endmodule
+
+module f5_TECH_NAND2(input [1:0] in, output out);
+assign out = ~(&in);
+endmodule
+
+// test_simulation_techmap_nor_19_tech.v
+module f6_TECH_NOR18(input [17:0] in, output out);
+assign out = ~(|in);
+endmodule
+
+module f6_TECH_NOR4(input [3:0] in, output out);
+assign out = ~(|in);
+endmodule
+
+module f6_TECH_NOR2(input [1:0] in, output out);
+assign out = ~(|in);
+endmodule
+
+// test_simulation_techmap_nor_2_tech.v
+module f7_TECH_NOR18(input [17:0] in, output out);
+assign out = ~(|in);
+endmodule
+
+module f7_TECH_NOR4(input [3:0] in, output out);
+assign out = ~(|in);
+endmodule
+
+module f7_TECH_NOR2(input [1:0] in, output out);
+assign out = ~(|in);
+endmodule
+
+// test_simulation_techmap_nor_5_tech.v
+module f8_TECH_NOR18(input [17:0] in, output out);
+assign out = ~(|in);
+endmodule
+
+module f8_TECH_NOR4(input [3:0] in, output out);
+assign out = ~(|in);
+endmodule
+
+module f8_TECH_NOR2(input [1:0] in, output out);
+assign out = ~(|in);
+endmodule
+
+// test_simulation_techmap_or_19_tech.v
+module f9_TECH_OR18(input [17:0] in, output out);
+assign out = |in;
+endmodule
+
+module f9_TECH_OR4(input [3:0] in, output out);
+assign out = |in;
+endmodule
+
+// test_simulation_techmap_or_5_tech.v
+module f10_TECH_OR5(input [4:0] in, output out);
+assign out = |in;
+endmodule
+
+// test_simulation_techmap_xnor_2_tech.v
+module f11_TECH_XOR5(input [4:0] in, output out);
+assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
+endmodule
+module f11_TECH_XOR2(input [1:0] in, output out);
+assign out = in[0] ^ in[1];
+endmodule
+
+// test_simulation_techmap_xnor_5_tech.v
+module f12_TECH_XOR5(input [4:0] in, output out);
+assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
+endmodule
+module f12_TECH_XOR2(input [1:0] in, output out);
+assign out = in[0] ^ in[1];
+endmodule
+
+// test_simulation_techmap_xor_19_tech.v
+module f13_TECH_XOR2(input [1:0] in, output out);
+assign out = in[0] ^ in[1];
+endmodule
+
+// test_simulation_techmap_xor_2_tech.v
+module f14_TECH_XOR5(input [4:0] in, output out);
+assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
+endmodule
+module f14_TECH_XOR2(input [1:0] in, output out);
+assign out = in[0] ^ in[1];
+endmodule
+
+// test_simulation_techmap_xor_5_tech.v
+module f15_TECH_XOR5(input [4:0] in, output out);
+assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
+endmodule
+module f15_TECH_XOR2(input [1:0] in, output out);
+assign out = in[0] ^ in[1];
+endmodule
-- 
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