From 536ae16c3abcf3fef1dd14df8733bf51fa1bce1a Mon Sep 17 00:00:00 2001
From: Udi Finkelstein <github@udifink.com>
Date: Thu, 25 Oct 2018 02:37:56 +0300
Subject: Rename the generic "Syntax error" message from the
 Verilog/SystemVerilog parser into unique, meaningful info on the error. Also
 add 13 compilation examples that triggers each of these messages.

---
 tests/errors/syntax_err11.v | 3 +++
 1 file changed, 3 insertions(+)
 create mode 100644 tests/errors/syntax_err11.v

(limited to 'tests/errors/syntax_err11.v')

diff --git a/tests/errors/syntax_err11.v b/tests/errors/syntax_err11.v
new file mode 100644
index 000000000..f3cde9dfc
--- /dev/null
+++ b/tests/errors/syntax_err11.v
@@ -0,0 +1,3 @@
+module a;
+parameter integer real x=0;
+endmodule
-- 
cgit v1.2.3